JP2712245B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2712245B2
JP2712245B2 JP6086188A JP6086188A JP2712245B2 JP 2712245 B2 JP2712245 B2 JP 2712245B2 JP 6086188 A JP6086188 A JP 6086188A JP 6086188 A JP6086188 A JP 6086188A JP 2712245 B2 JP2712245 B2 JP 2712245B2
Authority
JP
Japan
Prior art keywords
oxide film
silicon oxide
opening
diffusion region
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP6086188A
Other languages
Japanese (ja)
Other versions
JPH01233725A (en
Inventor
裕明 秋山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6086188A priority Critical patent/JP2712245B2/en
Publication of JPH01233725A publication Critical patent/JPH01233725A/en
Application granted granted Critical
Publication of JP2712245B2 publication Critical patent/JP2712245B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device.

〔従来の技術〕[Conventional technology]

半導体装置の高集積化に伴ない、電極又は配線のコン
タクト部も微細化され、コンタクト部の段差被覆性を改
善するための手段が種々に検討されている。
With the increase in the degree of integration of semiconductor devices, the contact portions of electrodes or wirings have been miniaturized, and various means for improving the step coverage of the contact portions have been studied.

第2図(a),(b)は従来の半導体装置の製造方法
を説明するための工程順に示した半導体チップの断面図
である。
2 (a) and 2 (b) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device.

第2図(a)に示すように、n型シリコン基板1の一
主面にp型拡散領域2を選択的に設け、p型拡散領域2
を含む表面にホウ素及びリンを含む酸化シリコン膜(以
下BPSG膜と記す)3を堆積する。次に、p型拡散領域2
の上のBPSG膜3を選択的にエッチングしてコンタクト用
開口部4を設け、熱処理により開口部4のBPSG膜の端部
をリフローさせ滑らかにする。このとき、BPSG膜3より
不純物のアウトディフュージョンを生じて開口部4の拡
散領域2の表面に拡散し、不純物拡散層8を生ずる。
As shown in FIG. 2A, a p-type diffusion region 2 is selectively provided on one main surface of an n-type silicon substrate 1, and a p-type diffusion region 2 is formed.
A silicon oxide film (hereinafter, referred to as a BPSG film) 3 containing boron and phosphorus is deposited on the surface containing. Next, the p-type diffusion region 2
The BPSG film 3 is selectively etched to form a contact opening 4, and the end of the BPSG film in the opening 4 is reflowed and smoothed by heat treatment. At this time, out diffusion of the impurity is caused from the BPSG film 3 and diffused to the surface of the diffusion region 2 of the opening 4 to form the impurity diffusion layer 8.

次に、第2図(b)に示すように、開口部4を含む表
面にアルミニウム層7を堆積し、これを選択的にエッチ
ングして開口部4の拡散領域2とコンタクトする電極を
形成する。
Next, as shown in FIG. 2B, an aluminum layer 7 is deposited on the surface including the opening 4 and is selectively etched to form an electrode which is in contact with the diffusion region 2 of the opening 4. .

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上述した従来の半導体装置の製造方法は、コンタクト
用開口部の段差を軽減するための熱処理時にBPSG膜から
の不純物のアウトディフュージョンによりコンタクト開
口部の拡散領域の表面に生じた不純物拡散層によりコン
タクト抵抗がばらつくという欠点がある。また、素子の
微細化に伴う層間膜の平坦化が必須となるため、層間の
酸化膜のリン及びホウ素の濃度を高くする必要があり、
影響も大きくなる。
The above-described conventional method of manufacturing a semiconductor device is characterized in that the contact resistance is reduced by an impurity diffusion layer formed on the surface of the diffusion region of the contact opening due to out-diffusion of impurities from the BPSG film during a heat treatment for reducing the step of the contact opening. There is a disadvantage that it varies. In addition, since the planarization of the interlayer film due to the miniaturization of the element is indispensable, it is necessary to increase the concentration of phosphorus and boron in the oxide film between the layers,
The effect is also greater.

また、上記アウトディフュージョン防止の為に、気相
成長法等で比較的低温にて全面に酸化膜を形成すること
も出来るが、その後の開口部の段差軽減の為の熱処理を
しても、全面に酸化膜が覆っているのでBPSG膜の流動性
が抑えられ段差軽減は十分に出来ないという欠点があ
る。
Further, in order to prevent the above out diffusion, an oxide film can be formed on the entire surface at a relatively low temperature by a vapor phase growth method or the like. However, since the BPSG film is covered with an oxide film, the flowability of the BPSG film is suppressed, and there is a disadvantage that the step cannot be sufficiently reduced.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の半導体装置の製造方法は、一導電型半導体基
板の一主面に逆導電型の拡散領域を選択的に設ける工程
と、前記拡散領域を含む表面にホウ素及びリンを含む酸
化シリコン膜を設けて選択的にエッチングし前記拡散領
域のコンタクト用開口部を設ける工程と、前記開口部を
含む表面に薄い第1の酸化シリコン膜を堆積する工程
と、熱酸化法により前記開口部の前記拡散領域の表面に
第2の酸化シリコン膜を形成する工程と、前記第1の酸
化シリコン膜をエッチングして除去した後前記ホウ素及
びリンを含む酸化シリコン膜の開口部上端を滑らかにす
る工程と、前記第2の酸化シリコン膜を除去し前記開口
部を含む表面に金属膜を堆積しこれを選択的にエッチン
グして前記拡散領域とコンタクトする電極を形成する工
程とを含んで構成される。
The method of manufacturing a semiconductor device according to the present invention includes a step of selectively providing a diffusion region of the opposite conductivity type on one main surface of the semiconductor substrate of one conductivity type, and a step of forming a silicon oxide film containing boron and phosphorus on the surface including the diffusion region. Providing a contact opening in the diffusion region by selective etching, depositing a thin first silicon oxide film on a surface including the opening, and diffusing the opening in the opening by a thermal oxidation method. Forming a second silicon oxide film on the surface of the region, etching the first silicon oxide film and smoothing the upper end of the opening of the silicon oxide film containing boron and phosphorus; Removing the second silicon oxide film, depositing a metal film on the surface including the opening, and selectively etching the metal film to form an electrode in contact with the diffusion region. .

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明す
る。
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)〜(e)は本発明の一実施例を説明する
ための工程順に示した半導体チップの断面図である。
1 (a) to 1 (e) are sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

まず、第1図(a)に示すように、n型シリコン基板
1の一主面にホウ素イオンを加速エネルギー30keV、ド
ーズ量5×1015cm-2で選択的にイオン注入してp型拡散
領域2を形成する。次に、BPSG膜3を約0.7μmの厚さ
に堆積し、拡散領域2の上のBPSG膜3を選択的に異方性
エッチングしてコンタクト用開口部4を形成する。
First, as shown in FIG. 1 (a), boron ions are selectively implanted into one main surface of the n-type silicon substrate 1 at an acceleration energy of 30 keV and a dose of 5 × 10 15 cm −2 to perform p-type diffusion. Region 2 is formed. Next, a BPSG film 3 is deposited to a thickness of about 0.7 μm, and the BPSG film 3 on the diffusion region 2 is selectively anisotropically etched to form a contact opening 4.

次に、第1図(b)に示すように、CVD法により開口
部4を含む表面にノンドープの酸化シリコン膜5を厚さ
30nmに堆積する。このときのBPSG膜3の表面温度は400
℃程度であり、不純物のアウトディフュージョンは生じ
ない。
Next, as shown in FIG. 1B, a non-doped silicon oxide film 5 is formed on the surface including the opening 4 by the CVD method.
Deposit to 30 nm. At this time, the surface temperature of the BPSG film 3 is 400
C., and no out diffusion of impurities occurs.

次に、第1図(c)に示すように、水素の流量16/m
in及び酸素の流量11/minの混合雰囲気中で900℃の熱
酸化処理を行い、酸化シリコン膜5を通して開口部4の
拡散領域2の表面を酸化させて酸化シリコン膜6を60nm
の厚さに形成する。この酸化処理時には、酸化シリコン
膜5が表面に存在することで、開口部4の拡散領域2へ
のリン及びホウ素の拡散を防ぐことが出来る。
Next, as shown in FIG. 1 (c), the flow rate of hydrogen is 16 / m
A thermal oxidation process at 900 ° C. is performed in a mixed atmosphere with a flow rate of in and oxygen of 11 / min to oxidize the surface of the diffusion region 2 of the opening 4 through the silicon oxide film 5 to make the silicon oxide film 6 60 nm.
Formed to a thickness of During this oxidation treatment, the diffusion of phosphorus and boron into the diffusion region 2 of the opening 4 can be prevented by the presence of the silicon oxide film 5 on the surface.

次に、第1図(d)に示すように、弗酸系のウェット
エッチングにより酸化シリコン膜5を除去する。この時
熱酸化によって形成した酸化シリコン膜6もエッチング
されるが、60nmと厚くつけてあり、気相成長法で形成し
た酸化シリコン膜5よりもエッチングレートが遅いので
30〜40nm程度は残すことが出来る。その後900℃の窒素
雰囲気中で30分間熱処理し、開口部4の段差を軽減す
る。
Next, as shown in FIG. 1D, the silicon oxide film 5 is removed by hydrofluoric acid-based wet etching. At this time, the silicon oxide film 6 formed by thermal oxidation is also etched. However, since the silicon oxide film 6 is formed as thick as 60 nm and has a lower etching rate than the silicon oxide film 5 formed by the vapor deposition method,
About 30 to 40 nm can be left. Thereafter, a heat treatment is performed for 30 minutes in a nitrogen atmosphere at 900 ° C. to reduce the step of the opening 4.

次に、第1図(e)に示すように、弗酸系のウェント
エッチングにより酸化シリコン膜6を除去し、開口部4
を含む表面にスパッタ法にてアルミニウム層を1μmの
厚さに堆積し、これを選択的にエッチングしてアルミニ
ウム電極配線7を形成する。
Next, as shown in FIG. 1 (e), the silicon oxide film 6 is removed by hydrofluoric acid-based wet etching, and the opening 4 is removed.
An aluminum layer is deposited to a thickness of 1 μm on the surface including the above by sputtering, and this is selectively etched to form an aluminum electrode wiring 7.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、コンタクト用開口部を
含むBPSG膜の表面に比較的低温にて(400℃)ノンドー
プの第1の酸化シリコン膜を形成し、しかる後開口部の
拡散領域の表面を熱酸化して第2の酸化シリコン膜を形
成した後第1の酸化シリコン膜を除去し、残った第2の
酸化シリコン膜をマスクとして開口部の段差を軽減する
熱処理を行うことにより、BPSG膜からの不純物のアウト
ディフュージョンによる拡散領域の汚染を防止すること
ができ、コンタクト抵抗のばらつきを無くすことができ
る効果がある。
As described above, according to the present invention, the non-doped first silicon oxide film is formed at a relatively low temperature (400 ° C.) on the surface of the BPSG film including the contact opening, and then the surface of the diffusion region of the opening is formed. Is thermally oxidized to form a second silicon oxide film, the first silicon oxide film is removed, and a heat treatment is performed using the remaining second silicon oxide film as a mask to reduce the step of the opening. There is an effect that contamination of the diffusion region due to out diffusion of impurities from the film can be prevented, and variations in contact resistance can be eliminated.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(e)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第2図
(a),(b)は従来の半導体装置の製造方法を説明す
るための工程順に示した半導体チップの断面図である。 1……n型シリコン基板、2……p型拡散領域、3……
BPSG膜、4……開口部、5,6……酸化シリコン膜、7…
…アルミニウム電極配線、8……不純物拡散層。
1 (a) to 1 (e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) show a conventional method of manufacturing a semiconductor device. FIG. 4 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining the method. 1 .... n-type silicon substrate, 2 .... p-type diffusion region, 3 ....
BPSG film, 4 ... opening, 5, 6 ... silicon oxide film, 7 ...
... aluminum electrode wiring, 8 ... impurity diffusion layer.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】一導電型半導体基板の一主面に逆導電型の
拡散領域を選択的に設ける工程と、前記拡散領域を含む
表面にホウ素及びリンを含む酸化シリコン膜を設けて選
択的にエッチングし前記拡散領域のコンタクト用開口部
を設ける工程と、前記開口部に含む表面に薄い第1の酸
化シリコン膜を堆積する工程と、熱酸化法により前記開
口部の前記拡散領域の表面に第2の酸化シリコン膜を堆
積する工程と、前記第1の酸化シリコン膜をエッチング
して除去した後前記ホウ素及びリンを含む酸化シリコン
膜の開口部上端を滑らかにする工程と、前記第2の酸化
シリコン膜を除去し前記開口部を含む表面に金属膜を堆
積しこれを選択的にエッチングして前記拡散領域とコン
タクトする電極を形成する工程とを含むことを特徴とす
る半導体装置の製造方法。
1. A step of selectively providing a diffusion region of the opposite conductivity type on one main surface of a semiconductor substrate of one conductivity type, and selectively providing a silicon oxide film containing boron and phosphorus on a surface including the diffusion region. Providing a contact opening in the diffusion region by etching, depositing a thin first silicon oxide film on a surface included in the opening, and forming a first silicon oxide film on the surface of the diffusion region in the opening by a thermal oxidation method. Depositing a second silicon oxide film, etching the first silicon oxide film and then smoothing the upper end of the opening of the silicon oxide film containing boron and phosphorus; Removing the silicon film, depositing a metal film on the surface including the opening, and selectively etching the metal film to form an electrode in contact with the diffusion region. Method.
JP6086188A 1988-03-14 1988-03-14 Method for manufacturing semiconductor device Expired - Lifetime JP2712245B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6086188A JP2712245B2 (en) 1988-03-14 1988-03-14 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6086188A JP2712245B2 (en) 1988-03-14 1988-03-14 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH01233725A JPH01233725A (en) 1989-09-19
JP2712245B2 true JP2712245B2 (en) 1998-02-10

Family

ID=13154592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6086188A Expired - Lifetime JP2712245B2 (en) 1988-03-14 1988-03-14 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2712245B2 (en)

Also Published As

Publication number Publication date
JPH01233725A (en) 1989-09-19

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