JP2712197B2 - Effect adding device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an effect adding device that performs amplitude modulation on an input waveform signal using a low-frequency signal to obtain a tremolo effect. [Prior Art] Conventionally, in order to obtain better sound effects in response to higher performance of audio equipment, effect adding devices for electronically adding various effects to musical sound signals and the like have been developed. Among these effects, the tremolo effect is obtained by amplitude-modulating the original sound using a low-frequency generator (LFO) that generates a low-frequency waveform having a predetermined period. FIG. 10 is a block diagram of a conventional tremolo effect adding circuit. In the figure, an input signal is input to two voltage-controlled amplifiers (VCA) 1 and 2, and the volume is controlled to obtain a stereo right output and left output. these
VCA1 and VCA2 are controlled by output signals from analog adders 3 and 4, respectively. The non-inverting input terminals of the analog adders 3 and 4 are supplied with a constant voltage serving as a reference for modulation, the inverting input terminals receive the output of a low-frequency generator (LFO) 5, and one of the outputs via a volume 7. The other is supplied via a phase inversion circuit 6 and a volume 8. The LFO 5 is provided with a volume 9 that makes the transmission frequency variable and changes the tremolo speed (TMSPED). In this tremolo effect adding circuit, one of the low frequency signals is supplied from the LFO 5 to the analog adder 3 via the volume 7, and the other is inverted by the phase inverting circuit 6 for the other, and the analog adder 4 is Supplied to The outputs of the analog adders 3 and 4 are supplied to the VCAs 1 and 2 as control voltages that fluctuate around the modulation reference and that have inverted phases. These VCAs 1 and 2 are subjected to amplitude modulation in accordance with control voltages from the analog adders 3 and 4, and stereo outputs of the tremolo effect are obtained as right and left outputs, respectively. Tremolo speed is volume 9
And the depth of the tremolo can be changed by the volumes 7, 8. [Problems to be Solved by the Invention] However, since the conventional tremolo effect adding circuit uses an analog circuit, there is a disadvantage that noise is easily generated and a natural sound effect cannot be obtained.
In addition, the analog circuit requires twice as many analog elements as a stereo circuit, and has drawbacks such as durability and aging. In recent years, there is a device that can add an effect such as a reverberation effect by using a delay element in real-time processing by improving digital signal processing technology and increasing the speed and density of a logic element. There is no effect adding device that performs amplitude modulation by using the above to obtain a tremolo effect. SUMMARY OF THE INVENTION It is an object of the present invention to provide a tremolo effect with good sound quality for a stereo output by a simple configuration with a small number of hardware. [Means for Solving the Problems] The present invention provides waveform memory means for storing low-frequency waveform data to be generated, modulation depth data for determining modulation depth, and modulation speed data for determining modulation speed. And input processing for inputting input signal data sampled at a predetermined cycle, and generating a read address to be provided to the waveform memory means based on the modulation speed data stored in the data memory means. A read address generation process, a read process for reading low-frequency waveform data from the waveform memory unit based on the read address generated in the read address generation process, a modulation depth data stored in the data memory unit, and the input process. Multiplication processing for multiplying the input signal data input by According multiplication result and a second multiplying a low-frequency waveform data read by the reading process
Multiplication processing, inversion processing for inverting the low-frequency waveform data read in the above-described reading processing, and multiplying the low-frequency waveform data inverted by the inversion processing by the multiplication result obtained in the first multiplication processing. A third multiplication process, a first subtraction process of subtracting the result of the multiplication by the second multiplication process from the input signal data from the input process and outputting the result, and a third subtraction process based on the input signal data from the input process. A second subtraction process of subtracting and outputting a multiplication result obtained by the multiplication process of
In a digital signal processing in a time-division manner within one sampling period to obtain an amplitude-modulated output. [Operation] The operation of the present invention is as follows. A read address to be given to the waveform memory means is generated based on the modulation speed data stored in the data memory means, and the low frequency waveform data is read from the waveform memory means by the read address. Then, the modulation depth data stored in the data memory means is multiplied by the input signal data sampled at a predetermined cycle to obtain a first multiplication result. The first multiplication result is multiplied by the read low-frequency waveform data to obtain a second multiplication result, while the read low-frequency waveform data is inverted, and the inverted low-frequency waveform data is inverted. And the first multiplication result are further multiplied to obtain a third multiplication result. Then, the second multiplication result is subtracted from the input signal data and output, and the third multiplication result is subtracted from the input signal data and output. These series of processes are executed by digital subtraction processing in a time-division manner within one sampling period to obtain an amplitude-modulated output. As a result, a stereo sound output with the tremolo effect is obtained. Therefore, since the tremolo effect is obtained by digital arithmetic processing, noise is less generated than when an analog circuit is used, and a natural stereo sound effect can be obtained. In addition, since a series of these processes is performed by one arithmetic unit in a time-division manner within one sampling period, an increase in hardware is relatively small, and the configuration can be simplified. Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a principle block diagram of a tremolo effect adding device according to one embodiment of the present invention. In the figure, a tremolo effect adding device executes arithmetic processing using low-frequency waveform data (1.0 to 0) output from a low-frequency generator (LFO) 11 described later, and performs stereo processing to which a tremolo effect is added. Get the output. That is, the input signal data is multiplied by a value (TMDPTH) that determines the tremolo depth by the multiplier 12, and the multiplied output is provided to the two multipliers 13 and 14.
One multiplier 13 multiplies the output of the multiplier 12 by the output of the LFO 11, and the other multiplier 14 adds “1” to the output of the multiplier 12 by the adder 15 to a value obtained by changing the sign of the output of the LFO 11. The added outputs are multiplied and supplied to adders 16 and 17, respectively. That is, one multiplier 13 is provided with the output of the LFO 11, and the other multiplier 14 is provided with a value obtained by changing the phase of the output of the LFO 11 (a value obtained by inverting the phase). Multiplied. The adders 16 and 17 are respectively multipliers
The values obtained by changing the signs of the outputs 13 and 14 and the input signal data are added, and the added outputs become the stereo right output and left output. LFO11 is a value that determines the tremolo speed (TMS
PED) is given, and this value changes the transmission frequency. FIG. 2 is a block diagram showing an example of the low frequency generator (LFO) 11 of FIG. In the figure, a low-frequency generator 11
Has a memory 18 for storing an output waveform, and first and second counters 19 and 20. The memory 18 stores low-frequency modulation waveform data to be generated, for example, as a cosine wave or a triangular wave, with a value of 0 to 1.0 for one cycle. The first counter 19 is supplied with a value (TMSPED) that determines the tremolo speed as load data. This first counter 19
A clock CK is supplied to the clock terminal from a clock generator (not shown), and a subtraction count is performed to perform a borrow.
Is issued, the load data (TMSPED) is read. The subtraction count output of the first counter 19 is supplied to the divider 21, and the borrow output thereof is supplied to the clock terminal of the second counter 20. The second counter 20 performs an increment count for each borrow output of the first counter 19,
The read addresses up to are output. That is, the first
And the second counters 19 and 20 constitute address generating means. The memory 18 is provided with the read address of the second counter 20 and the second counter 20
The read address obtained by adding “1” to the read address of the adder 22 is given. The waveform data read from the second counter 20 at the read address given to the memory 18 is sent to the first multiplier 23 and from the adder 22 to the memory 18.
The waveform data read at the read address given to the second multiplier 24 is given to the second multiplier 24, respectively. On the other hand, the divider 21 receives TMSPED and outputs the output of the first counter 19.
The dividing power calculated by TMSPED is divided into a first divider 23 and an adder.
Supply 25. The adder 25 adds the value “1” obtained by changing the sign of the output of the divider 21, and supplies the added output to the second multiplier 24. The outputs of the first and second multipliers 23 and 24 are added by an adder 26, and the added output is output as waveform data (LFOH). That is, the divider 21, the first
And the second multipliers 23 and 24 and the adders 25 and 26 constitute waveform data interpolation means. The operation of the tremolo effect adding device having the above configuration will be described. First, the operation of the low frequency generator 11 of FIG. 2 will be described with reference to the waveform diagram of FIG. At a certain time, the first counter 19
When TMSPED is loaded, the counter is sequentially decremented every clock CK, and when borrow is output, TMSPED is
Is loaded. Accordingly, as shown in FIG. 3, the output of the first counter 19 (C1 output) repeats a waveform that sequentially decreases from the value of TMSPED to “0” every clock. The output of the divider 21 (division calculation force) is calculated by the first counter 19.
In order to divide the output by TMSPED, a waveform that sequentially decreases from "1" to "0" every clock is repeated as shown in FIG. The second counter 20 performs an addition count every time a borrow output is given from the first counter 19,
The added output (C2 output) increases stepwise by "1" as shown in FIG. The output of the adder 22 is a value obtained by adding “1” to the C2 output. Memory from second counter 20
The waveform data read at the read address given to 18 is multiplied by the output of the divider 21 by the first multiplier 23,
The waveform data read from the adder 22 at the read address given to the memory 18 is multiplied by the output of the adder 25 by the second multiplier 24. The outputs of the first and second multipliers 23 and 24 are added by an adder 26. That is,
As shown in FIG. 4, the value of a _n of waveform data read out by the read address supplied from the second counter 20 in the memory 18, is read from the adder 22 at the read address given to the memory 18 The obtained waveform data is set to a _{n + 1} and the divider 21
Is h, the output of the adder 25 is 1-h.
Outputs of the first and second multipliers 23 and 24, respectively h · a _n
And (1-h) · an _{+ 1} , and the output an _{+ h} of the adder 26 is
It is shown by the following equation. _{a n + h = h · a} n + (1-h) · a n + 1 the a _{n + h,} as shown in FIG. 4, waveform data a _n and a _{n + 1} to be read by the address n and n + 1 Corresponds to an operation of interpolating between the two at the ratio of 1-h and h. That is, every time a borrow is output from the first counter 19, the waveform data of the memory 18 which differs by one address is sequentially interpolated, and an LFOH (an _{+ h} ) output indicated by a dotted line in FIG. 3 is obtained. This LFOH output is TM
Varies with SPED. That is, as TMSPED increases, the borrow output interval of the first counter 19 increases, and the period of the output waveform of LFOH increases. Cycle becomes shorter. Next, the operation of the tremolo effect adding device of FIG. 1 will be described. First, the input signal data is multiplied by TMDPTH by the multiplier 12, and the tremolo depth is determined. The output of the multiplier 12 is provided to multipliers 13 and 14, which multiply the output of the LFO 11 and the output of the adder 15 obtained by inverting the output of the LFO 11, respectively. And multiplier 1
The outputs of 3 and 14 are given to adders 16 and 17, respectively, and the values obtained by changing the signs of the adders 16 and 17 and the input signal data are added to obtain stereo right and left outputs, respectively. . That is, the amplitude modulation is performed by the multipliers 13 and 14 in accordance with the output of the LFO 11, the amplitude modulation output is added to the input signal data by the adders 16 and 17, and a sound with a stereo tremolo effect is obtained. Specific Configuration FIG. 5 is an overall block diagram of an embodiment showing a specific configuration of the tremolo effect adding device based on the principle of FIGS. 1 and 2. This specific configuration is described in FIG. 1 and FIG.
A tremolo effect adding device that executes a function corresponding to the block diagram in the drawing is realized by a digital signal processing LSI (DSP) or the like. In the figure, the program memory 31
A memory that stores a predetermined program, and supplies an output to the control circuit 33 using an output of the program counter 32 that is incremented by a clock signal CK2 supplied from a clock generator (not shown) as an address. The control circuit 33 controls the timing and execution of data transfer and operation between each register and the memory, which will be described later, and the supply of data to the program counter 32 by the flip-flop 34, based on the output contents of the program memory 31. The flip-flop 34 changes the state by the external sampling clock CK1, supplies the signal F to the control circuit zone 33,
From 33, a reset signal is applied to flip-flop. The clock signal CK supplied to the program counter 32 is given a clock that is sufficiently faster than the external sampling clock CK1 supplied to the flip-flop 34. The timbre parameter memories 35 and 36 store timbre parameters for adding a sound effect, constants used for calculation, and part of waveform data, as described in detail later. The register A37 and the register B38 store data supplied from the timbre parameter memories 35 and 36 or each register and supplied to the arithmetic circuit 39 and the multiplier circuit 40 for performing addition and subtraction. The operation results of the operation circuit 39 and the multiplication circuit 40 are supplied to a register C41, and the output of the register C41 is supplied to each unit via the operation circuit 39 or the internal bus 42. The waveform data memory 43 is a memory for storing waveform data. The write and read addresses are supplied by an address register 44, and the write and read data are stored in a data register 45. Above data register 45
Are bidirectional, and data transfer is performed through the internal bus 42, respectively. This waveform data memory 43
Is used to obtain a delay effect, and is not used in the tremolo effect of the present invention. The input register 46 stores digital input signal data from a sound source (not shown) and supplies it to each unit. The right output register 47 and the left output register connected to the internal bus 42
Numeral 48 stores right output data and left output data to which predetermined arithmetic processing is performed on input data and to which a tremolo effect is added in stereo, and outputs the stored data to the outside. The outputs of the right output register 47 and the left output register 48 are output as a sound to which a tremolo effect is added via a low-pass filter, an output amplifier, and the like (not shown). FIG. 6 shows the internal structure of the timbre parameter memory 35 of FIG. 5, in which LFO waveform data corresponding to the waveform data stored in the memory 18 of FIG. 2 at addresses 0 to N, and addresses N + 1 and N + 2. WAVE1 and WAVE2 corresponding to the contents of the audio waveform data are stored, respectively. FIG. 7 shows the internal structure of the timbre parameter memory 36 of FIG. 5. TMDTH corresponding to the content of the tremolo effect depth at address 0, and tremolo content corresponding to the speed of the LFO at address 1. TMSPED, second at addresses 2 and 3
C1 and C1 corresponding to the first and second counters 19 and 20 in FIG.
2, N corresponding to the number of LFO waveform data (upper limit value of C2) at address 4, H corresponding to the content of the division result of the divider 21 in FIG. 2 at address 5, and the adder of FIG. 2 at address 6 The LFOH corresponding to the content of the LFO output, which is the addition output of 26, is stored. Next, the operation of the effect adding apparatus configured as described above will be described in detail with reference to the drawings. Flowchart shown in FIG. 8, in step S ₁ of FIG. 8 illustrates the overall processing operation of the effect adding apparatus, it determines the state of the flip-flop 34 (F) is "1" or not is made . That is, when F = 1, the signal is supplied to the control circuit 33, whereby a count start signal is supplied from the control circuit 33 to the program counter 32. The program counter 32 starts increasing the count in synchronization with the clock signal CK2, and supplies an address to the program memory 31. The content of the program memory 31 is a control circuit
This is supplied to 33, which controls each part. In step S _2, a reset signal from the control circuit 33 is supplied to the flip-flop 34, flip-flop 34 is reset (F = 0). That is, the processing of each unit is executed in synchronization with the external sampling clock CK1. Next, in step S _3, the processing of the low-frequency generator (LFO) is performed will be described in detail later. Then, in step S _4, writes the value of the input register 46 to the wave1 (wave1 ←
Value of the input register), then in step S _5, wave1
Is multiplied by TMDPTH and written to WAVE2 (WAVE2 ← WAVE
1 x TMDPTH). In step S ₄ and S ₅ are first view corresponds to the process of multiplying TMDPTH in multiplier 12 to the input signal data. Next, in step S _6, WAV from WAVE1
The value obtained by subtracting the value obtained by multiplying E2 by LFOH is output to the right output register 47.
Transfer (right output register ← WAVE1 ← WAVE2 × LFOH), also in step S _7, from wave1 to WAVE2 (1-LFO
H) is transferred to the left output register 48 (left output register ← WAVE1 ← WAVE2 × (1-LFOH)). In step S ₆ the first diagram, the output of LFO11 the output of the multiplier 12 is multiplied by the multiplier 13, and outputs the sum as the value obtained by changing the sign of the multiplication of the input signal data in the adder 16 that in the corresponding, also the first drawing step S _7, the value obtained by inverting the output of LFO11 the output of the multiplier 12 and multiplied by multiplier 14, a value obtained by changing the sign of the multiplied value and the input signal data Adder 17
Corresponds to adding and outputting. Then, after the process of step S _7, the same processing is repeated every sampling clock returns to step S ₁ again. The flowchart shown in FIG. 9 shows the processing operation of the LFO. In Step S ₁₁ in the figure, stores the value obtained by subtracting "1" from C1 to C1 (C1 ← C1-1). That is, in FIG. 2, this corresponds to the case where the first counter 19 performs the subtraction counting for each sampling clock.
Next, in step S _12, C1 is determined whether "0" is made. That is, when C1 = 0, step
In S _13, stores the value taking the AND of a value obtained by incrementing the C2 and N to C2 (C2 ← (C2 + 1 ) ∩N), also stores TMSPED in C1 (C1 ← TMSPED). Logical operation of the step S _13, when the value obtained by incrementing the C2 does not exceed the number of LFO waveform data, the increment value is the content of C2, the first value (N = 0) when it exceeds the value Indicates that the content is C2. After processing or step S ₁₃ when it is not C1 = 0 in step S _12, in step S _14, by dividing the C1 in TMSPED, and stores the division value H (H ← C1 / TMSPED) . That is,
In Step S _12, S _13, the processing of S ₁₄ is a second view, the first
When the value of the counter 19 becomes "0", a borrow is output, the second counter 20 is counted up by this borrow output, and the TMSPED is again supplied to the first counter 19.
Is loaded, and when the value of the first counter 19 is not “0”, the output of the first counter 19 is
Corresponds to dividing by ED. Next, in step S _15, a multiplication value of the multiplication value of the waveform data and the H address indicated by C _2, and the waveform data indicated by the value obtained by adding "1" to the C2 and (1-H) And store the added value in LFOH (LFOH ← H × [C2] + (1-H) × [(C2 +
1) ∩N]). That is, the process of step S _15, the second
A value obtained by multiplying the value read from the memory 18 by using the output of the counter 20 as an address and the output of the divider 21 by a first multiplier 23, and the output of the adder 22 as an address
The multiplied value obtained by multiplying the value read from 18 and the output of the divider 21 by the first multiplier 23 and the value read from the memory 18 using the output of the adder 22 as an address This corresponds to adding an output and a multiplied value obtained by multiplying the output by the second multiplier 24 in the adder 26 to obtain LFOH. That is, in step S ₁₁ ~ step S ₁₅ of FIG. 9, LFOH is output as a low frequency waveform to perform the functions of the respective parts of FIG. 2. As described above, according to the present embodiment, the input signal data is multiplied by the low-frequency waveform output obtained at each sampling cycle by the digital arithmetic processing and the waveform output obtained by changing the phase of this waveform output, and the amplitude-modulated stereo signal is output. A tremolo output can be obtained. Therefore, noise is reduced as compared with the case where an analog circuit is used because of digital arithmetic processing, and a natural tremolo effect can be obtained. Further, to obtain a tremolo stereo output, the configuration can be simplified without an increase in hardware, and further, there is no problem such as durability or aging unlike an analog circuit. Note that, in the present invention, the waveform of the LFO 11 can be arbitrary, and it is sufficient that a waveform for at least one cycle is output. As the waveform of the LFO 11, for example, a cosine wave or a triangular wave can be used, and a waveform that generates a smooth waveform when generated continuously is preferable. The LFO 11 only needs to be able to obtain low-frequency waveform data at least for each sampling period. For example, the LFO 11 stores a waveform to be generated as time information, angle information, and change amount information, and is not limited to arithmetic processing. Further, in the above embodiment, the stereo tremolo effect is obtained, but the present invention can be applied to monaural. [Effects of the Invention] As described above, according to the present invention, a series of operations such as reading of low-frequency waveform data, multiplication of input signal data sampled at a predetermined cycle with the read low-frequency waveform data, and change of modulation depth are performed. The tremolo effect processing for the stereo output is performed in a time-division manner within the sampling period, so there is less noise than in the case of using an analog circuit, and a natural tremolo effect with good sound quality is obtained for the stereo output. Since the above-described series of processing is performed in a time-division manner by one arithmetic unit, the configuration is simplified without an increase in hardware.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a principle block diagram of an effect adding device showing the principle of the present invention, FIG. 2 is a block diagram showing an example of a waveform generator (LFO) of FIG. 1, and FIG. FIG. 4 is a diagram illustrating a waveform generated by the waveform generator of FIG. 2, FIG. 4 is a diagram illustrating that waveform data obtained by the waveform generator of FIG. 2 is obtained by interpolation, and FIG. 5 is an embodiment of the present invention. FIG. 6 is a block diagram showing a specific configuration of an effect adding apparatus according to an example, FIG. 6 is a diagram showing an internal configuration of a timbre parameter memory 35 in FIG. 5, and FIG. 7 is an internal configuration of a timbre parameter memory 36 in FIG. Fig. 8 is a flowchart showing the overall processing operation of the effect adding apparatus of the embodiment, Fig. 9 is a flowchart showing the processing operation of the waveform generator of Fig. 8, and Fig. 10 is a conventional tremolo effect adding. It is a block diagram of a circuit. 11 ... low frequency generator, 12, 13, 14 ... multiplier, 15, 16, 17 ... adder, 18 ... memory, 19 ... first counter, 20 ... second counter, 21 ... Divider, 22, 25, 26 Adder, 23 First multiplier, 24 Second multiplier, 31 Program memory, 35, 36 Tone parameter memory, 39 ... arithmetic circuit, 40 ... multiplication circuit.

Claims (1)

(57) [Claims] Waveform memory means for storing low-frequency waveform data to be generated; data memory means for storing modulation depth data for determining the modulation depth and modulation speed data for determining the modulation speed; An input process for inputting the input signal data, and a read address generation process for generating a read address to be given to the waveform memory unit based on the modulation speed data stored in the data memory unit;
A read process for reading low-frequency waveform data from the waveform memory unit using the read address generated in the read address generation process; a modulation depth data stored in the data memory unit; and an input signal input by the input process. A first multiplication process for multiplying the data by the data; a second multiplication process for multiplying the multiplication result by the first multiplication process with the low-frequency waveform data read in the read process; An inverting process for inverting the low-frequency waveform data read and read; a third multiplying process for multiplying the inverted low-frequency waveform data by the inverting process with the result of the multiplication by the first multiplication process; A first subtraction process for subtracting the multiplication result of the second multiplication process from the input signal data from the process and outputting the result, and an input signal from the input process. A second subtraction process to output the subtracting a multiplication result by the third multiplication processing from the data, the 1
And a calculating means for executing the digital calculation processing in a time-division manner within the sampling period to obtain an amplitude-modulated output.