JP2707017B2 - Capacitive element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitive element in a semiconductor integrated circuit device, and more particularly to a structure of a capacitive element having high speed and high density.

[0002]

2. Description of the Related Art A semiconductor integrated circuit device requires a resistor or a capacitor as a passive element together with a MOSFET or a bipolar transistor as an active element.
Among them, demands for high-performance capacitive elements have been increasing as the applications of semiconductor integrated circuit devices have expanded. Specifically, for (I) high integration, it is required that a large capacity can be realized in a small area, and for (II) high speed operation, the frequency dependence of the capacitance should be small.

In general, a capacitor element has a structure in which an insulating layer is sandwiched between electrodes. For the above (I), the insulating layer is made thinner, and for the above (II), the resistance of the electrode is reduced. It was necessary to reduce it. However, a structure that satisfies both the conditions (I) and (II) has not been realized. For example, the structure shown in FIGS. 6 and 7 has been proposed to realize the item (I).

FIG. 6 shows a case where a thermal oxide film 2 of single crystal silicon is used as an insulating film layer, and the film thickness is 10 nm.
Although the capacity per unit area can be increased because the layer can be made as thin as possible, one of the electrodes is single-crystal silicon 3,
Since the other is polycrystalline silicon 1, it was difficult to reduce the resistance.

FIG. 7 shows a case in which an oxide film 5 of polycrystalline silicon is used as an insulating film layer. One of the electrodes is made of a metal layer 4 to reduce the resistance. Due to the polycrystalline silicon 7, a sufficiently high speed could not be achieved. In FIG. 7, reference numeral 6 denotes an interlayer insulating film;
Is an oxide film and 9 is a silicon substrate.

On the other hand, FIG. 8 shows a conventional structure in which both electrodes are made of low-resistance metal wiring in order to realize the high-speed operation of the item (II). FIG. 8 shows a case where low-resistance metal layers 4 ₁ and 4 ₂ are used as electrodes using a multi-layer metal wiring technique of two or more layers. As the insulating film layer in the case is used the insulating film 5 ₁ by ordinary plasma CVD or thermal CVD method used in the multilayer wiring technology, current of the insulating film - shows an example of the voltage characteristics in FIG. FIG. 9 shows characteristics 22 to 24 when the insulating film is formed at 500 ° by a CVD method, an ozone TEOS (tetraethoxysilane) method, and a plasma TEOSCVD method, respectively.

[0007]

As described above, in the above-described structures of FIGS. 6 and 7, a large capacity can be realized because the insulating film layer can be made thin, but both electrodes are not reduced in resistance.
There is a disadvantage that a sufficiently high speed cannot be achieved.

In the structure shown in FIG. 8, the insulating film 5 is formed by an ordinary plasma CVD or thermal CVD method as the insulating film layer.
_{Although 1} is used, these films are more fragile than the thermal oxide film of single crystal silicon, and as shown in FIG. It is difficult to use it in a thick film state. For this reason, there is a disadvantage that the capacity per unit area is small, which is not suitable for high integration. In addition, since the above-mentioned CVD methods all have a forming temperature of about 400 ° C., when they are formed on an aluminum alloy-based metal wiring, deformation (migration) of aluminum occurs due to heat, and as a result, a withstand voltage failure of the capacitive element and the like may occur. As a result, yield and reliability deteriorate. For these reasons, higher performance capacitive elements have been demanded.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a capacitor having both high speed and high density.

[0010]

That is, in the capacitive element of the present invention, the electrodes are made of metal for realizing high-speed operation, and the insulator layer between the electrode metals is formed by bias ECR plasma for realizing high density. It is intended to achieve a thin layer by forming a high-quality insulating film formed at a low temperature by a CVD method. According to another aspect of the present invention, the reliability is further improved by providing a high melting point metal or a high melting point metal compound layer at the interface between the electrode metal and the insulating film.

[0011]

In the present invention, by using an insulating film formed by the bias ECR plasma CVD method for the insulating layer of the capacitor element, a film having a higher quality than the insulating film formed by the ordinary CVD method can be obtained, so that the thickness can be reduced. Also, this bias E
Since the CR plasma CVD method can be formed at a low temperature of 200 ° C. or less, migration of metal wiring can be reduced, and the yield and reliability as a capacitor can be improved. Further, in another aspect of the present invention, migration of the metal wiring can be further reduced by using a high melting point metal or a high melting point metal compound for a portion of the metal wiring in contact with the insulating film.

[0012]

FIG. 1 is a structural sectional view showing a first embodiment of a capacitive element according to the present invention. In the figure, reference numeral 10 denotes an insulating layer formed on a silicon substrate 16;
0 is a first metal wiring layer selectively formed on
Reference numeral 2 denotes a second metal wiring layer. These metal wiring layers 11,
Reference numeral 12 denotes an aluminum alloy system (for example, an alloy of trace amounts of Cu, Si and aluminum) used in a normal LSI manufacturing process.

Reference numeral 13 denotes the first and second metal wiring layers 1
And an insulating film provided between the first and second insulating films.
In order to form a capacitor at a desired position on the first metal wiring layer 11, the interlayer insulating film 14 is removed by etching to form an opening 15, and a bias ECR plasma C is formed thereon.
It is a silicon oxide film or a silicon nitride film formed by the VD method. In this bias ECR plasma CVD method, an insulating film can be formed at a low temperature of 200 ° C. or less and a low pressure of 10 ⁻⁵ to 10 ⁻³ Torr, so that a high-quality oxide film or nitride film close to a silicon single crystal thermal oxide film is obtained. be able to. FIG. 2 shows an example of the current-voltage characteristics of the oxide film.

FIG. 2 shows characteristics 21 of an oxide film formed by a bias ECR plasma CVD method in comparison with other insulating films. FIG. 2 shows that the conventional CV shown in FIG.
It shows a lower current even at a higher electric field than the oxide film obtained by the method D, and it is clear that the insulating property is excellent. Also, since the formation temperature is 200 ° C. or less, migration of the aluminum-based metal wiring during the formation of the insulating film is unlikely to occur.
This has an advantage that deterioration in withstand voltage as a capacitor element hardly occurs.

FIG. 3 is a structural sectional view showing a second embodiment of the present invention. This embodiment is different from that of FIG. 1 in that the first and second metal wiring layers 11 and 12 constituting the electrodes of the capacitive element and the interface between the insulating film 13 and the refractory metal layers 17 and 12 are provided respectively. 18 or a high melting point metal compound layer. The same reference numerals in the drawings indicate the same or corresponding parts.

According to the structure of this embodiment, a high melting point metal such as titanium or tungsten or a high melting point metal compound such as titanium nitride is less likely to be deformed by heat than an aluminum alloy. In combination with the feature that the insulating film 13 can be formed at a low temperature, a feature that a higher-performance capacitive element can be formed is provided.

The present invention is not limited to the embodiment shown in FIG. 3, but may be applied to the first metal wiring layer 11 or the second metal wiring layer 1.
The same effect can be obtained by providing a high melting point metal or a high melting point metal compound layer in a portion in contact with at least one of the insulating layers 13. It is also clear that the entire metal wiring layer may be made of a high melting point metal.

FIG. 4 is a cross-sectional view of main steps showing an example of a manufacturing method for realizing the structure of the first embodiment of the present invention. In this embodiment, as shown in FIG. 4A, after a first metal wiring layer 11 is selectively formed on an insulating layer 10, an interlayer insulating film 14 is formed by a CVD method or the like. Next, as shown in FIG. 4B, the interlayer insulating film 1 in the region 20 where the capacitive element is formed is formed.
After selectively removing 4 to form an opening 15, an insulating film 13 such as a silicon oxide film used for a capacitive element is formed thereon by bias ECR plasma CVD.

At this time, the bias ECR plasma CVD method generates plasma by an electron cyclotron resonance method, forms a thin film, applies an rf bias to a substrate holder, and performs flattening and film quality improvement by sputter etching. It is possible to form a good quality thin film at a low gas pressure of 10 ^-5 to 10 ^-3 Torr and a low temperature of 200 ° C. or less.

In this embodiment, a microwave power of 700 W,
rf power 200 W, gas pressure 1.0 m using SiH ₄ and O ₂
A silicon oxide film was formed under Torr conditions. r
Since the f power is mainly used for flattening, it may not be necessary to apply the f power. Next, as shown in FIG.
A through hole 19 for connecting the first layer wiring and the second layer wiring is opened at a predetermined position, and thereafter, the second metal wiring layer 12 is formed. Thereby, the capacitance element structure shown in the first embodiment of the present invention can be realized.

FIG. 5 is a sectional view of a main process showing an example of a manufacturing method for realizing the structure of the second embodiment of the present invention.
The difference from the embodiment shown in FIG.
1 has a high melting point metal layer 17 or a high melting point metal compound layer. Titanium, tungsten, molybdenum, or the like can be used as the high melting point metal. An oxide or the like can be used. Further, the second metal wiring layer 12 is also characterized in that the portion in contact with the insulating film 13 for the capacitor under the second metal wiring layer 12 is the high melting point metal layer 18 or the high melting point metal compound layer. In FIG. 5, the same parts as those in FIG. 4 are denoted by the same reference numerals.

[0022]

As described above, according to the present invention, by using an insulating film formed by bias ECR plasma CVD as an insulating layer as a structure of a capacitor, a film having a higher quality than an insulating film formed by a conventional CVD method can be obtained. As a result, a thin film can be obtained. For this reason, a large capacitance per unit area can be obtained, and there is an advantage that the capacitance element can be miniaturized, that is, the density can be increased. Also, the bias ECR plasma CVD method
Since it can be formed at a low temperature of 200 ° C. or less, migration of metal wiring can be reduced, so that the yield and reliability as a capacitive element can be improved.

According to another aspect of the present invention, a high melting point metal or a high melting point metal compound layer is provided in a portion of a metal wiring layer constituting an electrode of a capacitor in contact with an insulating film, thereby further reducing migration of a metal wiring. Therefore, a capacitor element having higher reliability can be realized. In addition, in the present invention, since all electrodes of the capacitor use metal wiring, the capacitor has low resistance and can realize a capacitor having excellent reliability. With these features, the capacitor realized by the present invention can provide a structure that is excellent in both high speed and high density and high reliability.

[Brief description of the drawings]

FIG. 1 is a structural sectional view showing a first embodiment of the present invention.

FIG. 2 shows a bias ECR plasma CV according to the present embodiment.
FIG. 4 is a diagram showing a comparison between current-voltage characteristics of an oxide film formed by a method D and a normal insulating film.

FIG. 3 is a structural sectional view showing a second embodiment of the present invention.

FIG. 4 is a sectional view of a main step showing an example of a manufacturing method for realizing the embodiment of FIG. 1;

FIG. 5 is a sectional view of a main step showing an example of a production method for realizing the embodiment of FIG. 3;

FIG. 6 is a structural sectional view showing an example of a conventional technique.

FIG. 7 is a structural sectional view showing another example of the prior art.

FIG. 8 is a structural sectional view showing still another example of the prior art.

FIG. 9 is a diagram showing current-voltage characteristics of various ordinary insulating films in comparison.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Insulating layer 11 1st metal wiring layer 12 2nd metal wiring layer 13 Insulating film (silicon oxide film) of a capacitive element 14 Interlayer insulating film 15 Opening 16 Silicon substrate 17, 18 Refractory metal layer

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yoshiharu Ozaki 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Kenji Miura 1-16-1 Uchisaiwaicho, Chiyoda-ku, Tokyo Japan (56) References JP-A-4-25128 (JP, A) JP-A-3-203261 (JP, A)

Claims (2)

(57) [Claims] A first metal wiring layer formed on a substrate, an insulating film formed on the first metal wiring layer, and a second metal wiring layer formed on the first metal wiring layer. A capacitive element characterized by being an insulating film formed by an ECR plasma CVD method. 2. The high melting point metal according to claim 1, wherein at least one of a portion in contact with the insulating film above the first metal wiring layer and a portion in contact with the insulating film below the second metal wiring layer. Alternatively, a capacitor element provided with a high melting point metal compound layer.