JP2704325B2 - Analog-to-digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter suitable for high-speed operation.

[0002]

2. Description of the Related Art Conventionally, a flash type is a typical example of a system suitable for high-speed operation in an analog / digital converter. This is a method in which an analog input signal is supplied in parallel to each input of an analog comparator of a power of 2 to perform a comparison operation at the same time. For example, a 6-bit analog
In the case of a digital converter, an analog input signal is supplied in parallel to input circuits of 2 6, that is, 64 comparators. For this reason, the capacitance formed in the input circuit becomes extremely large as the number of bits increases, which causes a significant reduction in high-speed performance.

On the other hand, the total length of the connection for connecting the input circuits in parallel similarly causes an extremely large transmission delay effect as the number of bits increases, and also causes a great hindrance to high speed performance. Now, even if these circuits are finely formed in an integrated circuit, if, for example, the distance between adjacent comparators is 100 microns on average, the total connection length of a 6-bit analog-to-digital converter is 640
It becomes 0 micron and 25600 micron for 8-bit. Assuming a stray capacitance per micron and line inductance of 1 femtofarad and 0.1 nanohenry, the total capacitance of the input circuit is 6.4 picofarads for a 6-bit analog-to-digital converter. With 8 bits, it reaches 25.6 picofarads. At the same time, the line inductance becomes 640 nanohenries and 2560 microhenries, respectively. When such a large reactance component exists in the input circuit, the cutoff frequency becomes a low value of about 100 MHz and 20 MHz, and the analog and analog signals for the purpose of high-speed operation are used.
This makes the implementation of digital converters very difficult.

[0004] The configuration of this type of conventional analog-to-digital converter will be described below. FIG. 5 shows a part of the input circuit of the analog / digital converter.
V _IN is a signal input path of a signal to be converted for the purpose of analog-to-digital conversion, V _RT is a high-voltage input path for a reference voltage for comparison, V _RB is a low-voltage input path for a reference voltage for comparison, and 1 is a comparison signal. Circuits A0, A1, A2,... A254, A255,
Reference numeral 2 denotes a group of reference voltage generating resistors R for comparison, and reference numeral 3 denotes an encoder for encoding the output of each comparison circuit into a digital signal. CLOCK IN is a basic clock signal input path for analog / digital conversion operation, 4 is a driver circuit for supplying a clock signal to each section, EC-OUT is a digital output of the encoder 3, and 5 is a digital output to an external circuit. OUTPUT is a data output, and C _ST is an input capacitance of each comparison circuit 1.

FIG. 6 shows an example of a semiconductor mask layout of the above-mentioned high-speed 8-bit flash analog-to-digital converter. Here, in order to reduce the attenuation of the input signal due to the filtering effect of the stray capacitance and the line inductance, the signal input path V _IN is branched into four, and the comparison circuit group 1 is arranged in four rows at the same time. , 4
The total extension per one signal input circuit V _IN is being shortened.

FIG. 7 illustrates the signal input path V _IN of the semiconductor mask layout. Signal input path V
_IN has four input signal paths IN1, IN2, IN
3 and IN4 toward the input terminal of each comparison circuit 1. FIG. 8 shows a circuit diagram of this semiconductor mask layout.

[0007]

However, in the conventional analog / digital converter, as shown in FIG. 8, the input signal paths IN1, IN2, IN3,
Since the number of comparison circuits connected per N4 is 64, the total length is slightly more than 6 mm, but the total stray capacitance of the entire signal input path _VIN is not small. Absent. Therefore, although the attenuation of the frequency characteristic at the farthest point of the branched input signal paths IN1, IN2, IN3, and IN4 is reduced, the signal input path V _IN
The capacitive load applied to an external circuit for supplying a high-frequency signal to the circuit is still very heavy.

For example, for a 100 megahertz sinusoidal signal with an amplitude of 1 volt, a capacitance of 25.6 picofarads acts as a 62.2 ohm reactance,
High frequency currents of up to 16 mA are wasted. In addition, since the influence of the capacitance becomes more significant as the frequency becomes higher, in a simple calculation, the reactance for a sine wave signal of 1,000 MHz is 6.3 ohms, and the waste of the high-frequency current is as much as 160 mA. .

An object of the present invention is to solve such a conventional problem and to provide an excellent analog-digital converter capable of improving high-frequency characteristics in an analog signal input circuit.

[0010]

In order to achieve the above object, the present invention maintains an inherent characteristic impedance including an input terminal connected to an input terminal to which an analog signal for digital conversion is input. A first distributed constant line, and one end connected to the first distributed constant line
M second distributed constant lines having different types of characteristic impedances, the combined impedance of which is equal to the characteristic impedance of the first distributed constant line;
A comparison circuit group of M groups composed of a plurality of comparison circuits in which a comparison input terminal is connected to these M second distributed constant lines in a distributed manner, and M second distributed constant lines A third distributed constant line connected to each other end and having the same characteristic impedance as the first distributed constant line; one end connected to the third distributed constant line and a predetermined voltage source connected to the other end is provided with a terminator resistor having a resistance equal to the characteristic impedance of the third distributed constant line, the input voltage of the analog signal, the ratio of the plurality
High voltage set for each of the comparison circuits and for comparison
From the input (V _RT ) to the low-voltage input (V
_RB ) until the value of a plurality of reference voltage generating means for comparison
Comparison with a reference voltage having a predetermined voltage value based on the
The plurality of comparison circuits with respect to the analog input signal.
At the same time on the road, and
In this way, digital information is obtained .

[0011]

According to the present invention, since the stray capacitance of the input path can be dispersed and made to have a constant impedance by making the analog signal input path a distributed constant with the above configuration, a high-frequency signal is supplied to the analog signal input path. Capacity load on external circuits that
Since the current load can be reduced even at a high frequency, the conversion operation can be performed at a higher speed.

[0012]

FIG. 1 shows the configuration of an input circuit of an 8-bit analog / digital converter according to an embodiment of the present invention. 1, 11 is connected to an input terminal of the analog signal for the purpose of digital conversion, a first distributed constant line having a certain line width to maintain the inherent characteristic impedance Z ₀ comprising an input terminal. 12,1
One end of each of the first, second and third distributed constant lines 11 is connected to the first distributed constant line 11, and two types of characteristic impedances Z
₀₁ , Z ₀₂ , and their characteristic impedances Z ₀₁ ,
The combined impedance of Z ₀₂ is the first distributed constant line 1
Equal to 1 the characteristic impedance Z ₀ is a four second distributed constant line. 16, 17, 18, and 19
This is a group of four comparison circuits in which comparison input terminals are connected to each of the second distributed constant lines 12, 13, 14, 15 in a distributed manner. 20 is connected to the other ends of the second distributed constant line 12, 13, 14, 15 of the four, in the third distributed constant line having a characteristic impedance equal _{Z 0} and first distributed constant line 11 is there. This third
The distributed constant line 20 has M input lines (in this embodiment,
Is the same figure as the geometrical division method when dividing into 4)
The line is synthesized using the reverse of the
One signal line impedance Z ₀ and the same Lee entering the vessel
It has a role to terminate in impedance Z _0. Reference numeral 21 denotes a terminating resistance element having one end connected to the third distributed constant line 20 and a predetermined voltage source (not shown) connected to the other end.
_It has a resistance value equal to _zero .

V _IN is a signal input path connected to an input terminal (not shown) to which an analog signal for analog-to-digital conversion is input, V _RT is a reference voltage input side for comparison, and V _RB is an input path. Reference voltage input for low voltage side for comparison,
R0 to R254 are reference voltage generating resistors for comparison,
A2, Aj~Al, Ap~Ar, A253~A255 comparison circuit, C _ST is an input capacitance of each comparator circuit. FIG. 2 is a simplified illustration of a group of branches and terminations of an input signal path in the above embodiment.

Next, referring to FIG. 1 and FIG.
Will be described. Signal input path V_INInput terminal
Desired specific impedance Z including₀Characteristic impe
Input to the first distributed constant line 11 having
The analog signal is connected to the first distributed constant line 11.
The second distributed parameter lines 12, 13, 14, and 15
Go on. Characteristic impedance Z₀₁Distributed constant line with
Roads 12, 15 and Z ₀₂Distributed line 13, 1 having
Of the four distributed constant lines 12, 13, 14, and 15 of FIG.
The combined impedance at a point is the characteristic impedance
Z₀Is set to be equal to
Are matched and at least the input signal is
The possibility of backflow as a reflected wave on the distributed parameter line 11 is small.
No. Further, the second distributed constant lines 12, 13, 14, 15
Are each a quarter of the entire comparison circuit
As if connecting the input capacitance of
Although it is included as if it is a part of the capacitance component of the distributed line,
From the second distributed parameter lines 12, 13, 14, and 15, respectively.
Achieves the desired characteristic impedance,
Signal input path V_INDispersion of stray capacitance and constant impedance
Signal input path V_INHigh frequency signal to
Capacity load on the external circuit to be supplied can be reduced.
You.

[0015] When the silicon semiconductor and to realize such a circuit, from close to the dielectric constant of approximately 10, when the characteristic impedance Z ₀ is 50 ohms, close to the thickness of the line width is approximately interlayer insulating layer value It is realized as. In the embodiment shown in FIG. 1, the signal input path V
_The characteristic impedance Z ₀ of the first distributed constant line 11 at _IN and the second distributed constant line 12 behind the branch,
13, 14 and 15 have two types of characteristic impedance Z
_The following relationship is maintained between ₀₁ and Z ₀₂ .

1 / Z ₀ = 2 / Z ₀₁ + 2 / Z ₀₂ Generally, the second distribution constant behind the branch is maintained while maintaining the relationship represented by 1 / Z ₀ = Σ ⁿ (m _j / Z _0j ). The characteristic impedance of the lines 12, 13, 14, 15 can be set freely. Here, n is the type of characteristic impedance, and m is the number of second distributed constant lines having the same characteristic impedance.

FIGS. 3 and 4 show an example of a semiconductor mask layout of the analog-to-digital converter according to the above-described embodiment which embodies this situation. FIG.
4 and A0, A1,... Aj,.
p, Aq, ··· An, ··· A254 and A255
Of the comparison circuit groups 16, 17, 13, 19
(256 in this embodiment).
The circuits A0 to A255 are, as shown in FIG.
The reference voltage generator is a plurality of reference voltage generators.
It is connected to the terminal of each stage of the pressure generating resistor group. In addition,
The delay time of each of the second distributed constant lines 12, 13, 14, 15 is set to be equal, and the return times of the reflected waves are made uniform. And with such a configuration, analog
Signal input voltage (V _IN ) and the plurality of comparison circuits A
0 to A255 and a reference voltage for comparison
From the high voltage side input (V _RT ) to the reference voltage for comparison low voltage side input
A plurality of reference voltage generating resistors for comparison up to the force ( _VRB )
Have predetermined voltage values sequentially based on the values of the instrument groups R0 to 255.
The comparison with the reference voltage to be performed is performed by the analog input signal (V
_IN ) with respect to the plurality of comparison circuits A0 to A255.
Execute at the same time and decode
Get digital information . The input analog signal input to the first distributed constant line 11 having the characteristic impedance equal to the specific impedance Z ₀ is applied to the second distributed constant line 1
After passing through 2, 13, 14, 15, and the third distributed constant line 20, it is guided to the terminating resistance element 21 and converted into heat, and therefore, reflected waves are suppressed.

[0018]

As described above, according to the present invention, the input capacitance which tends to be very large in the analog signal input section of the analog-to-digital converter is dispersed over a wide frequency band, and a constant impedance is obtained. Can reduce the capacitive load on the external circuit that supplies the high-frequency signal to the analog signal input path, and the current load can be reduced even at high frequencies. To the analog-to-digital converter.
This has the effect that the speed of the conversion operation can be further increased. Also, inside the semiconductor mask layout of this analog-to-digital converter, the branched second distributed constant line is limited only in the combined value of the characteristic impedance, and is completely free of the characteristic impedance. Can be provided, even if the applied ground pattern in the integrated circuit is deformed, the comparison circuits can be arranged without being equally divided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an input section of an analog-to-digital converter according to an embodiment of the present invention.

FIG. 2 is a connection diagram of a signal input path in the embodiment.

FIG. 3 is a layout diagram on the input side of a semiconductor mask layout in the embodiment.

FIG. 4 is a layout diagram of an output side of a semiconductor mask layout in the embodiment.

FIG. 5 is a schematic block diagram showing an example of a conventional analog / digital converter.

FIG. 6 is a schematic plan view of a semiconductor mask in the conventional example.

FIG. 7 is a layout diagram on the input side of a semiconductor mask layout in the conventional example.

FIG. 8 is a circuit diagram of an input unit in the conventional example.

[Explanation of symbols]

Reference Signs List 11 first distributed constant line 12, 13, 14, 15 second distributed constant line 16, 17, 18, 19 comparison circuit group 20 third distributed constant line 21 terminating resistor element _{VIN for} analog-to-digital conversion converted signal signal input path V _RT comparison reference voltage high voltage side input path V _RB comparison reference voltage reference voltage generator resistor group A0~A255 comparator circuit C _ST Comparative low voltage side input path R0~R254 for comparison of the Circuit input capacitance

Claims (1)

(57) [Claims] 1. A first distributed constant line connected to an input terminal to which an analog signal intended for digital conversion is input and maintaining a characteristic impedance including the input terminal, and the first distributed constant line Is connected at one end to N
M second distributed constant lines having different types of characteristic impedances, the combined impedance of which is equal to the characteristic impedance of the first distributed constant line, and M second distributed constant lines The input terminal for comparison consists of a plurality of comparison circuits connected in a distributed manner.
A group of comparison circuits of M groups, a third distributed constant line connected to the other end of each of the M second distributed constant lines, and having a characteristic impedance equal to that of the first distributed constant line; the third distributed constant line to be connected with one end connected predetermined voltage source at the other end, and a termination resistance element having a resistance equal to the characteristic impedance of the third distributed constant line, the analog signal And the plurality of comparison circuits
And the reference voltage for high voltage input
(V _RT ) to the comparison reference voltage low voltage side input (V _RB )
Based on the values of multiple reference voltage generators
The comparison with a reference voltage having a predetermined voltage value
Simultaneous conversion of analog input signals by the plurality of comparison circuits
And digitize these multiple comparison judgment outputs.
Analog information characterized by obtaining
Digital converter.