JP2704121B2 - Vector processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processing device.

[0002]

2. Description of the Related Art In general, in order to process a large amount of data at a high speed between a main memory and a register or an arithmetic unit, a vector processing apparatus continuously transmits a plurality of data to a memory access processing unit at the same timing. To achieve higher speeds.

A conventional vector processing apparatus of this type is shown in FIG.
As shown in the figure, a plurality (for example, four elements) of input ports for each element of a vector request, input registers 31a to 31d for each input port, and a buffer 32a operating the same for buffering when a port conflict occurs. 32d, buffers 33a-33d, port conflict detection circuit 37 for detecting port conflict and buffer control, output element detection circuit 36 for generating an output port from a memory address of an input element and determining an element to be output at the timing And selectors 34a to 34d for selecting an input element of each output port according to a control signal of the output element detection circuit 36, and output registers 35a to 35d corresponding to the output ports.

In this conventional vector processing device, the output port is in units of 8 bytes, and a 4-byte memory access instruction is also executed in units of 8 bytes.

FIG. 2 shows an address of each vector element (hereinafter, referred to as an element) at the time of a vector store instruction for explaining the conventional example and the present invention, and an output port to which each element is output for each element. In FIG. 2, when the base address of the vector instruction is “0” and the distance is “4”, elements 0, 1, element 2, 3,.
It can be seen that each element has the same output port.

Next, the operation of the conventional vector processing device at the time of the vector instruction shown in FIG. 2 will be described. First, the input registers 31a to 31d store 4
It is stored continuously for each element. At a certain timing, port conflicts are detected by the port conflict detection circuit 37 for the elements 0 to 3 stored in the read registers 33a to 33d. In this case, elements 0 and 1 are respectively connected to output port 0,
Since elements 2 and 3 each go to output port 1, a port conflict will occur. When a port conflict occurs, the output element detection circuit 36 detects the element having the highest priority (the element with the smallest element number) of the conflicting element, the selector 34a reads the element 0 of the read register 33a, and the selector 34b reads the register 33c. Are selected and stored in the output registers 35a and 35b.

At this time, from the port conflict detection circuit 37,
Since a contention has occurred, a hold request is issued, the read registers 33a to 33d hold, and the buffers 32a to 32d hold.
32d holds the read address of the buffer and keeps that state until the hold request is released.
That is, the elements continuously input to the input registers 31a to 31d are buffered in the buffers 32a to 32d. Elements 1, which survived the competition
No. 3 indicates that the conflict detection is performed at the next timing and no port conflict occurs this time, so that the output registers 35a and 35b
Are stored respectively. Since no conflict occurs, the hold request from the port conflict detection 36 is released, and the read registers 33a to 33d store the element 4 at the next timing.
7 are stored. Thereafter, the same processing is performed until the end of all elements.

FIG. 7 is a timing chart showing the above operation, and shows the output port arrival timing of each element when the timing at which elements 0 and 2 arrive at the output registers 35a to 35d is 1. Also, the port conflict detection target element and the number of output port register arriving elements at one timing are shown. In the case of the vector instruction in FIG. 2, it can be seen that, due to port contention, two elements are output for four elements at each timing. This is の of the maximum throughput.

[0009]

As described above, in the conventional vector processing apparatus, a 4-byte vector load / store instruction (a case where the distance is an odd multiple of 4 bytes)
In this case, the throughput is １ ／ of the maximum value, and there is a drawback that the performance of the vector load and store instructions in the main memory is seriously degraded.

[0010]

According to the present invention, there is provided a vector processing apparatus comprising: at least one vector operation unit for performing a vector operation for each vector element; A vector processing device comprising: a main storage unit configured by a memory module; and a memory access control unit that controls data transfer for each vector element via an output port between the vector calculation unit and the main storage unit. The memory access control unit includes n (n ≧ 1) input registers for holding vector elements input in a pipeline manner from the vector operation unit, and each set stores the content of the input registers in n vector element units. And m sets stored in the order of element numbers (m ≧
2) buffers, m × n read registers for holding vector elements read in response to clocks from the m sets of buffers, and vector elements held in the read registers. A port conflict detection circuit for detecting a conflict between the output ports that occurs when the bit width is equal to or less than the minimum access unit; and An output element detection circuit for detecting, and the same number of secretors as the number of the output ports for selecting the vector element from the read register in response to the detection of the output element are provided.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. The vector processing apparatus can transfer data in units of 8 bytes in parallel.

In FIG. 1, input registers 11a to 11
d is a plurality (for example, 4 elements) of input receiving registers for each element of the vector request. Buffer 12
Reference numerals a to 12h denote buffer groups for buffering input requests continuously issued when a wait occurs due to a port conflict. The buffers 12a to 12d and the buffer 1
2e to 12h correspond to the elements of the input registers 11a to 11d, respectively, and the buffers 12a to 12d and 12b
Elements of the input registers 11a to 11d are alternately input to e to 12h.

The read registers 13a to 13h are registers for reading the buffers 12a to 12h.
This is a register for port conflict detection. The output element detection circuit 16 generates selection conditions for the selectors 14a to 14d corresponding to the output ports. The port conflict detection circuit 17
This is a circuit for detecting a port conflict of each element of the read registers 13a to 13h, and buffers 12a to 12h,
And the read registers 13a to 13h. The output registers 15a to 15d are a group of registers corresponding to output ports (four ports in this example), and store the elements selected by the selectors 14a to 14d.

FIG. 2 shows an example in which the base address is "0".
It shows the relationship between the address of each element of the 4-byte vector store instruction with the distance being "4" and the output port from which each element is output. It can be seen that in the 4-byte vector store instruction, two elements having consecutive element numbers are output to the same output port.

Next, the operation of the first embodiment at the time of issuing the request shown in FIG. 2 will be described. Elements 0 to 3 are input from input ports 0 to 3 and input register 1
1a to 11d. At the next timing, four elements of elements 4 to 7 are sent to the input port. Thereafter, at each timing, four elements are continuously issued and stored in the input registers 11a to 11d continuously. .

The first four elements, elements 0-3, are buffer 1
Readout registers 13a to 13a through 2a to 12d
d is stored in the order of element numbers. Until then, valid elements were not stored in the read registers 13e to 13h. Here, the port conflict detection circuit 17 performs port conflict detection on the elements 0 to 3. As shown in FIG. 2, since elements 0 and 1 are both output to output port 0 and elements 2 and 3 are both output to output port 1, port conflicts occur between elements 0 and 1 and between elements 2 and 3, respectively. Occur. If a port conflict occurs, 1
Since only one element can be output, the element having the smallest element number among the elements in which contention has occurred is output with priority.
At this time, since other elements cannot be output, the output is waited for in the read registers 13a to 13d. That is, elements 0 and 2 are output and output registers 15a, 1
5b, elements 1 and 3 are read register 13
Hold at b and 13d.

At this time, elements 4 to 7, which are the next four elements, are read out from the read register 13 via buffers 12e to 12h.
e to 13h. The elements 1 and 3 and the elements 4 to 7 that have lost the contention at the previous timing are the target elements for the next port contention detection. Looking at the output ports of the respective elements from FIG. 2, it can be seen that the elements 4 and 5 and the elements 6 and 7 are in port conflict, respectively. Therefore, the elements going to the output port are the four elements of elements 1, 3, 4, and 6, and the elements 5, 7
Is detected by the port conflict detection circuit 17,
The data is held in the read registers 13f and 13h and is kept waiting.

At the next timing, the remaining elements 5 and 7 are output. At this time, for the subsequent elements, it takes 3T to output the first eight elements, so that 1T, that is, four elements remain in the buffer. Therefore, at the timing after the 4T, eight elements are always target elements for port conflict detection, and four elements are always output due to port conflict.

FIG. 3 shows the operation of this embodiment at the time of the vector store instruction given in FIG. 2. The timing at which the elements 0 and 2 arrive at the output registers 15a to 15d is set to 1. Output register 1 of each element at the time
For each arrival timing at 5a to 15d, the port conflict detection target element and the number of output elements are shown. From FIG. 3, at timings 1, 2, and 3, the number of output elements is 2, 4, 2, and
Although the throughput is lower than the maximum throughput, the number of output elements becomes 4 elements after element 8 after timing 4 and
It can be seen that the number of input elements is equal to the maximum and the maximum throughput is obtained.

FIG. 4 is a block diagram showing a second embodiment of the present invention. In this embodiment, similarly to the first embodiment, data can be transferred in units of 8 bytes in parallel. In the present embodiment, the input registers 21a to 21d, the buffers 21a to 22h, the read registers 23a to 23h, the selectors 24a to 24d, the output registers 25a to 25d,
The output element detection circuit 26 and the port conflict detection circuit 27 are the input registers 11a to 11 in the first embodiment, respectively.
d, buffers 12a to 12h, read register 13a
To 13h, selectors 14a to 14d, output register 15
a to 15d, the output element detection circuit 16, and the port conflict detection circuit 17.

In this embodiment, an element alignment circuit 28 for rearranging the elements stored in the read registers 23a to 23h when a port conflict occurs is additionally provided. Here, in the detection of port conflict, four elements are taken as one block as an example. In other words, the elements stored in the read registers 23a to 23d are regarded as one block, and the elements stored in the read registers 23e to 23h are regarded as one block. Detects that all the elements in have been output, shifts the block in which all the elements have been output by the element aligning circuit, and stores the subsequent block in the port conflict detection target register.

Next, the operation of the second embodiment at the time of issuing the request shown in FIG. 2 will be described.

The feature of this embodiment is that, at timing 2, the elements 5 and 7 that have lost the contention
Is stored in the read registers 23f and 23h instead of the read registers 23f and 23h. As a result, the elements 8 to 11 of the subsequent block are stored in the registers 23e to 23h without waiting for the output of the elements 5 and 7, and It may be a port conflict detection target element. Based on this result, elements 5 and 7 and elements 8 and 10 are output at the next timing. Thereafter, the shift is similarly performed in units of blocks, and four elements are output at each timing.

The above operation will be more apparent with reference to FIG. 5 showing the operation of the present embodiment for the vector store instruction given in FIG. FIG.
According to the above, at timing 1, the number of output elements is 2,
At subsequent timings, the number of output elements becomes four, which is equal to the number of input elements, and the maximum throughput is obtained. Therefore, it is understood that the second embodiment is a further improvement of the first embodiment.

As described above, in the present invention, the throughput of a vector memory access instruction is improved. In the embodiment, four input ports and four output ports are used. However, it is apparent that any number of ports can be used in the same manner. In addition, the expansion is 8 ports, twice the input 4 ports,
This can also be a multiple of any input port. In the embodiment, a vector store instruction is used, but a load instruction can be similarly implemented.

[0027]

As described above, according to the present invention, in a vector processing apparatus, when a port conflict of a vector load / store instruction occurs, a means for artificially expanding an input port is provided, thereby increasing the number of port conflict detection target elements. Thus, even if a port conflict occurs, the number of elements that can be output is increased, and the throughput is improved. For example, in the case of a 4-byte vector memory access instruction,
Throughput is improved about twice.

[Brief description of the drawings]

FIG. 1 is a block diagram of a vector processing device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an address and an output port of each element at the time of a vector store instruction.

FIG. 3 is a timing chart for explaining the operation of the first embodiment of the present invention.

FIG. 4 is a block diagram of a vector processing device according to a second embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of the second exemplary embodiment of the present invention.

FIG. 6 is a block diagram of a conventional vector processing device.

FIG. 7 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 11a to 11d Input register 12a to 12h Buffer 13a to 13h Read register 14a to 14d Selector 15a to 15d Output register 16 Output element detection circuit 17 Port conflict detection circuit 21a to 21d Input register 22a to 22d Buffer 23a to 23d Read register 24a to 24d Selectors 25a to 25d Output registers 26 Output element detection circuits 27 Port conflict detection circuits 31a to 31d Input registers 32a to 32h Buffers 33a to 33h Read registers 34a to 34d Selectors 35a to 35d Output registers 36 Output element detection circuits 37 Port conflict detection circuits 38 Element alignment circuit

Claims (2)

(57) [Claims] A main storage unit comprising one or more vector operation units for performing a vector operation for each vector element, a plurality of memory modules capable of performing a parallel operation using a plurality of bytes of data as a minimum request unit; In a vector processing device including a memory access control unit that controls data transfer for each vector element via an output port between a vector operation unit and the main storage unit, the memory access control unit includes a pipe from the vector operation unit. N (n ≧ 1) input registers for holding vector elements to be input in the line system, and m sets (m) for storing the contents of the input registers in n vector element units and in the order of element numbers. ≧ 2) buffers, and m × n readouts holding vector elements read out from the m sets of buffers in response to clocks A register, and a port conflict detection circuit for detecting a conflict between the output ports, which occurs when a bit width of the vector element is equal to or smaller than the minimum access unit, for the vector element held in each of the read registers. An output element detecting circuit for detecting the smallest one of the element numbers among the vector elements competing for the output element, and the same number as the number of the output ports for selecting the vector element from the read register in response to the detection of the output element cell of
Vector processing apparatus characterized by comprising a selector. 2. The buffer unit shifts the remaining vector elements that have lost the contention of the output port from the buffer to the read register so as to provide a storage area for a vector element of a subsequent input. 2. The vector processing apparatus according to claim 1, further comprising an element aligning circuit for performing the operation.