JPS6024976B2 - Memory access control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access control method, and in particular, the present invention relates to a memory access control method, and in particular, data consisting of a plurality of elements placed in a plurality of memory banks is accessed by a plurality of access request means, and a specified element is accessed by a plurality of access request means. The present invention relates to a memory access control method for reading and/or writing a plurality of element data according to their priorities in a data processing device that processes data.

An example of a data processing device that processes a plurality of element data is a vector calculation device. Calculations in this vector arithmetic device are normally performed for each element called an element.
+IB=(a, 10q, a20Q, . . . , an+bn) (ai, bi are elements).

Therefore, as a memory access system, it is necessary to protect the order of elements and send data to an arithmetic unit or vector register. On the other hand, regarding the memory system, the memory system has a plurality of memory banks (referred to as LS) that can be accessed independently, and can operate simultaneously as long as there is no access conflict.

Therefore, in some cases it is possible to access an element from multiple access request boats at the same time, while on the other hand, element access from one access request boat waits for a long time, and element access from another access request boat is delayed. There are also cases where memory access is possible. Conventionally, in such cases, the data was accessed without considering the element order, the data retrieved from main memory was temporarily held in a data buffer, and then, when each element was available,
Data was extracted in element order and sent to a vector register in the arithmetic unit. FIG. 1 is a block diagram of an example of a vector calculation device, and in the figure,
V mountain vector calculation unit, MS is main memory, MCU is main memory control unit, VR is vector register, LS. ~L
Sn is a memory bank. In the example shown in FIG. 1, there are four access boats, and each access boat arbitrarily accesses the memory and stores element data read from the main memory in each data buffer.

A control circuit (not shown) monitors the contents of each data buffer, and after confirming that element data of the same order has been read into each data buffer, the contents are transferred to the vector register. I'm trying to move it. Incidentally, recently, the speed of logic circuits has become faster, and the speed difference between the access time of a memory and the calculation speed of a vector calculation device or the like has become noticeable.

Therefore, a larger capacity data buffer is required than before. An object of the present invention is to eliminate the need for data buffers by managing the order of elements using memory access control priorities, and for this reason, the present invention provides a method for managing multiple elements placed in multiple memory banks. In a data processing device that accesses data consisting of a plurality of access request means and processes specified element data, memory access is performed in accordance with the priority order of the element data to be accessed by each access request means. The present invention is characterized in that it includes a control means and reads and/or writes a plurality of element data according to their priorities. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a block diagram of the memory access control unit of the embodiment according to the present invention. In the figure, 1 to 4 are IJ quest pointers (RQPA to D), and 5 to 8 are address boats (A to D).
D PORT), 9 to 12 are request address buffers, 13 is an LS busy check decoder (BSYCH
KDEC), 14 is a decoder for setting the LS busy latch (SETDEC), 15 is a decoder for resetting the LS busy latch (RSTDEC), 16 is a comparison circuit for checking the bus conflict list, 17 is a priority control circuit, 18 to 25 are main A register with a selector 26 is used to send an access address to the memory, a loopback address 26 is used for partial writing, and a pseudo busy latch group 27 has set/reset latches equal to the number of LSs in the main memory. The memory access control unit of the embodiment includes four independent access request means, and is capable of issuing a maximum of four accesses to any of the eight independent main memory units (MSO to 7) at the same time. It has become.

Each main memory unit (MS) further includes, for example, 16 memory banks (LS). First, an overview of the memory access control method according to the present invention will be explained below. Now, in order to extract each element of the vector data, the addresses of a total of n elements, starting from element 0 and corresponding to the length of the vector data, are sequentially sent from four access ports (VPA to VPD) of the vector arithmetic unit (not shown). shall come.

In other words, the 0th to 3rd element addresses are each V
Coming from PA~VPD, then the 4th~7th elements/
Addresses arrive from VPA to VPD, and are sent out in the same way, so in the end, of each address boat, A PORT5 has element numbers 0, 4, 8,
12, 16…. ..., 8 PORT 6 is element number 1, 5, 9, 13, 17..., C PO
RT 7 has electronic numbers 2, 6, 10, 14, 18.
..., D PORT 8 is element number 3,
7, 11, 15, 19... will be processed.
That is, A PORT 5 is 4i (i=0, 1, 2,
Similarly, the element number data of
B PORT 6 accesses 4i+1 data, C PORT 7 accesses 4i+2 data, and D PORT 8 accesses 4i+3 data. Assume that requests for element numbers 0 to 3 are first set to A to D PORTs 5 to 8.

At this time, the request pointer RQPAI is set on, and the other ROPB-D2-4 are turned off. R.O.
P indicates the priority of the requests of the four access boats, and thereby the priority of access to the main memory from each boat is taken into consideration. Hello, R
When QPA is on, if access from A PORT 5 is disabled due to LS busy or other conditions, access from B to D PORTs 6 to 8 is also disabled. That is, access from B PORT 6 is enabled only when access to A PORT 5 is enabled. Furthermore, under this condition (RQPAI is on), A PORT 5 and B PORT
6 can be accessed, and when access from C PORT 7 is disabled, not only C PORT 7 but also D PORT 8 will not be accessed.

In this case, only accesses from A PORT 5 and B PORT 6 are executed in that cycle, and the request pointer moves to C PORT 7 in the next cycle.
When RQPC3 is turned on, a request for element number 4 is set in APORT 5 and a request for element number 5 is set in B PORT6. At this time, the priority order is C>D>A>B, and C PORT 7 and D
A unless access from PORT 8 is enabled.
Access from PORT5 and B PORT6 is not performed. Also, if A~D PORT 5~
Among the accesses from 8, if there is one that accesses the same MS, the access boat having the higher priority according to the position of the request pointer makes the access. In this way, by controlling the management of the access order for each element in the memory access control unit, the order of each element can be maintained simply by sequentially transferring the data retrieved from the main memory to the vector arithmetic unit. I can do it.

Furthermore, in the case of a store operation, it is possible to similarly perform the store in the correct order. Below, details of circuit operation for performing the above-mentioned functions will be explained.

As mentioned above, the priority order is "Element number <n>
must be prioritized at the same timing as element number <n-1> or at a later timing.

” is taken under the condition that This condition is especially necessary to avoid logical contradictions during writing.

That is, when different element data are actually stored at the same address, the element data must be updated in a certain order. However, as long as there is no such address overlap, they may be updated at the same time. RQPA~○I~4 is set to ON for the access boat indicating the element with the lowest number among the four access boats.

For example, element numbers 0 to 3 are A to ○ PORT 5
~8, RQPAI is set. And 4
Element 0 of A PORT 5 in the access boat
Assuming that access is made only to A PORT 5, in the next cycle, element number 4 is set to A PORT 5, and element numbers 4, 1, 2, and 3 are set to A~○ PORT 5 to 8 in this order. As a result,
As for the request pointer, RQPB2 is turned on. The conditions for setting this request pointer are as follows.
Note that the fact that the right side of the equation includes the same term as the left side means that the previous state of the signal itself is reflected in the determination of the signal corresponding to that term.

[RQP=A]

= [D PORTCO]・[A PORTGO] 10RE
SET + [OPERATION END] 10 [ALLPO
RTGO]・[RQP=A][RQP=B]= {[A
PORT GO〕・〔B PORT〔X〕〕〔〔A
LLPORTGO]・[RQP=B]}・[OPERA
TIONEND] [RQP=C] = {[B PORT GO]・[C PORT(X
〕〕〔ALLPORTGO〕・〔RQP=C〕}・〔
operation
PERATIONEND〕Here A~D PORTGO
indicate that access was made from A to DPORT, respectively.

OPERATION END indicates that the last element of a series of vector data loads/stores has been accessed. ALL PORTGO is A~D
This indicates that all four access ports were accessed at the same time. RESET indicates that the initial state has been reset. Next, the comparison circuit 16 selects A~○ PORT
This circuit checks whether accesses 5 to 8 use the same MS address bus or not.

Specifically, among the address information held in each access boat, 3 bits necessary for identifying MSO-7 are inputted, and 3 bits at a time are compared with each other. The check results are A=B, A=C, A=D, B=C, as shown in the figure.
Each signal line of B=D, C=D,
The signal is sent to the control circuit 17. When an access bus causes a conflict, which access boat is stronger depends on the position of the IJ quest pointer at that time.

The priority control circuit 17 is the comparison circuit 1
6 output and each request pointer RQPA~DI~
Enter a value of 4 and determine which access boat is stronger. Figure 3 shows the game table. A to D written in the frame of FIG. 3 indicate stronger access boats. On the other hand, the LS busy state is held in the LS busy latch group 27.

There are as many LS busy latches as there are melons. For example, if eight MSs are created as shown in the figure, and one LS is present for each MS, 16×8=128 latches are created. A latch is set when access from a certain access boat is permitted, and the corresponding latch is selected by the decoder 4 and set. Also, the latch is reset by
This is when the access ends, and at the end of the access, the corresponding latch is selected and reset by the decoder 15. At the stage when a request is set in an access boat, the corresponding latch is selected by the decoder 3, and the access destination B is selected for each access boat A to ○.
is checked to see if it is busy.

The check results are then input to the priority control circuit 17 as the illustrated YA-D signals. Next, the loopback address 26 is a bus that provides a store address during partial writing, and is sent from an address pipeline register (not shown).

Since the store operation during this partial write has the highest priority, at this time, all LSs connected to the loopback MS address bus are forced to appear busy (ForceB). ,
It controls MS address bus collisions with A to D boats. In this way, when the busy check result information, the MS address bus conflict check result information, and the contents of RQPA~DI~4 are input to the priority control circuit 17, the priority control circuit Step 17 creates a condition for issuing memory access permission (MSGO).

As an example, conditions under which memory access of A PORT 5 is prohibited are shown below.

A PORT GO=A PORT REQ+(ABU
SY) ten (RQP=B) {(A=B) ten (A= C) ten (A=D) + (B spot Y) ten (C spot Y) ten (D already Y)} ten (RQP=C ) {(A=C) Ten (A=D) Ten (C Mother Y) + (D Spot Y)} Ten (RQP=D) {(A=D) + (D Spot Y)} Here, for example, ( A BUSY) indicates that B, which is the access target of A PORT5, is busy, and (RQP=
B) indicates that the request pointer is on B PORT 6, (A=B) indicates that A PORT 5 and B PORT
6 indicates that a bus collision has occurred.

The conditions for B to D PORTs 6 to 8 are created in the same way, so their explanation will be omitted.

In addition, the conditions for prohibiting the request are bus collision and L
There are other types besides S Busy, but they are omitted for the sake of simplicity. FIG. 4 shows an example of a priority circuit for A PORT5 that satisfies the above conditions. B~DPORT 6
Since the priority circuits 8 to 8 are created in the same manner, illustration of their circuit configurations will be omitted. In this way, once the conditions for memory access are obtained, the priority
The control circuit 17 sends a selection signal to a corresponding one of the registers 18 to 25 to cause the address held in the access boat to be set in the register.

As a result, access to the MS is subsequently performed. Data is then retrieved from the MS in the order of the element numbers, and the read data is sent to the vector arithmetic unit that has requested access via a data path (not shown). As explained above, according to the present invention, the memory access control unit accesses the memory according to the priority order of multiple element data, so there is no need to create a large amount of data buffer as in the conventional method. In addition, there is no need to provide a complicated mechanism to monitor the order in which data arrives in the data buffer.
This has the excellent effect of reducing hardware and simplifying control.

In addition, in the embodiment, application to a vector arithmetic device is shown, but the present invention is not limited to a vector arithmetic device.
Needless to say, the present invention is applicable to various data processing devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a vector calculation device, FIG. 2 is a block diagram of a memo-IJ/access control unit according to an embodiment of the present invention, and FIG. 3 is a diagram showing a game table in the event of a bus collision. FIG. 4 is a diagram showing an example of a priority circuit. In Figure 2, 1 to 4 are request pointers, 5 to 8
is an address board, 13 is an LS busy check decoder, 14 is a set decoder, 15 is a reset decoder, 16 is a bus conflict check comparison circuit,
17 is a priority control circuit, 18 to 25
The register 27 is a group of busy latches. Elephant Diagram Vertical Diagram Ship Diagram Dimensional Ball

Claims (1)

[Claims] 1. Data consisting of a series of multiple elements placed in multiple independently operable memory banks is accessed by multiple access request means, and the series of elements is
In a data processing device that processes data in the series of orders, an access order display means displays the priority among the access request means according to the series of orders of element data to be accessed by each access request means. a conflict check means for checking memory bus conflicts between element data to be accessed by each access request means; a busy display means for displaying the busy state of each of the memory banks; and an address order display means. , priority means for determining access to each memory bank based on the outputs of the contention check means and the busy display means, and the element data is read and/or written in accordance with the above series of orders. A memory access control method characterized by: