JP2700880B2 - Imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]   The present invention relates to an imaging device, and particularly to a device using a single imaging device.
Imaging device that generates a luminance signal and a chrominance signal
Imaging devices that can obtain high-resolution still images
You. [Conventional technology]   In recent years, imaging devices such as video cameras and electronic cameras
A solid-state image sensor using LSI technology is used as an image element.
It is supposed to be. Imaging system using solid-state imaging device
In addition to the single-panel type using a single image sensor,
There are two-panel type and three-panel type using an image sensor.
The single plate type is the most advantageous for achieving light weight and low cost.
is there. There are various color imaging methods in this single-chip system.
Are known, but high sensitivity points and high color resolution
Two-line simultaneous readout method using complementary color filter
Useful for   The two-line simultaneous readout video camera is a solid-state image sensor.
Read two horizontal lines next to each other at the same time
And a luminance signal and a chrominance signal are obtained from these signals.
The set of horizontal lines read at the same time is
Interlaced to shift one horizontal line to
A color television signal is obtained.   FIG. 2 shows an example of a solid-state imaging device of a two-line simultaneous readout method.
FIG. 1 is a solid-state image sensor (hereinafter referred to as a sensor)
8) is a drive scanning circuit of the sensor 1, 101, 102, 103 and
And 104 are output terminals of the sensor 1.   The light-receiving portion of the sensor 1 has
In addition, a color filter is arranged on each picture element. In the example of the figure
Is the odd horizontal line l₁, L_Three, L_Five, .... is white
Filter (hereinafter referred to as W filter) and green filter (hereinafter referred to as W filter).
And the lower G filter) are arranged alternately, and even-numbered
Horizontal line l_Two, L_Four,... Include a cyan color filter (hereinafter
Gy filter) and yellow filter (hereinafter Ye filter)
Are alternately arranged.   The number of picture elements per horizontal line determines the horizontal resolution
For an NTSC imaging device, this is about 400.
I have. The number of horizontal lines depends on the running
The number of lines is the same as the number of lines.
There are five. However, the top and bottom of the screen
Considering that it is not displayed on the television receiver, NT
In the case of SC system, it may be about 490 lines.   Now, such a sensor 1 is controlled by the drive scanning circuit 8.
The signal from the scanned picture element is output terminal 101,
Output to 102,104 and 104. This scan is described above.
In this way, two adjacent horizontal lines are
Will be For example, first the horizontal line l₁And l_TwoIs from the left end to the right
Scan in the direction₁From the signal from the W filter (described below)
Signal w) and the signal from the G filter (hereinafter referred to as g
Are obtained alternately, w of which is output terminal 101
Then, g is output to the output terminal 102. l_TwoFrom Gy Phil
Signal (hereinafter referred to as symbol cy) and Ye filter
Are alternately obtained.
Cy is output to output terminal 103 and ye is output to output terminal 104.
You.   Whether the output signals w, g, cy and ye from the sensor 1 are
The method for obtaining the luminance signal and the chrominance signal is as follows.
You.   The red signal, which is the three primary color signals, is r, and the green signal is g (
B), and the blue signal is b.
When, w = r + g + b cy = g + b ye = g + r It is. On the other hand, the luminance signal Y is obtained by dividing red, green, and blue by 3: 6: 1.
Can be obtained by combining the two colors.
Green transmittance is almost equal, and blue transmittance is about 1/3 of that
From that Y = r + 2g + b It is desirable that Also, the b signal is occupied by the luminance signal Y.
Considering that the ratio of
And the signal consisting of g + ye are practically Y and
I can do it. Therefore, w +
By calculating cy and g + ye, a luminance signal Y can be obtained.
Wear. On the other hand, for the color signal, the calculation of w-cy and ye-g
And add these to obtain the r signal, w-ye and
Perform cy-g operation and add these to obtain b signal
be able to.   That is, the horizontal line l₁And l_TwoOne scan from the scan output of
The luminance signal and the color signal of the line segment can be obtained. l₁And l_Twoof
When the simultaneous scanning is completed,_ThreeAnd l_FourIs scanned, and similarly
A luminance signal and a chrominance signal for one scanning line are obtained. The same applies hereinafter
, Two horizontal lines are scanned. The entire receiver
A signal obtained by one scanning corresponds to one field.
You.   By the way, in the video camera of the two-line simultaneous readout method,
Field (hereinafter referred to as the first field)
When the above scanning is performed, the next field (hereinafter referred to as
Field 2)_TwoAnd l_ThreeScan simultaneously
And then l_FourAnd l_FiveTo scan one horizontal line simultaneously.
Simultaneous scanning with offset, obtained in the same way as the first field
Luminance signal for one field from the w, g, cy and ye signals
I make color signals and signals. And of the first field
The method of scanning and the method of scanning the second field are alternately performed.
Interlaced color television
Signal.   By the way, such sensors as electronic cameras
When used in a device that obtains still images by shutter operation
In the sensor only by reading the signal for one field
Image information is interlaced because it disappears.
Signal (frame signal) cannot be obtained.   Therefore, conventionally, Japanese Unexamined Patent Application Publication No.
1H (H is the horizontal scanning period)
To form a frame signal with only one field scan
To create two field signals at the same time
Had been. FIG. 5 shows the configuration diagram.   5, 8, 101, 102, 103 and 104 in FIG. 5 are the same as in FIG.
It is. 91 and 92 are 1H delay circuits, 671 and 672 are
Described above using the signals w, g, cy, and ye output from the sensor 1.
An arithmetic operation is performed to generate a luminance signal Y and color signals r and b.
It is a tricks circuit.   In the above configuration, a shutter (not shown)
When the semiconductor device 1 is exposed, the drive scanning circuit 8 first outputs l₁
And l_Two, Then l_ThreeAnd l_FourScanning the first field and so on
Are performed, w and g are output terminals 101 and 102, and output terminal 103 is output.
Cy and ye are output to and 104. Obtained w, g, cy and ye
Is supplied to the matrix circuit 671 as it is. This result
As a result, the luminance of the first field is obtained from the matrix circuit 671.
The signal Y and the color signals r and b are obtained.   On the other hand, w and g are not changed,
y and ye are supplied through 1H delay circuits 91 and 92. Accordingly
Scanning of the first field with respect to the sensor 1
Then, w, g, cy and y supplied to the matrix circuit 672
e is first l_TwoAnd l_ThreeAnd then l_FourAnd l_FiveAnd so on.
The combination is the same as when field scanning is performed.
As a result, the second field is output from the matrix circuit 672.
And the color signals r and b are obtained.   The conventional device described above has two filters interlaced with each other.
Can be obtained, but only at the same time
There is a problem due to the lack. That is, on
The signal obtained as described above can be
VTRs and video floppy devices used in electronic cameras
If you try to record by VTR or video floppy
Originally, two video signals were recorded simultaneously.
Is not possible or difficult because it is not
That is to say. First, in a VTR, two video signals are
Is impossible to record. Also video floppy
In the device, the two video signals are inferior in image quality due to the restrictions described below.
It is difficult to record at the same time without conversion.   That is, in a video floppy device, concentric
To record a signal for one field per track
You. Record two interlaced field signals
Use two adjacent tracks. At this time,
The recording start point of the track is on the turning radius of the video floppy.
Must be aligned. Therefore, the above two fees
When recording a blank signal at the same time, two adjacent heads
Will be used. However, with a video floppy device
Has a track pitch of 100 μm and a track width of 60 μm
Therefore, the distance between the two heads is only 40 μm. Note for this
Significant image degradation due to crosstalk between heads during recording
Unsatisfactory image quality cannot be obtained.   Therefore, using the above-described conventional technique, two fields
Even if you can get a signal, you can convert it to a traditional VTR or video
It cannot be recorded by a floppy device. For this reason
In addition, the two-line simultaneous readout type sensor
Frame still images are not actually taken
Was. [Problems to be solved by the invention]   The above prior art uses a two-wire simultaneous readout type sensor.
Two interlaced with each other in still image capture
Field signals can be obtained,
Signal can be obtained only
Can be recorded by a VTR or video floppy device.
There was no problem.   It is an object of the present invention to use widely in conventional video cameras.
Image capture using two-line simultaneous readout sensor
Two fields interlaced with each other in the image
The signal can be recorded with a conventional VTR or video floppy device.
To easily record high-quality frame still images
An object of the present invention is to provide an imaging device that can be realized. [Means for solving the problem]   The above purpose is to convert the output signal of the sensor for one field.
Memory that can be stored as is or two files created simultaneously
Memory for storing at least one of the
To get two field signals at different times
Is achieved. [Action]   One field of the output signal of the sensor is stored as it is.
If memory is provided, what is stored in the memory?
It does not disappear even if read multiple times, so the memory
By reading the contents,
The first field signal or the second field signal
Field signal, so that the first field
The second field signal and the second field signal at different times.
Can be.   At least one of two field signals produced simultaneously
If you have a memory to store
Output with a delay of the field signal
To obtain two field signals at different times.
Can be 〔Example〕   Hereinafter, the present invention will be described with reference to the drawings.   FIG. 1 is a schematic block diagram of one embodiment of the present invention.
You. In the figure, reference numeral 1 denotes a sensor similar to that of FIG.
Is a semiconductor memory (hereinafter simply called memory), 3 is a memo
Re-control circuit, 4 is A / D converter, 5 is D / A converter, 6 is brightness
Matrix circuit for signal reproduction (hereinafter referred to as Y matrix)
And 7 are color signal reproduction matrix circuits (hereinafter referred to as C matrices).
8 is a drive scanning circuit 60 similar to that shown in FIG.
1,701,702 are output terminals.   In FIG. 1, a shutter (not shown) is used to
After the sensor 1 is exposed, the sensor 1
W, g, cy and ye obtained by scanning are A / D
The digital signal is converted by the conversion unit 4 into a digital signal.
Is stored. One field by the drive scanning circuit 8
When the scanning is performed, all the data stored in the sensor 1
The image information is stored in the memory 2. Then all images
W, g, cy and ye are read from the memory 2 storing the information
The analog signal is restored by the D / A converter 5 and
The trix 6 and the C matrix 7 are supplied. Y Mat
In the Rix 6 and the C matrix 7,
Therefore, the luminance signal Y is output from the output terminal 601.
Terminals 701 and 702 output color signals r and b.
You.   When reading w, g, cy and ye from memory 2,
First, as in the case of reading from sensor 1,
Line l₁And l_TwoInformation corresponding to, then l_ThreeAnd l_FourInformation corresponding to
Information, and so on. One field of communication
Is obtained, then l_TwoAnd l_ThreeInformation corresponding to the l_FourAnd l_Five
Read out the information corresponding to the
Get the signal of the field. As described above, the output terminal 601
The luminance signal Y of the frame signal and the output terminals 701 and 702
The color signals r and b of the frame signal can be obtained.   Also, first l₁And l_TwoInformation corresponding to the second l_TwoAnd l_Three
Information corresponding to the third, l_ThreeAnd l_FourInformation corresponding to
Non-interlaced by reading in a combination
Can be obtained. That is, for example, NTSC
In the imaging device for the expression, the reading speed from the memory 2 and the
And double the conversion speed of the D / A converter 5
If scanning is performed, 60 fields / second, 525 scanning lines
/ Field non-interlace signal can be obtained
You.   As described above, in the present embodiment, reading from the memory 2 is performed.
By changing the order of the frame signals,
Source signal can be obtained.   In addition, in this embodiment, the contents of the memory 2 are repeatedly read.
Of the frame signal or non-in
It is possible to repeatedly output the lace signal.
If you connect the output of the
Images can be displayed. Therefore, the static
Record still images on a recording medium such as a magnetic disk or magnetic tape
If you try to use a still image taken before
Check that the still image is suitable for recording
If you decide whether or not to record,
It is effective for effective use of recording media.   Next, a specific example of storing w, g, cy, and ye in the memory
State. 4 (a) to 4 (c) respectively show A /
A block diagram showing a specific example of the D conversion unit 4 and the memory 2
FIG. First, in FIG. 4 (a), 201, 202,
203 and 204 are memories, and 401, 402, 403 and 404 are A / D converters.
You. Fig. 3 shows the waveforms of w, g, cy, and ye output from sensor 1.
a) and b). w and cy, g and ye are the same
Imming. In the specific example shown in FIG.
(Cy) and g (ye) are the values shown in Fig. 3 c) and d), respectively.
A / D conversion is performed by locks S1 and S2. Each A / D converter 401-404
Samples the input signal at the rising edge of the clock
And converts it to digital data of about 6 to 8 bits.
Are output in parallel. The output data is
It is held until the clock rises. Therefore, A / D converter 4
Outputs of 01 and 402 are as shown in FIGS. 3 e) and f). these
For data, write clocks S2 and S1 shown in d) and c) of FIG.
It is written to the memories 201 and 202 as the embedded clock. Me
Writing to memory is performed according to the rising edge of the clock.
Writing is performed. The same applies to cy and ye.
With such a configuration, reading from the memory is performed by w, g,
cy and ye can be done at the same time.
Sample and hold circuit and latch for time alignment
No circuit needed.   In the specific example shown in FIG. 4 (b), w and g, cy and ye
Time-division multiplexing is stored in the memory. 401,402,403,40
4 is the same A / D converter as in FIG. 5A, 205 and 206 are memories, 21
1,212 is a multiplexer. Output of A / D converters 401 and 402
The force is as shown in FIG. 3 e), f). Multiplexer 211
Switches between them and supplies them to the memory 205. Switching control signal
The signal uses S3 shown in Fig. 3 g). S3 is low level (hereinafter
When the output of 401 is at the low level,
gh), the output of 402 is selected. Accordingly
Thus, the output is as shown in FIG. Receiving this
In the memory 205, ▲ ▼ shown in FIG.
Writing is performed as a clock. About cy, ye
The same is true for With such a configuration, the memory data
Since the number of wires is half that of the above (a), the circuit
The scale can be reduced. However, instead of memory
Operating speed must be doubled.   The specific example shown in FIG. 4 (c) performs A / D conversion.
This is a case where w and g and cy and ye are multiplexed before. 405,406 is A
The / D converters 205 and 206 are the same memory as in FIG.
You. FIG. 3 j) is obtained by adding w and g. this
In the A / D converter 405 using CLK shown in FIG. 3 k).
After / D conversion, the output is as shown in FIG. 3 l). did
A / D converter 4 using ▲ ▼ as write clock
What is necessary is just to write the output of 05 in the memory 205. about cy and ye
It is the same as above. According to this configuration, there are two A / D converters.
Thus, the circuit scale can be significantly reduced. Was
However, since the speed of A / D conversion is doubled, high-performance A / D conversion
A heat exchanger is preferred.   Note that each clock CLK, ▲
▼, S1, S2, S3 can be easily obtained from the drive scanning circuit 8.
it can.   In the time division multiplexing method described above, the A / D converter and the
And / or memory speed must be increased
Would exceed the capabilities of these elements in this case
Can be considered. However, in this embodiment, from the sensor
The overall operating speed by reducing the read speed of the
Can be slowed down, regardless of the performance of the device.
Instead, time division multiplexing can be performed.   Here, w, g, and w are stored in the respective memories of FIGS. 4 (a) to 4 (c).
An address specification for writing cy, ye will be described.
FIG. 21 shows a write address of the memory control circuit 3.
FIG. 3 is a block diagram showing a part to be executed. In FIG.
And H are the vertical synchronizing signal obtained from the drive scanning circuit 8 and
And horizontal synchronizing signals. CC and AC are also drive scan times.
The clock of the column address counter obtained from
And addressing pulses. 310 is the vertical synchronization signal V
It is reset (cleared) at the rising edge and the horizontal synchronization signal H
Count up one by one according to the rise, and count
The value is stored in each row of the memory shown in FIG. 4 (a), (b) or (c).
A row address generation counter that outputs as an address
You. 311 is reset at the rise of the horizontal synchronization signal H
(Cleared), one by one according to the rising edge of the clock CC
Counts up and stores the count value in the column address of the memory.
Is a column address generation counter which is output as "1".   The clock CC is the same as the write clock of each memory.
One signal is used. Therefore, the clock shown in FIG.
CC is S1 and S2, and the black CC in FIGS. 4 (b) and (c)
Check CC is ▲ ▼. Also, addressing pulse
AC is S2 if the write clock of each memory is S1,
In the case of S2, it becomes S1, and in the case of ▲ ▼, it becomes CLK. that's all
As is clear from FIG. 21, the structure of FIG. 21 with respect to FIG.
Consists of column address and addressing pulse AC respectively
Two systems are required.   Writing to each memory in FIG. 4 (a), (b) or (c)
In response to the rise of the addressing pulse AC,
The memory number indicated by the row address and column address at that time
The land is selected. Next, the write clock rises
And the data is written to that address
You.   Next, reading from the memory, Y matrix and C
A specific example of the matrix will be described.   FIG. 6 shows a case where the memory configuration is as shown in FIG. 4 (a).
FIG. 14 is a block diagram showing a specific example of a reading side in the case. same
In the figure, 201, 202, 203, 204 are memories, 501, 502, 503, 5
04 is D / A converter, 61 is Y matrix and C matrix
611 is a changeover switch, 601, 70
1,702 is an output terminal.   In FIG. 6, all the memories are shown in FIG. 7a).
Since reading is performed using S2 'as the reading clock,
The output is represented by FIG. 7b). All D /
The A converter receives this and crosses S1 'shown in Fig. 7c).
D / A conversion is performed as
Become representative. In the matrix circuit 61,
When a matrix operation is performed between these outputs, output terminals 601,
Y, r, and b are output to 701 and 702, respectively. Selector switch
611 makes Y by switching between w + cy and g + ye. Its control
The signal is S3 'shown in FIG. 7 e), and when high, w + c
Select g + ye for y and Low.   FIGS. 8 (a) and 8 (b) show that the memory configuration is the fourth.
One device on the reading side in the case as shown in FIGS.
It is a block diagram which shows a body example. First, regarding FIG.
explain. 205, 206 are memory, 501, 502, 503, 504 are D / A conversion
Converter, 771,772 is a sample and hold circuit, 61,601,701,70
2 is the same as that of FIG.   In FIG. 8 (a), ▲ shown in FIG. 17a)
Reading from memory 205 is performed by ▼ '
Then, the output of the memory 205 is as shown in FIG. Then D
The / A converters 501 and 502 respectively use S2 ',
D / A conversion is performed using S1 'shown in d) as a clock.
Therefore, the output is as shown in e) and f). That is, w and g
Is obtained. For time alignment, w
Sample and hold at clock S1 'in the hold circuit 771
Then, FIG. 17 g) is obtained. The same applies to cy and ye
You. The obtained signal is input to the matrix circuit 61 and output
Y, r, b are obtained from the children 601, 701, 702. Switching system for making Y
The control signal is the same as in the example of FIG. 6 at S3 'shown in FIG.
is there.   Next, FIG. 8B will be described. 505,506 is D / A change
773,774,775,776,777,778 are sample-and-hold times
The roads 205, 206, 61, 601, 701, and 702 have the same reference numerals in FIG.
It is the same as the one.   In the memory 205 of FIG. 8 (b), the CLK 'of FIG.
Since the reading is performed as lock, the output is
It becomes like b).   Next, in the D / A converter 505, ▲ shown in FIG.
▼ 'is used as a clock to perform D / A conversion.
Is as shown in FIG. This is sample hold times
At roads 773 and 775
Sample is held by locks S2 'and S1'.
(F) and (h) are obtained. For time adjustment, w
At the clock S1 'in the sample-and-hold circuit 777.
The sample is held to obtain FIG. 18 i). About cy and ye
The same is true for Subsequent processing is the same as in the example of FIG.
The same. With this configuration, there are two D / A converters.
I'm done. However, it is necessary to move the D / A converter twice as fast
Yes, and if the level difference between w and g, cy and ye is large, D / A
High-performance D / A converter due to large fluctuation of conversion output
Is required.   By the way, as described above, in this embodiment,
By changing the reading order of
Both non-interlaced signals can be obtained. here
Changing the order of reading from the memory means
Is the horizontal line of the sensor₁, L_Two, …… one-to-one correspondence
To specify the address in memory (especially the row address)
Changing the procedure. Hereinafter, the memory control circuit
FIG. 9 shows a specific example of a portion for designating the read address 3
This will be described below.   In FIG. 9, L1 is the row address of the w and g signals,
L2 is the row address of cy and ye. That is, L1 is 1
If the sensor horizontal line l₁Information corresponding to the selected
Then, as the following becomes 2,3,4, ……_Three, L_Five, L₇, ……
Is selected. Similarly, L2 is 1,2,3,…
... then l_Two, L_Four, L₆, …… is selected
It is. FIG. 8 shows an oscillator 301 for obtaining a frame signal.
Operation clock when reading from the memory of (b)
Clock CK2, which is twice the frequency of
In the first field, the synchronization signal H2 with twice the frequency of the signal
Field switching signal that goes low and high in the second field
Signal Fi, a vertical synchronizing signal V and a horizontal synchronizing signal H
I do. Divider 302 divides CK2 by 2 and outputs it as clock CK.
Power. When the mode selection signal M is Low
If it is high, output CK; if high, output CK2 as clock CLK '.
Power.   6 and 8 based on this CLK '.
(A) and (b) the operating clock of each memory and its
Other clocks CLK ', ▲ ▼', S1 ', S2', S
3 'and the like are formed in the pulse generation circuit 314. Fig. 22
Is a block diagram showing a specific example of the pulse generation circuit 314.
You. In the figure, reference numeral 313 denotes a flip-flop. Ma
In addition, the addressing pulse A
C is output and the column address generation counter 312
The clock CC to be supplied is output. Note that specifically
Uses the same signal as the clock CC when reading each memory.
I have. Therefore, FIGS. 6 and 8 (a) and FIG.
The clock CC of (b) is S2 'and ▲ ▼' CL, respectively.
K '. The column address generation counter 312
Counts up one by one at the rise of the CC
The count value is output as the column address of the memory. Also,
The addressing pulse AC is used when the write clock of each memory is
S1 'for S2', CLK 'and C for ▲ ▼'
In the case of LK ', it becomes ▲ ▼'.   Divider 304 divides H2 by 2 and outputs horizontal synchronization and line switching signal
Output as number HS. The relationship between H2 and HS is shown in Fig. 13 (a) and
And (b). The counter 305 sets the rising edge of the vertical synchronization signal V.
Reset (clear) by going up, HS is used as clock
Works. The output A1 is as shown in FIG. 13 c). A1
Becomes the row address L1 as it is. The latch circuit 306
Since A1 is latched as a clock, its output A2 is
(D). Multiplexer 307 addresses
If the selection signal AS is low, A1
Output as dress L2. Multiplexer 308 is
If the mode selection signal M is Low, it is Fi, and if it is High, it is HS.
It is output as the address selection signal AS. Multiplexer
309 is H if the mode selection signal M is Low, and High if the mode selection signal M is Low.
Output H2 as a signal HH and supply it to the pulse generation circuit 314.
And to the reset terminal of the counter 312.
You.   In the above configuration, if you want to obtain a frame signal,
The mode selection signal M is set to Low. As a result, the clock CLK '
Becomes CK, so that in FIG. 6, FIG. 8 (a) or (b)
Each part operates at the clock speed required to obtain the frame signal.
Make. Therefore, the frame signal is also obtained from the memory
The reading is performed at the speed required for the reading. On the other hand, AS
In the first field, both L1 and L2 are A1
And the combination of signals to be read is l₁And l_Two, L_ThreeWhen
l_Four, ......, so that the read signal
One field signal can be obtained. Also, the second
In the field, L1 becomes A1, L2 becomes A2, and the combination is l_TwoWhen
l_Three, L_FourAnd l_Five, ……, so the second field
A signal can be obtained.   Next, when you want to obtain a non-interlaced signal,
The selection signal M is set to High. As a result, the clock CLK 'becomes C
K2, so each of FIGS. 6, 8 (a) and (b)
Section is twice the clock speed required to obtain the frame signal
Operates at speeds. Therefore, the frame from memory
The reading is performed at twice the speed required to obtain the signal.
Be done. At this time, AS becomes HS, so L2 is
(F). On the other hand, L1 is as shown in (e). I
Therefore, l₁And l_Two, L_TwoAnd l_Three, L_ThreeAnd l_Four,……When
Signals are read out at the double speed in this order. As a result, double speed
Can be obtained.   Note that the column address of each memory is
It will be clear that this is determined by the event value. Ma
In addition, from each memory of FIG. 6, FIG. 8 (a) or (b)
In fact, the rising edge of the addressing pulse AC
Depending on the row and column address at that time.
Memory address is selected, and then the read clock
The data written to the address selected according to the rise
Data is read.   This is the end of the description of the embodiment relating to FIG.   FIG. 10 is a block diagram showing another embodiment of the present invention.
You. In the figure, 6 'is a Y matrix, 7' is a C matrix.
Rix, 51, 52 and 53 are D / A converters, 601 ', 701' and
And 702 'are output terminals. Others are the same as those in FIG.
Indicates the same or equivalent part. Therefore, in this embodiment,
Configuration until image information is written in memory 2
The operation is the same as that of the embodiment relating to FIG.
You. Also, frame signals or non-interlaced signals
Reading information from memory 2 to obtain
Are the same as those described with reference to FIG.   Now, in the present embodiment, the data read from the memory 2
The digital signal is a Y matrix 6 'and a C matrix.
7 '. Y matrix 6 'and C matrix
In step 7 ', digital luminance is calculated using these signals.
The signal Y and the color signals r and b are calculated. The calculated Y, r and
And b pass through D / A converters 51, 52 and 53, respectively.
And output to the output terminals 601 ', 70
Output to 1 'and 702'. According to this embodiment, the first
As in the embodiment shown in FIG.
A television receiver that repeatedly outputs interlaced signals
Can be displayed. Also, read from sensor 1
Speed is arbitrary, regardless of the output signal format
Can be. Further, as an effect peculiar to the present embodiment, Y mat
Rix 6 'and C matrix 7' by digital circuit
Configuration so that the reliability of the circuit can be improved.
You. In addition, as will be described later, the signal can be easily transmitted using a latch circuit.
Signal can be delayed,
The circuit can be simplified as compared with using a road.   Here, reading from the memory and Y matrix and
A specific example of the C matrix will be described. Figure 11 shows the memory
Of the reading side when the configuration of FIG. 4 is as shown in FIG.
It is a block diagram which shows a specific example. In the figure, 201,
202, 203, 204 are memories, 51, 52, 53 are D / A converters, 601 ', 70
1 'and 702' are output terminals, 611 'is a multiplexer, 661,6
62 is a sign inverter.   In FIG. 11, all memories are stored in the memory shown in FIG.
Since reading is performed by lock S1 ', the output
Are represented in FIG. 19 b). Gain in this way
Digital operation is performed between the obtained data,
Obtain Y, r, b as digital data. In addition, multi
Plexa 611 'switches between w + cy and g + ye to create Y
The control signal uses S3 'shown in Fig. 19c).
I have. That is, when S3 'is High, w + cy is Low,
At this time, g + ye is selected. The first obtained in this way
Y shown in Fig. 19 d) is determined by ▲ ▼ 'in Fig. 19 e).
D / A conversion is performed. R and b are the same as Y and time.
D / A using ▲ ▼ 'shown in Figure 19f) as a clock
Is converted. Note that the memory read clock is S1 '
The clock CC is S1 'and the addressing pulse is S2'.
You.   FIG. 12 shows the configuration of the memory shown in FIGS. 4 (b) and (c).
Block that shows a specific example of the read side when
FIG. 205 and 206 are memory, 771 'and 772' are latch times
Roads, 661,662,51,52,53,601 ', 701', 702 '
It is the same as the sign.   In FIG. 12, the read clock from the memory is
20 It will be ▲ ▼ 'shown in Fig. A). Y and C mat
The output of the memory itself and the
The output is latched by latch circuits 771 'and 772', respectively.
And are supplied. Same as latch circuit clock
The output after latching is small because ▲ ▼ 'is used.
One clock later. Output of memory 205, its latch
The output of the memory 206 and its latched
Are shown in Fig. 20 b), c), d) and e). These digital
From the data, Y, r, b are digitally calculated in the calculation unit
Is done. That is, first, c) and e) in FIG. 20 are added.
To obtain f). Then, this is converted into D / A by CLK 'shown in i).
In other words, analog Y is obtained. Next, c) and d) in FIG.
The sum of b) and e) is subtracted from the sum of
As described above, data of r is obtained every other cycle. Figure 20
Subtract the sum of b) and d) from the sum of c) and e)
Then, as shown in h), data b is obtained every other cycle.
Then, these data are D / A converted by S1 'shown in j).
To obtain analog r and b. According to this configuration,
Although two switch circuits are required, the number of adders is
Circuit is small because there are few
can do.   This is the end of the description of the embodiment relating to FIG.   FIG. 14 is a block diagram of another embodiment of the present invention. same
In the figure, 1 is a sensor, 2 and 2 'are memories, 4 and
And 4 'are A / D converters, 5 and 5' are D / A converters, and 8 is
Drive scanning circuit for sensor 1, 9 for 1H delay circuit, 10 for switching
Switches 105 and 106 are output terminals of the sensor 1. Ma
Also, a circuit that combines the Y matrix and C matrix
These are represented as matrix circuits 671 and 672, respectively.   The actual output of the sensor 1 in this embodiment is four.
But here, it is expressed in two.
You. That is, the sensor 1, the drive scanning circuit 8, the output terminal 10
5, 106, 1H delay circuit 9, matrix circuit 671, 672 part
Has the same configuration as the conventional example shown in FIG.
It is driven in the same manner as in the conventional example. In this embodiment,
A / D converters 4 and 4 ', memories 2 and 2', D
The specific configuration of the / A converters 5 and 5 'is Y, r, b, respectively.
These are provided independently.   With the above configuration, the first filter is provided from the matrix circuit 671.
Fields Y, r, b are output from the matrix circuit 672 to the second field.
Y, r, and b are output, and these outputs are A / D converted.
Are converted into digital signals by the conversion units 4 and 4 ',
Stored in 2 '. Next, when obtaining a frame signal
First reads Y, r, b of the first field from memory 2.
This is passed through the D / A converter 5 and the changeover switch 10.
And output. Then, the changeover switch 10 is switched.
Read Y, r, b of the second field from the memory 2 '.
And output through the D / A converter 5 '. This
Thus, a frame signal can be obtained.   When obtaining a non-interlaced signal,
From 2 and 2 ', reading is performed alternately by one scan, and
The read signal is switched through the D / A converters 5, 5 '.
It is supplied to the switch 10. In the changeover switch 10, the memory
The switching is performed in synchronization with the reading of data. This
Thus, a non-interlaced signal can be obtained.   According to this embodiment, the method of reading from the memory and the switching
Frame signal and noise by changing the operation of the conversion switch.
And an interlaced signal. Also this
These signals are repeatedly output and displayed on the television receiver
You can also. Furthermore, the band of the color signal is
The advantage is that even if it is slightly narrower, it has almost no visual effect.
To reduce the memory capacity for the color signals r and b.
Can also be. In this embodiment, scanning for one scanning line is performed.
Since the delay time is defined by the 1H delay circuit 9, the sensor
The reading speed from 1 cannot be made arbitrary.   By the way, when writing to the memories 2, 2 'of this embodiment,
The necessary row addresses and column addresses are the same as in FIG.
It is obtained by a similar configuration. In this embodiment,
The case of obtaining the above frame signal and the case of non-interlaced
Change how to read from memory when obtaining a signal
The control can be realized by the configuration shown in FIG. That is, the book
In the embodiment, both the row addresses of the memories 2 and 2 'are L
Use 1, if L1 is 1, the first scan in each field
The information corresponding to the line is selected.
3, so that the information corresponding to the scanning lines is selected.
You. In addition, AS is used for controlling the switch 10. Sand
If AS is Low, memory 2 (first field), Hig
If h, memory 2 '(second field) is selected
To do. If you use this method,
The latch circuit 306 and the multiplexer 307 become unnecessary.
This will be further described below.   When you want to obtain a frame signal, the mode selection signal M is Low
At the speed necessary to obtain the frame signal.
Reading from the memory is performed. Also, at this time, AS
Field switching signal Fi.
Memory 2 or memory 2 'is selected in response to the
Output from 10. Therefore, from the output of switch 10,
Gives a frame signal. In addition, double speed non-interlace
Mode signal, the mode selection signal M goes high.
At twice the speed required to obtain the frame signal.
Reading is performed from the memory. And at this time
Since the control signal of the switch 10 becomes the HS shown in FIG. 13 b),
The output of the switch 10 is the first scan line of the second field,
1st scan line of 1 field, 2nd scan of 2nd field
Line, second scan line in the first field, etc.
Thus, a double-speed non-interlaced signal is obtained.   The A / D converters 4 and 4 'are provided with a matrix circuit 671.
And may be before 672. A / D converters 4 and 4 '
May be further before the 1H delay circuit 9, and in this case,
The structure of this part is as shown in FIG.
A / D converters 41 and 42 are provided instead of
Matrix circuits 671 ', 6 instead of matrix circuits 671,672
72 'will be provided. Also do this
And using the line memory 11 instead of the 1H delay circuit 9.
Can be. When the line memory 11 is used, the sensor 1
Can be set to any reading speed. Also, D / A
The converters 5 and 5 'are also provided after the changeover switch 10.
In this case, the configuration of this part is shown in FIG.
Thus, the changeover switch 10 'and the D / A converter 5 "are provided.
, The changeover switch 10 'is set to a digital switch.
Switch, and the number of D / A converters is halved.
You.   Here, the A / D conversion in the embodiment having the configuration shown in FIG.
The specific configuration of the switching units 41 and 42 and the matrix circuits 671 'and 672'
I will talk about it. The configuration of the A / D converter is shown in FIG.
It can be the same as the same part of (b) or (c).
The output of the A / D converter when the same configuration as in FIG. 4A is used.
Are represented by FIGS. 3 e) and f). Accordingly
Therefore, as a configuration of the matrix circuits 671 ′ and 672 ′,
First, time alignment is performed using a latch circuit, etc.
Matrix operation is performed with the same configuration as the matrix section in FIG.
You can do it. Also, the A / D converter is shown in FIG.
If the same configuration as in c) is used, the matrix circuit 671 'and
And 672 'may have the same configuration as in FIG.   In the embodiment shown in FIG.
Frame signal and double-speed non-interlaced signal.
The protrusion control may be the same as in the embodiment of FIG. did
Therefore, the row address of the memory 2, 2 'at the time of reading is
As a control signal for L1 and switch 10 'in FIG.
Will be used.   FIG. 16 is a block diagram of another embodiment of the present invention.
In this embodiment, the memory 2 is taken from the embodiment shown in FIG.
Excluded. That is, in this embodiment, the first filter is used.
Y, r, b are output in real time,
2 fields are stored in the memory 2 '. Then
The contents of memory 2 'are read out, and Y,
r and b are output. Thus, a frame signal is obtained.   Therefore, in this embodiment, a non-interlaced signal is obtained.
I can't do that, and repeatedly output the frame signal
It cannot be displayed on a television receiver. However
While, the frame capacity is half that of the embodiment of FIG.
Signal can be obtained.
This is useful when recording on a recording medium as it is. 〔The invention's effect〕   According to the present invention, a two-wire simultaneous readout type sensor is used.
Two interlaced with each other in still image capture
Of different field signals at different times
High-definition frames on conventional VTRs and video floppy devices.
This has the effect that a still image can be easily recorded.   According to the present invention, the low frequency component of the luminance signal is of course
Vertical resolution for high frequency components and color signals
The effect that the degree does not deteriorate can be achieved
You.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1, FIG. 10, FIG. 14, FIG. 15, and FIG. 16 are block diagrams of an embodiment of the present invention, respectively, FIG. FIG. 3 is a time chart for explaining the operation of FIG. 4 described later, FIG. 4 is a block diagram showing a specific example of a main part of FIG. 1, and FIG. 5 shows an example of a conventional imaging apparatus. FIG. 6 is a block diagram showing a specific example of another main part of FIG. 1, FIG. 7 is a time chart for explaining the operation of FIG. 6, and FIG. FIG. 11 is a block diagram showing a specific example of a portion for designating a read address of the memory control circuit of FIG. 1, and FIGS. 11 and 12 are block diagrams showing specific examples of main parts of FIG. 10, respectively. Is a time chart for explaining the operation of FIG. 9, and FIGS. 17 and 18 are time charts for explaining the operation of FIG. 19 and 20 are time charts for explaining the operation of FIGS. 11 and 12, and FIG. 21 is a block diagram showing a specific example of a portion for specifying a write address of the memory control circuit of FIG. FIG. 22 is a block diagram showing a specific example of the pulse generation circuit of FIG. 1 ... Sensor, 2,2 '... Memory, 3 ... Memory control circuit, 4,4', 41,42 ... A / D converter, 5,5 ', 5 ", 51-53 ...
D / A converter, 6,6 '... Y matrix, 7,7' ... C matrix, 8 ... Drive scanning circuit, 9 ... 1H delay circuit, 10,1
0 ': Changeover switch, 11: Line memory, 105, 106 ...
... Output terminals, 671,671 ', 672,672' ... Matrix circuit

Claims (1)

(57) [Claims] In an imaging apparatus for simultaneously reading out two adjacent horizontal lines from an imaging device in which a plurality of color filters are two-dimensionally arranged in a predetermined repetition order, one horizontal signal of two horizontal lines read from the imaging device is provided. Delay means for generating a combination of two horizontal lines shifted by one horizontal line by delaying the signal of the line by one horizontal scanning period; and a first luminance based on the signals of the two horizontal lines read from the image sensor. First signal generating means for generating a signal and a chrominance signal; second signal generating means for generating a second luminance signal and a chrominance signal based on two horizontal line signals obtained from the delay means; First storage means for storing the first luminance signal and color signal for one field; and storing the second luminance signal and color signal for one field. A second storage means for reading a signal stored in one of the first and second storage means as a luminance signal and a chrominance signal of the first field, and reading the signal as a luminance signal and a chrominance signal of the second field; An image pickup apparatus comprising: a signal output unit that reads out a stored signal to output a frame image signal including two fields of a luminance signal and a color signal that are interlaced with each other or a frame image signal that is not interlaced. apparatus. 2. In an imaging apparatus for simultaneously reading out two adjacent horizontal lines from an imaging device in which a plurality of color filters are two-dimensionally arranged in a predetermined repetition order, one horizontal signal of two horizontal lines read from the imaging device is provided. Delay means for generating a combination of two horizontal lines shifted by one horizontal line by delaying the signal of the line by one horizontal scanning period; and a first luminance based on the signals of the two horizontal lines read from the image sensor. First signal generating means for generating a signal and a chrominance signal; second signal generating means for generating a second luminance signal and a chrominance signal based on two horizontal line signals obtained from the delay means; Field storage means for storing one of the first luminance signal and the color signal and the second luminance signal and the color signal for one field; By selecting one of the signal read from the field storage means as the luminance signal and the color signal of the second field and the signal not stored in the field storage means, and selecting the other as the luminance signal and the color signal of the second field. An image pickup apparatus comprising: signal output means for outputting a frame image signal composed of a luminance signal and a color signal of two fields interlaced with each other.