JP2696952B2 - Power supply circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch for preventing a latch-up phenomenon caused by different power supply voltages when a signal is exchanged between digital circuits constituted by C-MOS. The present invention relates to a power supply circuit capable of reducing an up prevention circuit.

2. Description of the Related Art An example of a conventional power supply circuit will be described below with reference to the drawings.

FIG. 4 shows a conventional power supply circuit. 4th
In the figure, 1 and 2 are power supplies, and 3 and 10 are DC stabilized power supplies, which output the same voltage. 5 and 6 are C-MOS
, And 9 is a latch-up prevention circuit.

The operation of the power supply circuit configured as described above will be described below.

The digital circuit 5 is supplied with power from the power supply 1 via the stabilized DC power supply 3, and the digital circuit 6 is supplied with power from the power supply 2 via the stabilized DC power supply 10. , Signals are exchanged via the latch-up prevention circuit 9. Here, when the power supply 1 or 2 is reduced in voltage and the voltage falls below a region where the output voltage of the DC stabilized power supply 3 or 10 can be stabilized, the digital circuit 5
And the power supply voltage of the digital circuit 6 is different. When the digital circuit 5 and the digital circuit 6 are configured by C-MOS,
The maximum input voltage of the input port is generally the power supply voltage V _DD +0.3 V of the digital circuit having the input port,
A latch-up prevention circuit 9 is provided so that the power supply voltage difference is not applied to the input port.

Figure 5 is shows a specific circuit configuration of the latch-up prevention circuit 9 in the signal transfer between the digital circuit 5 and the digital circuit 6, in FIG. 5, PO5 ₁ ~PO5 _n is the output of the digital circuit 5 port, PI5 ₁ ~PI5 _n input ports of the digital circuit 5, PI6 ₁ ~PI6 _n input ports of the digital circuit 6, PO6 ₁ ~PO6 _n output ports of the digital circuit 6, Rf
_{1 ~Rf n} is a pull-up resistor for pulling up the input port PI6 ₁ ~PI0 _n digital 6 to the power supply voltage of the digital circuit 6, Rr ₁ ~Rr _m input port PI5 ₁ ~PI5 _m digital circuit 5
The a pull-up resistor for pulling up the power supply voltage of the digital circuit 5, Df ₁ ~Df _n anode input port PI6 ₁ ~
The cathode is connected to PI6 _m is diode connected to the output port _{PO5 1 ~PO5 n, Dr 1 ~Dr} n input ports PI5 ₁ ~
Connected to PI5 _n, a diode having a cathode connected to the output port PO6 ₁ ~PO6 _n.

With the above configuration, the output port PO5 ₁ ~PO5 _n or PO6 ₁ ~
When PO6 _m is “H”, the voltage of “H”, that is, the power supply voltage of the digital circuit having the output port is the diode Df
_{Since 1 to} Df _n or Dr _{1 to} Dr _m are in the opposite direction, the input port PI
6 ₁ ~PI6 _n or PI5 not applied to _{1 ~PI5 n,} even if there is a difference in the power supply voltage of the digital circuit 5 and 6 it is possible to prevent the occurrence of latch-up phenomenon.

However, in the above-described configuration, the latch-up prevention circuits must be provided by the number of ports that exchange signals between digital circuits. A large number of components are required, a large mounting area on a printed circuit board is required, and a large material cost is required for the latch-up prevention circuit.

SUMMARY OF THE INVENTION In view of the above problems, the present invention reduces the latch-up prevention circuit, thereby reducing the mounting area of the latch-up prevention circuit on a printed circuit board and reducing the material cost of the latch-up prevention circuit. Circuit.

Means for Solving the Problems In order to solve the above problems, a power supply circuit of the present invention comprises:
A first stabilized DC power supply for supplying power from a first power supply to a first digital circuit constituted by a C-MOS;
A power supply is supplied from the power supply to a second digital circuit composed of the other C-MOS that exchanges signals with the first digital circuit, and the output voltage of the first DC stabilized power supply is used as a reference voltage. And a second stabilized DC power supply that outputs the same voltage as the voltage.

According to the present invention, since the output voltage of the second stabilized DC power supply uses the output voltage of the first stabilized DC power supply as a reference voltage, the output voltage of the second stabilized DC power supply is always the same as that of the first stabilized DC power supply. Voltage can be obtained, and the output voltage of the second stabilized DC power supply can be reduced to the first stabilized DC voltage even when the first power supply is reduced in voltage and the output voltage of the first stabilized DC power supply decreases. It becomes equal to the output voltage of the power supply. When the voltage of the second power supply decreases, the output voltage of the second stabilized DC power supply decreases and becomes lower than the output voltage of the first stabilized DC power supply. That is, when the voltage of the first or second power supply is reduced, the relationship of the power supply voltage of the first digital circuit ≧ the power supply voltage of the second digital circuit always holds. Therefore, it is only necessary to provide a latch-up prevention circuit between the output port of the first digital circuit and the input port of the second digital circuit to be paired, and the number of latch-up prevention circuits can be reduced.

Embodiment Hereinafter, a power supply circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a power supply circuit according to an embodiment of the present invention. In FIG. 1, 1, 2, 3, 5, and 6 have the same configuration as the conventional one. Reference numeral 4 denotes a stabilized DC power supply. Reference numeral 7 denotes a reference voltage input terminal of the stabilized DC power supply 4. The output voltage of the stabilized DC power supply 4 generates the same voltage as the reference voltage.
8 is a latch-up prevention circuit. Power is supplied to the digital circuit 5 from the power supply 1 via the DC stabilized power supply 3,
Power is supplied to a digital circuit 6 which transmits and receives signals via a digital circuit 5 and a latch-up prevention circuit via a stabilized DC power supply 4 in which an output voltage of the stabilized DC power supply 3 is input to a reference voltage input terminal 7. Is done.

The operation of the power supply circuit configured as described above will be described below with reference to FIGS.

First, FIG. 2 shows an example of a circuit of the stabilized DC power supply 4, in which Tr ₁ and Tr ₂ are transistors, D ₁ is a diode, R
Reference numeral ₁ denotes a resistor. The emitter of the transistor Tr ₁ is connected to the power supply 2, power is supplied from the collector of the transistor Tr _{1 to} the digital circuit 6, and the base of the transistor Tr ₂ serves as the reference input terminal 7. One the other is grounded is connected to the emitter of the transistor Tr ₂ resistor R ₁ and the transistor Tr ₂
When the voltage V _{R1 at} the connection point with the emitter of the transistor Tr ₂ is V _be , the base voltage and the emitter voltage of the transistor Tr ₂ are V _be and the reference voltage is V _ref ,
The _R1 = V _ref -V _be. Furthermore, by the diode D ₁ from the collector of the transistor Tr ₁ is applied is fed back to the connection point between the emitter of the resistor R ₁ and the transistor Tr _2, the forward voltage of the diode D ₁ When _{V f, V O = V f} + V _{R1 = V ref -V be + V} f
Becomes Accordingly, the base of the transistor Tr _1, by matching the characteristics of the forward voltage characteristics of the emitter voltage and the diode D _1, the same output voltage and the reference voltage is obtained at the collector of the transistor Tr _1.

By inputting the output voltage of the stabilized DC power supply 3 to the reference voltage input terminal 7 of the stabilized DC power supply 4, the power supply 1 is reduced in voltage. 4 also becomes the same voltage as the output voltage of the stabilized DC power supply 3 in synchronism. When the output voltage of the stabilized DC power supply 4 is reduced due to the reduced voltage of the power supply 2, the stabilized DC power supply 3 is changed from the output voltage of the stabilized DC power supply 4.
Output voltage is higher. That is, when the voltage of the power supply 1 or 2 is reduced, the relationship of the power supply voltage of the digital circuit 5 ≧ the power supply voltage of the digital circuit 6 holds. Therefore, a signal that needs to be provided with a latch-up prevention circuit is transmitted and received only between the output port of the digital circuit 5 and the input port of the digital circuit 6 to be paired, and the output port of the digital circuit 6 to be paired with the input port of the digital circuit 5. No latch-up prevention circuit is required between them, and they can be directly connected.

Figure 3 is shows a specific circuit configuration of the latch-up prevention circuit 8 in the signal exchanges between the digital circuit 5 and 6 in the present invention, the input port in Figure 5 described in the conventional example PI5 ₁ ~PI5 latch-up prevention circuit between the _n and the output port PO6 ₁ ~PO6 _m are removed, those which are directly connected.

As described above, according to the present embodiment, power is supplied from the power supply 1 to the digital circuit 5, and power is supplied to the DC stabilized power supply 3 and the digital circuit 6 that exchanges signals with the digital circuit 5.
By providing an output voltage of the stabilized DC power supply 3 as a reference voltage and providing a stabilized DC power supply 4 that outputs the same voltage as the reference voltage, a latch-up prevention circuit in signal transfer between the digital circuit 5 and the digital circuit 6 is provided. Therefore, the mounting area of the latch-up prevention circuit on the printed circuit board can be reduced, and the material cost of the latch-up prevention circuit can be reduced.

As described above, according to the present invention, the first power supply to the first digital circuit configured by the C-MOS from the first power supply is performed.
And a second digital circuit composed of a C-MOS for transmitting and receiving signals to and from the first digital circuit from the second power supply, and the output of the first DC stabilized power supply. By providing a second DC stabilized power supply that uses a voltage as a reference voltage and outputs the same voltage as the reference voltage, a latch-up prevention circuit in signal transmission and reception between the first digital circuit and the second digital circuit is provided. Can be reduced,
Therefore, the mounting area of the latch-up prevention circuit on the printed circuit board can be reduced, and the material cost of the latch-up prevention circuit can be reduced.

[Brief description of the drawings]

1 is a circuit block diagram of a power supply circuit according to one embodiment of the present invention, FIG. 2 is a circuit connection diagram of a DC stabilizing circuit used in the circuit, and FIG. 3 is a latch-up prevention circuit used in the circuit. FIG. 4 is a circuit block diagram of a conventional power supply circuit, and FIG. 5 is a specific circuit diagram of the latch-up prevention circuit of FIG. 1 ... power supply 2 ... power supply 3 ... stabilized DC power supply 4 ...
... DC stabilized power supply, 5 ... digital circuit, 6 ... digital circuit, 7 ... reference voltage input terminal, 8 ... latch-up prevention circuit.

Claims (1)

(57) [Claims] 1. A first DC stabilized power supply for supplying power to a first digital circuit composed of a C-MOS from a first power supply, and a signal exchange with a first digital circuit from a second power supply. A second DC stabilization circuit for supplying power to a second digital circuit composed of a C-MOS and using the output voltage of the first DC stabilization power supply as a reference voltage and outputting the same voltage as the reference voltage A power supply circuit comprising a power supply.