JP2696067B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device using a dynamic cell in which a memory cell includes a selection transistor and a capacitor for storing data. . 2. Description of the Related Art FIG. 11 is a circuit diagram showing a configuration of a memory cell used in a dynamic semiconductor memory (hereinafter referred to as DRAM). Each memory cell has an MO for selection.
It comprises an S-transistor 31 and a capacitor 32 for data storage, and the drain of the transistor 31 has a data line
A source 33 is connected to one electrode of a capacitor 32, and a gate electrode is connected to a word line 34.
The other electrode of the capacitor 32 is connected to a predetermined potential application point, for example, an earth. A DRA having such a memory cell is provided.
In M, the word line 34 is activated at the time of writing data to make the selection MOS transistor 31 conductive. At this time, the capacitor 32 for data storage is charged or discharged by the potential of the data line 33, and data is written.
On the other hand, when reading data, the word line 34 is activated to turn on the MOS transistor 31 for selection, and the potential of the capacitor 32 for data storage is read out to the data line 33. Will be When such a DRAM is realized by an integrated circuit, each memory cell is conventionally configured as shown in a sectional view of FIG. In other words, in the P-type substrate 40, N ^{+ serving as the} source and drain
Type semiconductor regions 41 and 42 are provided. Both N ⁺ type semiconductor regions 4
On the channel region 43 set between 1 and 42, a gate insulating film 44 interposes a gate electrode of the transistor 33, which is composed of a first polycrystalline silicon layer. A lead line 34 is provided. One electrode 45 of the data storage capacitor 32 made of a polycrystalline silicon layer is connected to the surface of the N ⁺ type semiconductor region 41 serving as the source region of the transistor 31, and N ^{+ serving as} the drain region of the transistor 31. A data line extracting electrode 46 made of a polycrystalline silicon layer is connected to the surface of the type semiconductor region 42. Here, the one electrode 45 of the capacitor 32 and the data line extraction electrode 46 are formed by patterning the same second polycrystalline silicon layer. The one electrode 45 of the capacitor 32 is covered with the other electrode 47 made of a polycrystalline silicon layer via an insulating film as a dielectric for capacitance. The other electrode 47 is formed by patterning a third polycrystalline silicon layer. Further, the data line 33 made of a metal for wiring, for example, aluminum is connected to the data line extracting electrode 46 via a contact hole 48. Here, the data line 33 is not directly connected to the surface of the N ⁺ type semiconductor region 42 as the drain region,
The first reason is that the N ⁺ type semiconductor region 42 has a data line extraction electrode made of the same silicon material.
The reason for this is to connect the data line 33 to the data line take-out electrode 46 with a large contact area by making the contact resistance 46 sufficiently low even with a small contact area. [0007] In a conventional DRAM having a memory cell having such a configuration, a capacitor 32 is used.
Since the one electrode 45 and the data line extraction electrode 46 are formed by patterning the same second-layer polycrystalline silicon layer, the one electrode 45 and the data line extraction electrode 46 are mutually connected. In order to separate them, they must be separated by at least the minimum dimension during patterning. Further, in the case of FIG. 12, in order to increase the capacitance, the other electrode 47 of the capacitor 32 is extended to the side surface of the one electrode 45,
On the other hand, since it is formed so as to be located between the electrode 45 and the data line extraction electrode 46, the dimension between the one electrode 45 and the data line extraction electrode 46 needs to be further increased. For this reason, in the conventional DRAM, there is a problem that the occupied area per cell is large, and it is difficult to achieve high integration. In order to increase the degree of integration, it is conceivable to reduce the area of the capacitor 32 and instead reduce the thickness of an insulating film as a dielectric for capacitance. However, when a 4M bit DRAM chip is housed in a 300 mil package, if a silicon oxide film is used as an insulating film, this film thickness becomes 10 mm.
If not less than nm, 2
A capacitance of about 0 (fF) cannot be obtained. Further, even when a material other than the silicon oxide film is used as the insulating film, the film thickness must be made extremely thin, and it is extremely difficult to put it to practical use. As described above, there is a disadvantage that it is difficult to achieve high integration in a conventional dynamic type semiconductor memory device in which a memory cell is constituted by a selection transistor and a capacitor for data storage. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of manufacturing a highly integrated semiconductor memory device. According to the present invention, there is provided a method for manufacturing a semiconductor memory device, comprising a first conductive member of a first layer on a semiconductor substrate of a first conductivity type via a first insulating film. Forming a gate electrode of the transistor, and forming a source and drain region of the selection transistor comprising the second conductivity type semiconductor region in a self-aligned manner in the base using the gate electrode. Forming a first opening communicating with the surface of the source region of the selection transistor in the second insulating film after depositing a second insulating film on the entire surface; After depositing the conductive member, the conductive member of the second layer is patterned to be connected to the surface of the source region and to be partially connected to the data storage capacitor, a part of which extends to above the gate electrode. A step of forming an electrode and a third insulating film on the entire surface After depositing a third layer, a conductive member of a third layer is deposited, and the conductive member of the third layer is patterned to form a layer on the gate electrode.
On one electrode of the data storage capacitor extending
Side surface of the one electrode on the drain region side and the gate
Continuously cover the side surface of the electrode on the drain region side
Forming the other electrode of the data storage capacitor in a shape ; depositing a fourth insulating film on the entire surface; and selectively removing the second insulating film and the fourth insulating film by a photo-etching method. Forming a second opening leading to the surface of the drain region; and depositing a fourth layer of conductive member after depositing a fourth layer of conductive member.
The conductive member of the layer is patterned to partially cover the fourth insulating member.
It overlaps with the other electrode of the data storage capacitor through a film.
Forming a drain extraction electrode connected to the surface of the drain region so as to overlap with each other. According to the method of manufacturing a semiconductor memory device of the present invention, the other electrode of the data storage capacitor and the extraction electrode from the drain region of the selection transistor are formed of conductive members of different layers. It is not necessary to separate them from each other in a plane. Therefore, the other electrode and the extraction electrode of the data storage capacitor can have a sufficient area. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a memory cell portion of a DRAM manufactured by a method of manufacturing a semiconductor memory device according to the present invention. FIG. 1A is a pattern plan view,
FIG. 1B is a cross-sectional view taken along the line II ′ of FIG. Reference numeral 10 denotes a P-type silicon semiconductor substrate. This board
The 10 source of the common drain region to become the N ⁺ type semiconductor region 11 is formed disposed in a staggered manner, the selection transistors on both sides of the N ⁺ -type semiconductor region 11 of the two select transistors An N ⁺ type semiconductor region 12 serving as a source region is provided. The N ⁺ -type semiconductor region 11 and the two N ⁺ -type semiconductor regions 12 arranged on both sides thereof are formed in one element region 13, and each element region 13 is connected to a field insulating film. Separated by 14. In each of the element regions 13, the N ⁺ type semiconductor region 1
A channel region 15 is set between 1 and the N ⁺ type semiconductor region 12. On this channel region 15, a gate electrode 17 of a selection transistor composed of a first polycrystalline silicon layer is formed via a gate insulating film 16. A first electrode 19 of a data storage capacitor formed of a second polycrystalline silicon layer is connected to the surface of each N ⁺ type semiconductor region 12 via a contact hole 18. I have. The one electrode 19 is formed so as to extend above the gate electrode 17 via an insulating film in the element region 13 via an insulating film, and a field insulating film adjacent to the element region 13 is formed.
It is formed to extend above the gate electrode 17 of another selection transistor formed on 14. Further, each of the above-mentioned one electrodes 19 is provided via an insulating film 20 made of a silicon oxide film or the like for capacitance of the data storage capacitor.
It is covered with the other electrode 21 of the data storage capacitor constituted by the third polycrystalline silicon layer. The other electrode 21 is formed so as to continuously cover not only the upper surface of the one electrode 19 but also the side surface of the one electrode 19 on the drain region side and the side surface of the gate electrode 17 of the selection transistor on the drain region side. ing. A data line extracting electrode 23 made of a fourth polycrystalline silicon layer is connected to the surface of each N ⁺ type semiconductor region 11 via a contact hole 22. . The end of the electrode 23 is formed to extend above the flat portion of the other electrode 21 of the data storage capacitor via an insulating film, and the one electrode 19 of the capacitor is formed.
Is formed to extend to above. The physical height of the uppermost layer of the data line extraction electrode 23 is formed so that the height of the other electrode 21 of the data storage capacitor is also higher. A data line 25 made of a wiring metal, for example, aluminum is connected to the surface of each data line extracting electrode 23 via a contact hole 24.
These data lines 25 are extended in the horizontal direction so as to be common to the selection transistors adjacent in the horizontal direction in the figure, and the gate electrodes 17 are connected to the data lines 25. , That is, in the vertical direction. Each memory cell having such a configuration has N
^The source region of the selecting MOS transistor having the ⁺ type semiconductor region 11 as a drain region and the N ⁺ type semiconductor region 12 as a source region, as a dielectric between one electrode 19 and the other electrode 21. And a capacitor for data storage with the insulating film 20 interposed therebetween. Therefore, the equivalent circuit of each memory cell is the same as that of FIG. A DRAM using such a memory cell
Then, one electrode 19 of the capacitor and the electrode for taking out the data line
Since 23 and 23 are formed of different layers of polycrystalline silicon, they can be formed in a state where they are overlapped in a plane as shown in the figure, and it is not necessary to separate at least both planes. . Therefore, even if the area of one memory cell is reduced, the area of each of the one electrode 19 of the capacitor and the data line extracting electrode 23 can be made sufficiently large. Since the area of one electrode 19 of the capacitor can be made sufficiently large, the capacitance can be increased without making the thickness of the insulating film 20 between the electrodes extremely small. As a result, high integration can be achieved and the capacitance of each capacitor can be sufficiently increased. For example, when the occupation area of each memory cell is 1.8 μm × 4 μm in a design standard having a minimum dimension of 0.8 μm, the capacitance of the data storage capacitor is sufficiently large as 20 (fF). It was confirmed that. Therefore, a 4M bit DRAM chip can be sufficiently accommodated in a 300 mil package. Further, in the above embodiment, since the area of the electrode 23 for taking out the data line can be made sufficiently large, the opening dimension of the contact hole 24 for connecting to the data line 25 is increased. can do. As a result, the resistance between the drain region of the selection transistor and the data line can be sufficiently reduced. Next, a method of manufacturing a semiconductor device according to the present invention for manufacturing a DRAM having the above configuration will be described with reference to FIGS. Here, FIGS. 2A to 10A are plan views of patterns in each manufacturing process, and FIGS. 2B to 10B are FIGS. 2A to 10A, respectively. FIG. 2 is a sectional view taken along line II ′ of FIG. First, as shown in FIG. 2, a field insulating film 14 is selectively formed on a P-type substrate 10 by a selective oxidation method, and an element region 13 is separated. This field insulating film
Reference numeral 14 denotes a hatched area in FIG. Next, as shown in FIG. 3, an insulating film for forming a gate insulating film is grown on the substrate surface by a thermal oxidation method. Subsequently, a first polycrystalline silicon layer is deposited on the entire surface, and the polycrystalline silicon layer is patterned to form a gate electrode 17 and a gate insulating film 16 sequentially. Here, the gate electrode 17 is a shaded region in FIG. Instead of forming the gate electrode 17 with a polycrystalline silicon layer, a metal silicide layer such as molybdenum silicide, titanium silicide, tungsten silicide, or a refractory metal layer is patterned. You may. Thereafter, an N-type impurity, for example, arsenic (As) is diffused into the substrate 10 by using the gate electrode 17 as a mask.
^{The +} type semiconductor regions 11 and 12 are formed, respectively. Although the gate insulating film 16 is patterned at the same time when the gate electrode 17 is formed, an unnecessary portion may be removed before the N-type diffusion. Next, after an insulating film is deposited on the entire surface as shown in FIG. 4, each of the N ⁺ type semiconductor regions 12 is
The contact hole 18 is opened to the surface of the contact hole. Here, this contact hole 18 is a hatched area in FIG. Next, as shown in FIG. 5, a second polycrystalline silicon layer is deposited on the entire surface, and this polycrystalline silicon layer is patterned to form one electrode 19 of the capacitor. Insulation film as a dielectric for capacitors on the entire surface
20 is deposited to a predetermined thickness. As the insulating film, a silicon oxide film is used as described above, but in addition, a silicon nitride film, a tantalum oxide film, or the like can be used. The thickness of the insulating film 20 is about 10 nm in terms of a silicon oxide film.
About 20 nm if a silicon nitride film is used. An insulating film having such a thickness can be easily deposited by a normal process. Here, the electrode 19 is shown in FIG.
(A) is a shaded area. Next, as shown in FIG. 6, a third polycrystalline silicon layer is deposited on the entire surface, and this polycrystalline silicon layer is patterned to form the other electrode 21 of the capacitor. Here, the electrode 21 is a hatched area in FIG. 6A, and the other electrode 21 is formed so as not to remain on the drain region as shown. Subsequently, as shown in FIG. 7, after a predetermined thickness of an insulating film is deposited on the entire surface, contact holes 22 communicating with the surfaces of the respective N ⁺ -type semiconductor regions 11 are formed by photo-etching.
Open. Here, this contact hole 22 is shown in FIG.
(A) is a shaded area. Next, as shown in FIG. 8, a fourth polycrystalline silicon layer is deposited on the entire surface, and the polycrystalline silicon layer is patterned to form a data line extracting electrode 23. . Here, the electrode 23 is a hatched area in FIG. 8A, and the physical height of the uppermost layer of the data line extracting electrode 23 is higher than that of the other electrode 21 of the capacitor. It is formed to be high. Subsequently, as shown in FIG. 9, after a predetermined thickness of an insulating film is deposited on the entire surface, a contact hole communicating with the surface of the data line extracting electrode 23 is formed by photo-etching.
Open 24. Here, this contact hole 24 is shown in FIG.
(A) is a shaded area. Next, as shown in FIG. 10, a wiring metal, for example, aluminum is deposited on the entire surface, and this aluminum is patterned to form data lines 25. Here, this data line 25 is a shaded area in FIG. Through the above steps, the memory shown in FIG. 1 is manufactured. In addition, in the drawings used for describing these manufacturing steps, the dimensions of each part are not always accurately described. For example, the contact hole 22 in FIG. 7A and the contact hole 24 in FIG.
Are the same, but these are actually
As shown in the cross-sectional view of (b), the dimensions of the contact hole 24 are larger. It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified. For example, in the above embodiment, the data line extracting electrode 23
The periphery of the contact hole 24 for connecting the data electrode 25 to the data line 25 is connected to one electrode 19 and the other electrode 21 of the data storage capacitor.
Is formed in a state where it is present on both of them, but it may be formed in a state where it is present at least on one electrode 19 or the other electrode 21. By opening the contact hole 24 to such a size, the resistance between the drain region of the selection transistor and the data line can be sufficiently reduced. As described above, according to the present invention,
A method for manufacturing a semiconductor memory device that can manufacture a semiconductor memory device that can be highly integrated can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a configuration of a semiconductor memory device manufactured by a method of manufacturing a semiconductor memory device according to the present invention, (a) is a pattern plan view, and (b) is a cross-sectional view. FIGS. 2A and 2B are diagrams for explaining a manufacturing process according to an embodiment of a method of manufacturing a semiconductor memory device according to the present invention, wherein FIG. FIG. 3 is a view for explaining a manufacturing process subsequent to FIG. 2;
(A) is a pattern plan view, (b) is a sectional view. FIG. 4 is a view for explaining a manufacturing process subsequent to FIG. 3;
(A) is a pattern plan view, (b) is a sectional view. FIG. 5 is a view for explaining a manufacturing process subsequent to FIG. 4;
(A) is a pattern plan view, (b) is a sectional view. FIG. 6 is a view for explaining the next manufacturing step of FIG. 5;
(A) is a pattern plan view, (b) is a sectional view. FIG. 7 is a view for explaining the next manufacturing step of FIG. 6;
(A) is a pattern plan view, (b) is a sectional view. FIG. 8 is a view for explaining the next manufacturing process of FIG. 7;
(A) is a pattern plan view, (b) is a sectional view. FIG. 9 is a view for explaining the next manufacturing step of FIG. 8;
(A) is a pattern plan view, (b) is a sectional view. FIG. 10 is a view for explaining the next manufacturing step of FIG. 9;
(A) is a pattern plan view, (b) is a sectional view. FIG. 11 is a circuit diagram showing a configuration of a memory cell used in a dynamic semiconductor memory. FIG. 12 is a cross-sectional view illustrating a configuration of a conventional memory cell. [Description of References] 10 ... P-type silicon semiconductor substrate, 11 ... N ⁺ type semiconductor region (common drain region), 12 ... N ⁺ type semiconductor region (source region), 13 ... Element region, 14 ... Feature Gate insulating film, 15 ... channel region, 16 ... gate insulating film, 17 ... gate electrode, 18 ...
Contact hole, 19: one electrode of capacitor, 20: insulating film, 21: other electrode of capacitor, 22: contact hole
, 23 ... electrode for taking out data wire, 24 ... contact hole
25, data line.

Claims (1)

(57) [Claims] Forming a gate electrode of a selection transistor made of a conductive member of a first layer on a semiconductor substrate of a first conductivity type via a first insulating film; and forming a gate electrode in the substrate by using the gate electrode. Forming a source and drain region of a selection transistor composed of a second conductivity type semiconductor region in a self-aligned manner, and depositing a second insulation film over the entire surface; Forming a first opening communicating with the surface of the source region of the transistor, depositing a second layer of conductive member over the entire surface, and patterning the second layer of the conductive member to form the source; Connected to the surface of the area and partially up
Forming one electrode of a data storage capacitor extending over the gate electrode; and depositing a third insulating film on the entire surface, and then depositing a third-layer conductive member. Patterning a conductive member to extend over the gate electrode;
-On and between one electrode of the storage capacitor
The side surface of the drain region and the gate electrode
The above shape has a shape that continuously covers the side surface on the rain area side.
- forming a second electrode of the data storage capacitor, all
After depositing a fourth insulating film on the surface, the second
Forming a second opening communicating with the surface of the drain region by selectively removing the insulating film and the fourth insulating film, the
After depositing the four layers of conductive members, the conductive parts of this fourth layer
The material is patterned and partially over the fourth insulating film.
So that it overlaps with the other electrode of the data storage capacitor
Method of manufacturing a semiconductor memory device being characterized in that comprising a step of forming a surface with a drain connected extraction electrode of the drain region. 2. 2. The method according to claim 1, wherein a physical height of an uppermost layer of the drain extraction electrode is higher than that of the other electrode of the data storage capacitor.