JP2695785B2 - Processing state display method of processing unit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of displaying an operation state of a processing device which displays whether or not the operation of a processing device controlled by a program is normal in sequence. 2. Description of the Related Art Conventionally, in order to detect an abnormality of a processing apparatus, Japanese Patent Application Laid-Open No. 60-15 / 1985
As described in Japanese Patent Publication No. 3548, an abnormality is automatically detected by using a watchdog timer, and a restart is further performed. Also, Japanese Patent Application Laid-Open No. 60-55448 discloses that a count value of a timer counter is taken into a processing device,
The timer counter is determined to be defective. As a method that does not use the watchdog timer,
As described in JP-A-61-118845, there is a method of turning on and off a lamp at a check point in a program and displaying an operation state of a soft sequence. However, in the former case, if the timer counter is defective, it cannot be detected. This problem is solved by the technique shown by the middle man, but if neither the processing device nor the timer counter is operated from the beginning, no display will be performed, and it will be determined that it is normal despite abnormalities. There is a defect. By the way, it is generally known from the processing result whether or not the sequence operation of the processing device is normal. However, the output position of the processing result is far from the place where the operation sequence operation state is to be grasped, or the output data of the processing result is In the case of constant data, it is not easy to know whether the processing result is output normally or the constant data is output due to an abnormal software loop. It is necessary to easily know whether or not it is operating. As the method, there is a method described in the latter, but in this case, there is a restriction that the program whose operation is to be monitored is divided into two, and each program must be alternately started by a timer. It is an object of the present invention to provide an operating state display method of a processing device that has no such restrictions and easily knows whether or not a processing sequence is operating normally. [Means for Solving the Problems] The object of the present invention is to determine whether or not a program that is inserted during a sequence processing operation and that controls display on and off is periodically executed, and that the display is periodically turned on and off. It is achieved by recognizing whether or not it has been done. The display ON / OFF control program controls the display ON / OFF based on the state of a specific bit which is inverted at a constant cycle and is created by the timer interrupt program. That is, for example, the display-on control program turns on the display only when the state of the specific bit is "1", and the display-off control program turns off the display only when the state of the specific bit is "0". For example, if the processing sequence is normal, the display is turned on and off in synchronization with the state inversion of the specific bit. Display is on,
If it is not turned off, it can be determined that some abnormality has occurred in the display or the processing sequence, but if it is on or off, it can be determined that everything including the processing sequence is normal. . Here, the inversion of the specific bit is created by a timer interrupt program. The timer interrupt program indicates that the cause of the program interrupt is a timer interrupt. The timer interrupt is, for example, a hardware interrupt for performing periodic processing (here, inversion of a specific bit) at a predetermined time interval. This means that a trigger signal having a fixed cycle is generated by an oscillating circuit of a wearer and input to an interrupt line of a processing device for executing a program to generate the interrupt having the fixed cycle. Generally, the time interval is an integer (N) times the fixed period, and the interrupt program counts the number of interrupts every time there is a fixed period interrupt. (Here, the inversion process of the specific bit). This is a general processing content of the timer interrupt processing. DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to FIGS. First, a processing apparatus according to the present invention will be described with reference to FIG. FIG. 2 shows an example of this, showing a schematic configuration. As illustrated, the processing device 1 includes a main program processing unit 4 that processes a main program, which is one of the execution programs, a register 3 that sets the state of a specific bit,
The interrupt processing program, which is one of the execution programs, is interrupted during the execution of the main program, and the register 3
And a timer interrupt processing unit 2 for inverting the state of the specific bit. Since the timer interrupt processing unit 2 (interrupt processing program) has a configuration independent of the main program processing unit 4 (main program), the interrupt processing is interrupted during execution of the main program when an interrupt occurs. The execution is temporarily interrupted, and an interrupt process is inserted into the main program. In general, if an interrupt occurs during the execution of the main program,
The execution of the main program is temporarily interrupted. During this interruption, the interrupt processing program is executed, and when the execution of the interrupt processing program is completed, the execution of the main program is resumed. It has been. The main program processing section 4 determines the state of a specific bit of the register 3 by the display on control program processing and the display off control program processing inserted in the main program, and displays the result via the output buffer 5 according to the result. The display ON / OFF signal is output to the device 6. The display-on control program processing and the display-off control program processing are sequentially executed when the main program is executed. The output on the display 6 is controlled to be turned on and off by this output. in this case,
The state of the specific bit set in the register 3 is inverted by the timer interrupt processing unit 2 at regular intervals, and the cycle is set to be longer than the execution cycle of the main program. Although the function of the timer interrupt processing unit 2 is performed by software, that is, program processing, the timer interrupt processing unit itself may be configured by hardware, that is, by the configuration of the oscillation circuit and the frequency dividing circuit. Obviously, the above-described operation function may be provided. FIG. 1 shows a schematic flow of an example of a main program according to the present invention, and the operation of the above processing device will be described below with reference to FIG. When the execution of the main program starts, first, a necessary initialization process S1 is performed by an initialization program.
After the initial setting process, a first main program process S2 is performed. After the first main program processing S2 is executed, the state of the specific bit described above is determined by the display ON control program processing S3. For example, only when the state is determined to be “1”, the display ON signal is turned ON. Is output to the display 6 and if it is determined to be "0", the second main program processing S4 is immediately executed. After the second main program processing, a display off control program processing S5 is executed. After this execution, the first main program processing S2 is executed again. Thus, the main program is configured such that the first main program processing S2, the display-on control program processing S3, the second main program processing S4, and the display-off control program processing S5 are periodically executed. Here, in the display-off control program processing S5, the display-off signal is output to the display 6 only when the state of the specific bit is “0”.
When the state is determined to be “1”, the first main program processing S2 is immediately executed without performing any processing. Therefore, when the display ON / OFF control program is executed in the main program execution cycle in a state where the inversion cycle of the specific bit is longer than the execution cycle of the main program, the display by the display 6 is synchronized with the inversion cycle of the specific bit. And then turned on and off. However, when the processing sequence of the main program becomes abnormal for some reason, for example, assuming that an abnormal loop occurs in the first main program processing S2, after the occurrence of the abnormal loop, the control program processing of display ON and OFF is no longer performed. Is not performed, and the display 6 maintains the display state before the occurrence of the abnormality. The maintenance of the display state is also caused by the failure of the display 6 itself or the output buffer 5, but in any case, when the display by the display 6 is turned on and off in a predetermined manner, at least the processing sequence normally operates. It can be judged that there is. As described above, according to the present invention, the processing sequence operates normally without depending on the processing result and without having to periodically start the timer of the program whose operation is to be monitored. There is an effect that it is easy to know whether or not there is.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a schematic flow of an example of a main program according to the present invention, and FIG. 2 is a diagram showing a schematic configuration of an example of a processing device according to the present invention. . 1 ... processing device, 2 ... timer interrupt processing unit, 3 ... register, 4 ... main program processing unit, 5 ... output buffer, 6 ... display unit.

Claims (1)

(57) [Claims] A register (3) in which the state of a specific bit is set, and an interrupt processing program which is executed by interrupting the main program, wherein the specific bit of the register is set at regular intervals set to be longer than the main program execution processing cycle. The state of a specific bit of the register is determined by a timer interrupt processing unit (2) for inverting the state, a display on control program processing and a display off control program processing inserted in the main program, and according to the result, A main program processing unit (4) for outputting a display on or display off signal to a display (6), the method comprising: displaying an operation state of a processing device (1); Performing a display-on control program process after executing the first main program process. By determining the state of a particular bit of the register, the outputs a display-on signal to the display unit when a result particular bit state "1" 2
And a third step of executing a second main program process of the main program after executing the display-on control program process; and executing a display-off control program process after the second main program process, The state of the specific bit of the register is determined, and as a result, when the state of the specific bit is “0”, a fourth display output signal is output to the display.
And a method for displaying an operation state of the processing device, the method comprising: