JP2693765B2 - Field effect transistor - Google Patents

Description

TECHNICAL FIELD The present invention relates to field effect transistors. (Prior Art) In recent years, a field effect transistor (hereinafter referred to as FET) using a compound semiconductor material such as GaAs has been actively developed as a high frequency and high output element. FIG. 5 is a sectional view of an example of a conventional field effect transistor. The structure of the FET is IEEE Transaction on Electron Devices (IEEE Transaction
s on Electron Devices) Volume ED-33, 1986, Vol. 11
No. 1818, for conventional high power
This is a typical example of a GaAs FET. The FET is an undoped GaA on the surface of the semi-insulating GaAs substrate 1a.
s buffer layer 8, an n-type GaAs active layer 2n having a donor impurity concentration of 2.5 × 10 ¹⁷ cm ^{−3 on} its surface and a double recess portion 27 provided at the center of the surface, and 1 × on both sides of the surface. A drain electrode 14 and a source electrode 15 are respectively provided on the contact regions 2b of the two n ^{+ -type} GaAs layers having a donor impurity concentration of about 10 ¹⁸ cm ⁻³ and on the contact regions 2b on both sides. The structure of the active layer 2n of this FET is a so-called double recess structure, and the Schottky gate electrode 16 of Al is provided on the bottom of the double recess portion 27. Because of its shape, thickness of the n-type GaAs active layer 2n is thicker between the gate electrode and the drain electrode than beneath the gate electrode 16, and the internal resistance decreases and the impurity concentration N _S is higher Therefore, a high output current I _O can be passed. [Problems to be Solved by the Invention] As an analytical model of the breakdown voltage V _GD between the gate and drain electrodes of a device in a GaAs FET, IEE Transaction on Electron Devices (IEEE T
ransactions on Electron Devices) Volume ED-27, 1980
Year 6, No. 6, page 1013
le) model is well known. Although this model is a relatively simple model, it is generally accepted because it agrees well with the measured value. According to this Wempl's model, the gate-drain electrode voltage V _GD is inversely proportional to the impurity concentration N _S on the surface between the gate and drain. That is, it is necessary to reduce the concentration N _S in order to improve the voltage V _GD . However, when the concentration N _S just below the gate electrode is also reduced at the same time, the output current I _O also decreases. In addition, in order to improve the performance of FETs in general, the gate length Lg
It is extremely important to shorten the gate length Lg, but as the gate length Lg is shortened, the effect of the two-dimensional distribution of the electric field inside the device cannot be ignored, and so-called short channel effects such as increased drain conductance become apparent. The power gain at will be degraded. As a countermeasure, increasing the aspect ratio of the channel (ratio between Lg and the effective channel thickness), increasing the impurities in the channel, and thinning the film, the conventional FET structure
Since the gate electrode and the channel layer are in direct contact with each other, an increase in impurities in the channel causes an increase in leakage current of the gate, resulting in deterioration of device characteristics. The conventional field effect transistor described above has a problem in that the gate length is shortened in order to obtain a high output power, and therefore characteristic deterioration accompanying the short channel effect occurs. It is an object of the present invention to provide a high output field effect transistor which has a high breakdown voltage between the gate and drain electrodes and can obtain a high output current. A field-effect transistor according to a first aspect of the present invention includes an n-type semiconductor layer provided on a high resistance substrate, and a low impurity concentration semiconductor barrier layer having an electron affinity smaller than that of the n-type semiconductor. A drain having a stack of stacked layers, a recess for relaxing the lower electric field strength is provided only on a part of the surface of the semiconductor barrier layer, and a drain provided on the surface of the stack with the recess sandwiched ( A source electrode and a gate electrode. The field effect transistor of the second invention has a p-type semiconductor layer provided on a high resistance substrate and a sum of electron affinity and energy gap larger than a sum of electron affinity and energy gap of the p-type semiconductor. A semiconductor barrier layer having a low impurity concentration, and a stacked body, and a recess for relaxing the electric field strength of the lower portion is provided only on a part of the surface of the semiconductor barrier layer, and the surface of the stacked body is provided. It is characterized by comprising a drain (source) electrode and a gate electrode provided so as to sandwich the recess. (Operation) Hereinafter, the operation of the present invention will be described with reference to the drawings. FIG. 1 is a schematic sectional view of a semiconductor chip for explaining the operation of the present invention. The semiconductor chip has a stack S composed of a high resistance substrate 1, an active layer 2 of one conductivity type and a barrier layer 3 on the substrate, a drain electrode 4 and a source electrode 5 on both sides of the surface, and a gate electrode 6 in the middle. There is. The one-conductivity type active layer 2 has a recess 7 in a part on the surface between the gate and drain electrodes. The barrier layer 3 acts to confine the carriers in the channel of the one conductivity type active layer 2 to the upper side. Immediately below the barrier 3, the spread width of the depletion layer into the one-conductivity type active layer 2 increases, so that the effective carrier concentration,
That is, the effective impurity concentration is reduced and the gate-drain electrode withstand voltage V _GD is improved. In this case, since the carrier concentration and the impurity concentration immediately below the gate electrode 6 do not change, basically, the output current I _O
Can be maintained at a high value and the output power is greatly improved. This effect is due to the gate
This is caused by relaxation of the concentrated region of the electric field on the surface between the drain electrodes. FIG. 2 is a characteristic diagram of electric field strength on the surface of the active layer in FIG. The characteristic curve ln shows the characteristic of the distribution of the electric field intensity on the surface of the active layer 2 between the gate and drain electrodes. The characteristic curve lo is the conventional FE of FIG. 5 shown for comparison.
The electric field strength distribution on the surface of the active layer 2 between the gate and drain electrodes of T is shown. As shown by the curve lo, in the conventional FET, when the gate-drain voltage is applied, at the position X of the electric field strength on the active layer surface,
A strong electric field causes avalanche breakdown. As shown by the curve ln, even if the same gate-drain voltage is applied to the FET of the present invention, the electric field is relaxed to some extent in the active layer 2 immediately below the recess 7, so that the voltage breakdown on the surface of the active layer due to the strong electric field. Does not occur. Here, the film thickness of the barrier layer 3 provided with the concave portion 7 is set to the output current I _O
A high voltage and high output current, that is, a high output power FET can be obtained by selecting a range that does not cause a significant decrease in Embodiment Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a sectional view of an embodiment of the present invention. The semiconductor wafer comprises a semi-insulating GaAs substrate 1a, an undoped GaAs buffer layer 8 having a film thickness of 0.5 μm on the surface thereof, and an impurity concentration of about 1 × 10 ¹⁸ cm ⁻³ and a film thickness of about 30 mm on the surface. -Shaped GaAs active layer 2n and barrier layer of undoped Al _0.5 Ga _0.5 As with an impurity concentration of 1 × 10 ¹⁶ cm ^-3 or less and a film thickness of 50 nm
It is composed of a laminated body Sa in which 3a is stacked. A drain electrode and a source electrode 15 made of an alloy of AuGa and Ni are provided on both sides of the surface of the stacked body Sa, and a gate electrode 16 forming a Schottky junction with the active layer 2n is provided by TiAu in the middle thereof. Further, a recess 17 having a depth of about 15 nm is provided in a part of the surface of the barrier layer 3a between the gate electrode 16 and the drain electrode 14. As the barrier layer 3a above the laminated body Sa, at least an active layer
A semiconductor layer having the same electron affinity as that of the active layer 2n at the interface of 2n, such as undoped GaAs or Al toward the surface side.
Undoped AlxGa with gradually increasing As molar ratio x
_(1-x) As or the like may be used. The withstand voltage V _GD between the gate and drain electrodes of the FET of this example is approximately 25 V,
The output current was extremely good at about 500 mA / mm, and the output in the microwave band was about twice as good as that of the conventional structure FET. FIG. 4 is a sectional view of an embodiment of the second invention. The semiconductor wafer has a semi-insulating GaAs substrate 1a and a film thickness of about 0.5 μm when the impurity concentration on the surface is about 1 × 10 ¹⁵ cm ⁻³ or less.
GaAs buffer layer 8a, and the p-type Ge active layer 2p having an acceptor impurity concentration of about 1 × 10 ¹⁸ cm ^-3 and a film thickness of about 30 nm on its surface.
And an undoped Al _0.1 Ga _0.9 As barrier layer 3b having an impurity concentration of about 1 × 10 ¹⁶ cm ^-3 or less and a film thickness of about 50 nm. Drain and source electrodes made of AuZn are formed on the surface of the laminate 3b.
A gate electrode 26 made of tungsten that forms a Schottky junction with 24, 25 and the barrier layer 3b is provided. A recess 17b having a depth of 20 nm is provided between the gate / drain electrodes 26, 24 on the surface of the stacked body 3b. The effects of this embodiment are similar to those of the first embodiment of the invention. (Effects of the Invention) As described above, according to the present invention, the short channel effect can be suppressed and the high breakdown voltage can be improved by providing the concave portion in a part of the surface between the gate and drain electrodes of the laminated body of the upper layer of the semiconductor wafer. There is an effect that it is possible to realize a field effect transistor excellent in high-frequency and high-output property of output current.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a semiconductor chip for explaining the operation of the present invention, FIG. 2 is an electric field strength characteristic diagram of the surface of the laminate of FIG. 1, and FIG. 4 is a sectional view for explaining an embodiment of the invention of FIG. 4, FIG. 4 is a sectional view for explaining an embodiment of the second invention, and FIG. 5 is a sectional view for explaining a conventional field effect transistor. Is. 1 ... High resistance substrate, 1a ... semi-insulating GaAs substrate, 2 ... one conductivity type active layer, 2n ... n type GaAs active layer, 2p ... p type Ge active layer, 3,3a, 3b ... Barrier layer, 4,14,24 …… Drain electrode, 5,15,25 …… Source electrode, 6,16,26 …… Gate electrode,
7,17,17a, 17b ... Concave, S, Sa, Sb ... Laminate.

Claims (1)

(57) [Claims] An n-type semiconductor layer provided on a high resistance substrate,
A semiconductor layer having a low impurity concentration that has an electron affinity smaller than that of the semiconductor layer, and a layered structure in which a semiconductor layer having a low impurity concentration is stacked, and the electric field strength of a lower portion is relaxed only on part of the surface of the semiconductor barrier layer. And a drain (source) electrode and a gate electrode provided on the surface of the laminated body with the recess interposed therebetween. 2. A p-type semiconductor layer provided on a high resistance substrate,
Type semiconductor having a stack of a semiconductor barrier layer having a low impurity concentration having a sum of electron affinity and energy gap larger than the sum of electron affinity and energy gap, and only a part of the surface of the semiconductor barrier layer A field effect transistor, characterized in that a lower part is provided with a concave part for relaxing the electric field strength, and a drain (source) electrode and a gate electrode provided on the surface of the laminate with the concave part interposed therebetween.