JP2689915B2 - Time division multiplex bus initialization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of slave cards each having a signal transmitting / receiving means and having different logical formats of signals to be transmitted / received, and one slave card having a signal transmitting / receiving means called a bus master. The present invention relates to an initialization circuit of a time division multiplex bus for performing time division multiplex communication with a master card.

[0002]

2. Description of the Related Art A bus master which performs time division multiplex communication with a plurality of slave cards each having a different signal logical format is supposed to recognize the logical format of each slave card. Therefore, conventionally, the logical format of each slave card is recognized by the following method. That is, the first method uses a signal line different from that of the time division multiplex bus to recognize the type of each slave card of the communication partner, and to provide a transmission / reception circuit so that signals can be transmitted / received in a logical format according to the recognition result. It is a method of switching. In the second method, the ID information of each slave card is fixedly assigned to the bus signal on the time division multiplexing bus, and the ID information assigned is recognized and the signal is transmitted / received according to the logical format. This is a method of switching circuits and the like.

[0003]

The first conventional method is as follows.
Since a special interface for recognizing the type of each card is required, there is a drawback that the interface of the bus master and each slave card becomes complicated. Further, in the second method, since the area for the type information is fixedly secured in the bus signal, the information amount of the bus signal is substantially reduced. Therefore, the amount of information in the bus signal must be increased. Therefore, you have to increase the bus clock or increase the number of buses.
There is a drawback that the bus speed is increased and the interface is complicated.

Therefore, an object of the present invention is to communicate with each slave card having a different logical format without increasing the speed of the time division multiplexed bus and without complicating the interface.

[0005]

In order to solve such a problem, the present invention provides a plurality of slave cards having data transmitting / receiving means and different logical formats of transmitted / received data, and a plurality of slave cards from each slave card. A data reception means for receiving data and a bus master having a plurality of data conversion means for converting transmission data according to each logical format are connected to a time division multiplex bus, and a plurality of bus masters and a plurality of bus masters are connected via the time division multiplex bus. in a data transmission system and a slave card to perform data transmission, when
Performs a self-reset when connected to a split / multiplex bus
Means and the time-division multiplexed bus time given by the bus master after generating the identification signal after completion of this self-reset.
The slave card is provided with an identification signal generating means for transmitting the identification signal to the slot a fixed number of times and a receiving means for receiving the identification signal recognition information (start pattern) returned in response to the transmission of the identification signal. The bus master is provided with detecting means for detecting, transmitting means for transmitting the identification signal recognition information, and selecting means for selecting the data converting means according to the received identification signal.

[0006]

When the slave card is connected to the time division multiplex bus, it transmits an identification signal to the bus master, and the bus master receives the identification signal to initialize the time division multiplex bus and recognize the identification signal to the slave card. While transmitting the information, the data converting means corresponding to the identification signal is selected from among the data converting means for converting the data into the respective logical formats, and the data transmission with the slave card is started.
As a result, it is possible to communicate with each slave card having a different logical format without increasing the speed of the time division multiplexed bus and without complicating the interface. Further, the slave card sends an identification signal a fixed number of times to the time slot of the time division multiplex bus given from the bus master. As a result, the bus master side can reliably recognize the identification signal of the slave card.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.
In the figure, 1 is called a bus master and is mounted on a master card. Time-division multiplexed buses 2 and 3 are connected to the bus master 1, and a plurality of slave cards 41, 42, ... Are connected to the time-division multiplexed buses 2 and 3. Each slave card has a different signal format for transmission and reception.

Here, the bus master 1 receives a signal transmitted from each slave card, a receiving circuit 11, an identification signal detecting circuit 12 for detecting an identification signal (ID information) from each slave card, and the above identification signal. A start pattern generation circuit 13 for generating a start pattern indicating the recognition of the identification signal when it is detected and transmitting it to the slave card. The transmission signal to each slave card is converted and output so as to match the logical format of each slave card. It is composed of data format conversion circuits 141 to 14n and changeover switches SW1 and SW2.

On the other hand, each slave card 4 generates an identification signal unique to each card and sends it to the bus master 1, an identification signal generation circuit 41, and a main signal transmission circuit 42 that sends a signal (main signal) to the bus master 1. , A start pattern receiving circuit 4 for receiving a start pattern from the bus master 1
3, a main signal receiving circuit 44 for receiving a main signal from the bus master, and a changeover switch SW3.

By the way, in the bus master 1, when the main signal is communicated with each slave card, the logical format of the main signal is different in each slave card.
First you need to recognize this format. Therefore, in this embodiment, when the slave card is connected to the buses 2 and 3 and the power is turned on, the changeover switch SW3 is switched to the identification signal generating circuit 41 side, and the identification signal generating circuit 4 is switched.
Bus master 1 via bus 3 from its own identification signal
Send to In the bus master 1, the identification signal is received by the reception circuit 11, and further detected by the identification signal detection circuit 12.

Then, the bus master 1 returns the start pattern from the start pattern generation circuit 13 to the corresponding slave card via the bus 2. When the transmission of the start pattern to the slave card is completed, the changeover switch SW1 is switched from the start pattern generation circuit 13 side to the data format conversion circuit 14 side. On the other hand, when the corresponding slave card receives the start pattern, the changeover switch SW3 is switched from the identification signal generating circuit 41 side to the main signal transmitting circuit 42 side, and as a result, the slave card and the bus master 1 communicate with each other in the normal main signal. Start operation. Then, when the bus master 1 transmits the main signal to the corresponding slave card, the changeover switch S
W2 is switched to select the data format conversion circuit corresponding to the above-mentioned identification signal to convert the main signal into a corresponding logical format for transmission.

FIG. 2 is a timing chart showing a series of operations of the bus master 1 and the corresponding slave card 4 when the slave card 4 is connected to the buses 2 and 3, and FIG. 3 is a flowchart thereof. The operation of the main part of the present invention will be described in more detail with reference to FIGS. 2 (b) and 2 (c)
Indicates the transmission / reception timings of the buses 2 and 3, respectively, and the slave card 4 corresponding to the slave n of the time slot.
n has been removed from the bus, indicating that this slot is empty. Note that FIG. 2A shows the transmission timing of the bus master 1 for the corresponding time slot, and the bus master has been turned on and is operating.

In such a situation, the slave card 4
When n is connected to buses 2 and 3 and installed in the system,
The slave card 4n operates as follows. That is, FIG.
When the power is turned on in (a), self reset for resetting itself is performed in step S1, and when the reset is released, then in step S2, the bus 2, 3
Recognize the time slot assigned to itself above.
Next, in the recognized transmission time slot (corresponding to the reception time slot in the bus master) on the bus 3 shown in FIG. Identification signal (I
D) is transmitted. This identification signal is transmitted a certain number of times, and as a result, the type of slave card is recognized on the bus master 1 side.

That is, the bus master 1 determines whether or not the identification signal from the slave card 4n is received in step S11 of FIG. 3B. When the identification signal is received from the slave card 4n, the identification is performed in step S12. Recognize the card type from the signal. When the card type is recognized and it is determined to be "Y" in step S13, the bus master 1
Is an initialization process of the bus transmission in step S14 (that is, a process of initializing a portion related to the transmission format information of the slave card which is stored in a memory (not shown) of the bus itself and matches the logical format according to the type of the slave card) After that, the start pattern generation circuit 13 is started in step S15 for the transmission time slot corresponding to the slave card 4n of the transmission bus 2 which is in the empty state.
To send the start pattern from.

As a result, a start pattern as shown in FIG. 2 (f) is output from the transmission time slot (corresponding to the reception time slot in the slave card) corresponding to the slave card 4n of the bus 2. After that, the bus master 1 switches the changeover switch SW1 to the data format conversion circuit 14 side and switches the switch SW2 to select the data format conversion circuit according to the card type to prepare for communication with the corresponding slave card. At the same time, in step S16, the main signal communication with the corresponding slave card is performed.

On the other hand, in the corresponding slave card 4n,
After transmitting the above-mentioned identification signal, it is judged in step S4 whether or not the start pattern is received through the reception time slot of itself on the bus 2, and when the start pattern transmitted from the bus master 1 is received, Step S
At 5, the changeover switch SW3 is switched to the main signal transmitting circuit 42 side, and the main signal communication with the bus master 1 is started. 2 (h) and 2 (i) show the communication states of the corresponding time slots on the buses 2 and 3. In this way, when the bus master and a plurality of slave cards having different logical formats are connected on the same bus for communication, the bus master 1 and the card 4 can be used without increasing the signal speed of the bus.
Communication can be performed without changing the interface between them and further without increasing the number of signal lines.

[0017]

As described above, according to the present invention, the slave card transmits its own identification signal to the bus master when connected to the time division multiplex bus, while the bus master receives the identification signal. The slave is selected by initializing the time division multiplex bus, transmitting identification signal recognition information to the slave card, and selecting the data conversion means corresponding to the identification signal among the respective data conversion means for converting the data into each logical format. Since the data transmission with the card is started, it is possible to communicate with each slave card having a different logical format without increasing the speed of the time division multiplex bus and complicating the interface. Further, since the slave card sends the identification signal to the time slot of the time division multiplexed bus given from the bus master a fixed number of times, the identification signal of the slave card can be surely recognized on the bus master side.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the system of the above embodiment.

FIG. 3 is a flowchart showing the operation of the system of the above embodiment.

[Explanation of symbols]

1 ... Bus master, 2, 3 ... Time division multiplexed bus, 41, 4
2 ... Slave card, 11 ... Reception circuit, 12 ... Identification signal detection circuit, 13 ... Start pattern generation circuit, 141-
14n ... Data format conversion circuit, 41 ... Identification signal generation circuit, 42 ... Main signal transmission circuit, 43 ... Start pattern reception circuit, 44 ... Main signal reception circuit, SW1 to SW3
… Changeover switch.

Claims (1)

(57) [Claims] 1. A plurality of slave cards having data transmission / reception means and different logical formats of data to be transmitted / received, data reception means for receiving data from each slave card, and transmission data according to the respective logical formats. connecting the bus master time division multiplexed bus having a plurality of data conversion means for converting Te, in the bus master and data transmission system in which a plurality of slave cards perform data transmission through the time division multiplex bus, wherein Self reset when connected to time division multiplexed bus
Means for performing the self-resetting, and after the self-reset is completed, an identification signal is generated and the time-division multiplexing bar provided from the bus master.
The slave card is provided with an identification signal generating means for transmitting the identification signal for a certain number of times to the slave time slot, and a receiving means for receiving the identification signal recognition information returned in response to the transmission of the identification signal. Is provided in the bus master, and the slave card is connected to the time division multiplex bus, the detecting means for detecting the signal, the transmitting means for transmitting the identification signal recognition information, and the selecting means for selecting the data converting means according to the received identification signal. When receiving the identification signal, the bus master initializes the time division multiplex bus by receiving the identification signal and transmits identification signal recognition information to the slave card to start data transmission. A time division multiplex bus initialization circuit characterized by the above.