JP2689125B2 - LSI test equipment - Google Patents

Description

DETAILED DESCRIPTION [Overview] The present invention relates to a device for testing an LSI, and sets a timing of an input signal to a device under test for the purpose of reducing skew between channels in a multi-channel LSI test device. Timing adjusting means, a driver that adjusts the waveform and level of the input signal to the LSI under test, a comparator that identifies the level using the output signal from the LSI under test as an input, and generates an output signal, the comparator Timing adjusting means for setting the timing of the strobe signal for specifying the timing of the identification signal of the driver, and the output of the driver and the input of the comparator are connected to the input / output pin of the LSI under test to connect the input / output pin and the driver. A changeover switch for switching the connection between the output and the input / output pin and the input of the comparator It has multiple channels corresponding to each input / output pin of the LSI under test, and when adjusting the skew of the LSI tester, disconnect the output of the driver and the input of the comparator from the changeover switch and connect them to each other to connect to the measurement electrodes. With a changeover switch for each channel, a standard measurement system for measuring the timing of the signal waveform by arbitrarily selecting each measurement electrode, the timing of each channel based on the timing measurement result in the standard measurement system In the LSI test apparatus for making the timing offset value of the output signal in the driver of all channels and the timing offset value of the timing measurement in the comparator the same by performing the timing setting in the adjusting means, the standard measurement system applies to each measurement electrode. Each contacted electro-optic crystal A voltage state of the measurement electrode is detected by detecting birefringence induced in the electro-optic crystal by irradiating the electro-optic crystal with laser light from a side opposite to the measurement electrode; It has a configuration as an LSI test apparatus, characterized in that the optical path length of a laser beam for irradiating a laser beam is configured to be the same for each measurement electrode.

[Industrial applications]

The present invention relates to a device for testing an LSI, and more particularly to an LSI test device having a large number of drivers and comparators, in which the skew between the driver and the comparator is reduced.
It relates to a test device.

[Conventional technology]

The LSI test equipment is required to have a large number of measurement pins as the LSI is highly integrated. In addition, with the speedup of LSI,
It is necessary to have higher accuracy, especially to reduce the skew between the driver and the comparator.

In the LSI test equipment, it is required to satisfy both the demand for the high pin count and the demand for the high precision.

FIG. 6 shows the structure of a test channel in a conventional LSI test apparatus. In Fig. 6, the test
Only the configuration of 1 channel corresponding to 1 pin under test of the LSI (DUT) is shown. That is, when the input / output pin of the LSI under test and the output of the driver are connected, the changeover switch 1 is changed over to the c side. The test clock is input from the test pin 1A through the timing adjustment circuit 2 and the driver 3 to the LSI under test (DUT) through the pin under test. Further, when the input / output pin of the LSI under test and the input of the comparator are connected, the changeover switch 1 is changed over to the d side.
The output signal of the LSI under test (DUT) is applied from the pin under test to the comparator 4 via the test pin 1A, and it is discriminated whether the voltage level at a certain timing is higher than the reference voltage or not to generate an output.

Driver 3 in the test channel shown in FIG.
When adjusting the timing on the side, a separately prepared standard comparator with adjusted timing is used.
That is, with the output of the driver 3 connected to the input of the standard comparator, the delay time is adjusted in the timing adjustment circuit 2 including a delay circuit or the like so that the clock standard comparator detects the delay time at a predetermined timing.

When adjusting the timing on the side of the comparator 4, a separately prepared standard driver with adjusted timing is used. That is, with the output of the standard driver connected to the input of the comparator 4, a delay time is set in the timing adjusting circuit 5 including a delay circuit and the strobe signal is given to the comparator 4. The strobe signal is a timing signal for performing the comparison. Therefore, the timing at which the input signal to the comparator 4 changes is measured by changing the timing of the strobe signal. The delay time of the timing adjustment circuit 5 is adjusted so that the measured value for the input signal that changes at a predetermined timing by the standard driver matches the reference value.

This adjustment is performed for each of the timing adjustment circuits 2 and 5, and when completed, the test pin 1A is connected to the LSI under test.
By connecting to the DUT pin under test, the L under test
When the input / output pin of SI and the output of driver 3 are connected,
A test input at a predetermined timing is given to the LSI under test (D
UT) to the required test conditions. Also tested
When the input / output pin of the LSI and the input of the comparator 4 are connected, the quality of the output timing of the LSI under test (DUT) can be known by the output of the comparator.

An actual LSI test apparatus has, for example, several hundreds of such channels corresponding to the increase in the number of pins of LSI.

Conventional LSI having the test channel shown in FIG.
In the test equipment, when the number of test channels becomes very large, even if the high-accuracy standard measurement system shown in FIG. It is impossible to do.

That is, when the number of test channels becomes very large, setting the same operation timing for the driver 3 and the comparator 4 of each channel causes variations in the electrical length of the wiring to the standard driver and the standard comparator or variations in adjustment. Difficult on the basis. For example, in the case of a multi-pin LSI tester with about 500 pins, it was difficult to keep the timing accuracy for all pins within ± several hundreds ps.

[Problems to be solved by the invention]

The present invention is intended to solve the above-mentioned problems of the prior art, and an LSI having a large number of test channels is provided.
It is an object of the present invention to provide an LSI test device that can perform timing adjustment for a driver and a comparator of each channel under the same conditions and with high accuracy.

[Means for solving the problem]

The configuration of the present invention is as described below. That is, under test
Timing adjusting means (2) for setting the timing of the input signal to the LSI, a driver (3) for adjusting the waveform and level of the input signal to the LSI under test, and a level using the output signal from the LSI under test as an input. A comparator (4) for identifying an output signal and generating an output signal; a timing adjusting means (5) for setting a timing of a strobe signal defining a timing of the identification signal of the comparator; and an input / output pin of the LSI under test. The driver (3)
And the input of the comparator (4) are connected, and the connection between the input / output pin and the output of the driver (3),
The changeover switch (1) for switching the connection between the input / output pin and the input of the comparator (4) is provided for a plurality of channels corresponding to each input / output pin of the LSI under test. Each channel is provided with a changeover switch (6) for disconnecting the output of (3) and the input of the comparator (4) from the changeover switch (1) and connecting them to the measurement electrode (7). A standard measurement system (8) for arbitrarily selecting each of the measurement electrodes (7) to measure the timing of the signal waveform is provided, and the timing adjustment means (for each channel) based on the timing measurement result in the standard measurement system (8). 2),
An LSI that equalizes the timing offset value of the output signal in the driver (3) of all channels with the timing offset value of the timing measurement in the comparator (4) by performing the timing setting in (5).
In the test apparatus, the standard measurement system (8) includes an electro-optic crystal in contact with each measurement electrode (7), and the electro-optic crystal is irradiated with laser light from a side opposite to the measurement electrode (7). The voltage state of the measurement electrode (7) is detected by detecting the birefringence induced in the electro-optic crystal by the optical path length of the laser beam irradiating the electro-optic crystal. ) Is configured to be the same as the above.

The changeover switch 6 is used when adjusting the skew of the LSI test equipment.
The output of the driver 3 and the input of the comparator 4 are separated from the changeover switch 1 and connected to each other to connect the measurement electrode 7
Is to be connected to.

Further, the standard measurement system 8 arbitrarily selects each measurement electrode 7 and measures the timing of its signal waveform with high accuracy.

[Action]

The changeover switch 1 is provided for a plurality of pins under test of the LSI under test, the timing of the input signal to the LSI under test is adjusted through the timing adjusting means 2, and the waveform and level of the input signal to the input / output pin are adjusted. Is adjusted via the driver 3 and connected to the input / output pin of the LSI under test, and the voltage level at the timing defined by the strobe signal of the output signal from the input / output pin of the LSI under test is identified via the comparator 4. An LSI that generates an output signal and adjusts the timing of the strobe signal via the timing adjusting means 5.
In the test apparatus, in order to adjust the skew between the driver 3 and the comparator 4 between the channels of this LSI test apparatus, a changeover switch 6 is provided for each channel, and the output of the driver 3 and the input of the comparator 4 are changed over. The measuring electrodes 7 are separated from each other and are connected to each other and connected to the measuring electrodes 7, and each measuring electrode 7 is arbitrarily selected by the standard measuring system 8 to measure the timing of its signal waveform with high accuracy. Then, based on the timing measurement result in the standard measurement system 8, the timing adjusting means 2, 5 for each channel
Since the timing setting in (1) is performed, the timing offset value of the output signal in the driver 3 of all channels and the timing offset value of the timing measurement in the comparator 4 can be made the same.

〔Example〕

FIG. 1 shows the configuration of each test channel of an LSI test apparatus according to an embodiment of the present invention, and the same components as those in FIG. 6 are designated by the same reference numerals. 6 is a changeover switch and 7 is a measuring electrode.

When the LSI under test (DUT) is tested, the a side is selected as the change-over switch 6, and in this state, the configuration is the same as that of the conventional LSI test apparatus and the same operation as that of the conventional LSI test apparatus is possible.

On the other hand, the b switch side is selected as the changeover switch 6 when adjusting the timing of the LSI test apparatus. In this case, the driver 3 and the comparator 4 are not connected to the LSI under test (DUT), the output of the driver 3 is connected to the input of the comparator 4 and the measurement electrode 7, and the output of the driver 3 when the clock is input. With the standard measurement system connected to the measurement electrode 7, the timing can be measured with high accuracy.

FIG. 2 shows the overall configuration of an LSI test apparatus according to an embodiment of the present invention, and only the configuration corresponding to the two channels indicated by suffixes 1 and 2 is shown. Each subscripted numbered component is equivalent to a non-subscripted numbered component in FIG. It is assumed that the measurement electrodes 7 ₁ and 7 ₂ are respectively integrated with a measurement unit made of an EO (electro-optic) crystal or the like. Reference numeral 8 is a standard measurement system, which has the same structure as that described in FIG. 9 is the LSI under test (D
UT), the pin under test i is connected to the test pin 1A ₁ and the pin under test j is connected to the test pin 1A ₂ .

When testing the LSI under test (DUT) 9, each changeover switch 6 ₁ , 6
₂ is selected on the a side and the driver is connected to the input / output pin of the LSI under test.
C or d is selected for the changeover switches 1 ₁ and 1 ₂ depending on whether the outputs of 3 ₁ and 3 ₂ are connected or the inputs of the comparators 4 ₁ and 4 ₂ are rejected. The same applies to each changeover switch connected to all other pins under test of the LSI under test (DUT) 9 not shown.

In this state, similarly to the conventional LSI test apparatus, the LSI under test is passed through the drivers 3 ₁ and 3 ₂ at the timing determined by the clock setting timing and the adjustment of the timing adjusting circuits 2 ₁ and 2 _2.
A test clock can be input to the (DUT). Also, strobe setting timing and timing adjustment circuit
Comparator 4 at the timing determined by the adjustment of 5 ₁ , 5 _2.
1, 4 by performing the identification in _2, it is possible to determine the path and fail output of the test LSI (DUT). In this case, input can be given to the LSI under test (DUT) at any timing by externally changing the clock setting timing, or the output of the comparators 4 ₁ and 4 ₂ can be changed while changing the strobe setting timing. The output timing of the LSI under test (DUT) can be measured by checking the presence or absence.

When the timing of the LSI tester is adjusted, the changeover switches 6 ₁ and 6 ₂ are selected on the b side, and the outputs of the drivers 3 ₁ and 3 ₂ are output from the comparators 4 ₁ and 4 ₂ to the measurement electrodes 7 ₁ and 7 _{2 respectively.} Connected to. In this state, the timing adjusting circuit scans the measuring section including the measuring electrodes 7 ₁ and 7 ₂ with the laser beam in the standard measuring system 8 to perform the timing measurement with high accuracy.
The output timing of the drivers 3 ₁ and 3 ₂ can be adjusted by setting the settings of 2 ₁ and 2 ₂ . The Enter this manner the driver 3 ₁ are timing adjustment, 3 ₂ outputs to the comparator 4 _1, 4 _2, by measuring the timing with comparator 4 _1, 4 _2, the timing adjustment circuit 5 ₁ , 5 ₂ can be adjusted.

In the configuration shown in FIG. 2, in order to make the timing setting conditions for each channel the same, the drivers 3 ₁ , 3
Branching position for ₂ and comparator 4 _1, 4 ₂ connects the line electrical length and the measuring electrode has to be the same exact for all pins. In addition, it is desirable that the line length between the branch point and the measurement electrode be as short as possible.

FIG. 4 is a diagram showing a configuration of a standard measurement system using a non-contact probe in the LSI test apparatus of the present invention in FIG. In FIG. 3, reference numeral 11 denotes a measurement electrode that is brought into contact with the pin to be measured, which is integrated with the electro-optic (EO) crystal 12 and the transparent electrode 13 to form the measurement portion 10.

Reference numeral 14 is a high-precision delay circuit, which performs timing adjustment for delaying the input clock by a required time based on the delay data. A driver 15 drives a laser diode (LD) 16 according to an input clock whose timing is adjusted, and the laser diode (LD) 16 emits light by this. The light from the laser diode (LD) 16 is a beam splitter
It becomes linearly polarized light through 17 and is converted into circularly polarized light through a 1/4 wavelength (λ / 4) plate 18 and is incident on the measurement unit 10 through a polarization means 19 such as a mirror.

At this time, if a voltage is applied between the measurement electrode 11 and the grounded transparent electrode 13, the electro-optic (EO) crystal 12 has birefringence. Therefore, when a laser is incident on the measurement unit 10, reflected light is generated in the electro-optic (EO) crystal 12. This reflected light passes through the transparent electrode 13 and the polarization means 19 and has a quarter wavelength (λ /
4) It enters the plate 18 and is converted into elliptically polarized light. The output light is reflected by the boundary surface inside the beam splitter 17, changes its direction by 90 °, enters the photodiode 20, and is converted into an electric signal.
After being amplified through an amplifier 21, it is converted into a digital signal of a predetermined number of bits in an analog-digital converter (ADC) 22 to generate output data.

At this time, the timing of the laser light that irradiates the measurement unit 10 is changed using the high-precision delay circuit 14 according to the delay data, and the fixed delayed clock is applied to the analog-digital converter (ADC) 22 as a strobe signal. When the analog-to-digital conversion operation is performed by the analog-to-digital conversion operation, the voltage waveform of the input signal at the pin to be measured in contact with the measurement electrode 11 can be obtained by the output of the analog-to-digital converter (ADC) 22. Timing of the signal can be measured by detecting the point where the upper voltage and the reference voltage match. For the standard measurement system using such a non-contact probe, see
62-183852 (JP-A-64-28566, JP-B-7-99376).

FIG. 4 illustrates the relationship between the generation of output data and the delay data in the LSI test apparatus of the present invention, in which the timing at which the output data (voltage) matches a certain threshold value is obtained.

As described above, in the standard measurement system shown in FIG. 3, without using a measurement cable without contacting the pin under test,
Since the timing of the signal at the pin under test can be measured, highly accurate timing measurement can be performed without being affected by the transmission impedance of the measurement cable or the capacitance of the measurement terminal portion.

In this case, a large number of measuring units 10 are provided corresponding to the input / output pins of the LSI under test (DUT), and each measuring unit is provided via the deflection means 19.
The above-described measurement can be performed on each input / output pin while scanning 10 with a laser beam.

Further, in the standard measurement system for measuring the timing of the signal waveform at each measurement electrode 11, in order to make the optical path length of the laser beam to all the measurement electrodes 11 the same, the measurement electrode 11 is the inner wall of the cylindrical casing in the LSI test apparatus. Placed on the circumference of
The central axis is made to coincide with the rotation axis of the deflecting means 19. The control of the laser pulse irradiation timing for sampling the voltage waveform on the measurement electrode 11 is performed by delaying the clock with high precision by the high precision delay circuit 14 as described above. FIG. 5 is a flow chart showing a procedure for timing adjustment in each driver and comparator by the LSI test apparatus of the present invention.

First, the changeover switch SW1 of all pins (FIG. 1, the changeover switch 6, 6 ₁ in Fig. 2, 6 ₂₎ of the b-side, the pulse generation timing of the entire pin driver (3, 3 _1, 3 ₂₎ Set to the same reference value (step S1). Irradiate the measurement electrodes (7, 7 ₁ , 7 ₂ ) of each pin with a laser pulse (step S2),
The waveform timing is measured with high accuracy by the standard measurement system 8 (step S3). The measured value Ts at this time is the driver (3,3 ₁ ,
3 ₂ ) timing set value and the constant offset value corresponding to the electrical length between the driver (3, 3 ₁ , 3 ₂ ) and the measuring electrode (7, 7 ₁ , 7 ₂ ) until the sum of the driver (3 , 3 ₁ , 3 ₂ ) timing adjustment circuit (2,2 ₁ , 2 ₂ ) driver (3,3 ₁ , 3 ₂ )
Adjust the clock timing of (step S4, S
Five).

Next, the edge timing of the driver output is measured by the comparator (4,4 ₁ , 4 ₂ ) (step S6), and the measured value Tc at this time is the standard measurement system 8 for the driver (3, 3 ₁ , 3 ₂ ). Until the sum of the measured value Ts obtained in step 3 and the constant offset value corresponding to the electrical length between the measuring electrodes (7,7 ₁ , 7 ₂ ) and the comparators (4, 4 ₁ , 4 ₂ ) is reached. The strobe timing of the comparators (4, 4 ₁ , 4 ₂ ) is adjusted by the timing adjustment circuit (5, 5 ₁ , 5 ₂ ) on the (4, 4 ₁ , 4 ₂ ) side (S7, S8).

By performing the above operation for all pins, the driver (3, 3 ₁ , 3 ₂ ) and comparator (4, 4) between each pin are
The skew of ₁ , 4 ₂ ) is reduced. Further, when the temperature change more than the allowable value is detected and the above adjustment is performed, the skew due to the temperature change can be reduced.

In this way, when the timing adjustment is completed, the changeover switches SW1 for all pins are set to the a side, and the timings of the drivers (3, 3 ₁ , 3 ₂ ) for each pin are returned to the original set values and the LSI under test is reset. (DUT) test ready.

〔The invention's effect〕

As described above, according to the LSI test apparatus of the present invention, in the LSI test apparatus including the driver and the comparator of many channels, the skew of the driver and the comparator between the channels is reduced, and the LSI test apparatus is highly accurate.
You will be able to test LSI.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a test channel in an LSI test apparatus as an embodiment of the present invention, FIG. 2 is a diagram showing an overall configuration of an LSI test apparatus as an embodiment of the present invention, and FIG. FIG. 5 is a diagram showing a configuration of a standard measurement system using a non-contact probe in the LSI test apparatus of the present invention. FIG. 4 is a diagram showing a relationship between output data generation and delay data in the LSI test apparatus of the present invention. FIG. 6 is a flow chart showing the procedure when timing adjustment is performed in each driver and comparator by the LSI test apparatus of the present invention, and FIG. 6 is a diagram showing the configuration of test channels in the conventional LSI test apparatus. 1,1 ₁ , 1 ₂ , 6,6 ₁ , 6 ₂ ...... Selection switch 1A, 1A ₁ , 1A ₂ ...... Test pin 2,2 ₁ , 2 ₂ , 5,5 ₁ , 5 ₂ ...... Timing adjustment circuit 3,3 ₁ , 3 ₂ …… Driver 4,4 ₁ , 4 ₂ …… Comparator 7,7 ₁ , 7 ₂ , 11 …… Measurement electrode 8 …… Standard measurement system 9 …… LSI under test (DUT) 10… … Measuring part 10A …… Performance board 12 …… Electro-optic (EO) crystal 13 …… Transparent electrode 14 …… High-precision delay circuit 15 …… Driver 16 …… Laser diode (LD) 17 …… Beam splitter 18 …… 1 / 4 wavelength (λ / 4) plate 19 ...... Deflection means 20 ...... Photo diode 21 ...... Amplifier 22 ...... Analog-to-digital converter (ADC)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshihiro Ishizuka 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Soichi 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 56) References JP-A 61-286768 (JP, A) JP-A 58-201121 (JP, A) JP-A 60-253878 (JP, A)

Claims (1)

(57) [Claims] 1. A timing adjusting means for setting a timing of an input signal to an LSI under test, a driver for adjusting a waveform and a level of an input signal to the LSI under test, and an output signal from the LSI under test as an input. A comparator that identifies the level and generates an output signal, a timing adjusting unit that sets the timing of the strobe signal that defines the timing of the identification signal of the comparator, and the output of the driver and the input and output pins of the LSI under test. Corresponding to each input / output pin of the LSI under test, a switch that connects the input of the comparator and switches the connection between the input / output pin and the output of the driver and the connection between the input / output pin and the input of the comparator is provided. With multiple channels, the output of the driver and the input of the comparator are adjusted during skew adjustment of the LSI test equipment. Each switch is provided with a changeover switch which is separated from the changeover switch and is connected to each other and connected to the measurement electrodes, and a standard measurement system for arbitrarily selecting each of the measurement electrodes to measure the timing of the signal waveform is provided. By setting the timing in the timing adjusting means of each channel based on the timing measurement result in the standard measurement system, the timing offset value of the output signal in the driver of all channels and the timing offset value in the timing measurement in the comparator are made the same. In an LSI test apparatus, the standard measurement system includes electro-optic crystals that are in contact with the respective measurement electrodes, and the electro-optic crystals are induced in the electro-optic crystal by irradiating a laser beam from the side opposite to the measurement electrodes. By detecting the birefringence Detecting the voltage state of the measurement electrodes Te, the optical path length of the laser beam for irradiating the electro-optical crystal, LSI test apparatus characterized by being configured to be the same for each measurement electrode.