JP2684381B2 - Plasma gas phase reaction method - Google Patents
Plasma gas phase reaction methodInfo
- Publication number
- JP2684381B2 JP2684381B2 JP63127577A JP12757788A JP2684381B2 JP 2684381 B2 JP2684381 B2 JP 2684381B2 JP 63127577 A JP63127577 A JP 63127577A JP 12757788 A JP12757788 A JP 12757788A JP 2684381 B2 JP2684381 B2 JP 2684381B2
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- substrate
- film
- room temperature
- plasma
- etching
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- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔イ〕発明の利用分野 本発明は、プラズマ化学気相反応により被形成面上に
平坦または概略平坦な高品質の絶縁膜を減圧下で形成す
る方法を提供するものである。The present invention provides a method for forming a flat or substantially flat high-quality insulating film under reduced pressure on a surface to be formed by plasma chemical vapor reaction. Is.
本発明は、カソード側に基板に配設する等の方法によ
り、異方性プラズマCVD法で絶縁被膜を形成する工程
と、アノード側に基板を配設する等の等方性プラズマエ
ッチング方法とを併用して、凹凸表面を有する被形成面
上に被膜作製を行い、かつその上表面を平坦または概略
平坦(上部と底部との間の高低差が少ないまた滑らかに
連続した形状)に形成する方法を提供するものである。The present invention includes a step of forming an insulating coating by an anisotropic plasma CVD method by a method such as disposing a substrate on the cathode side, and an isotropic plasma etching method such as disposing a substrate on the anode side. In combination, a method of forming a coating on a surface having a concavo-convex surface and forming the upper surface flat or substantially flat (a shape in which there is little difference in height between the top and bottom and a smooth continuous shape) Is provided.
〔ロ〕従来の技術 最近LSIの高集積化、大規模化に伴いICチップに占め
る配線の面積が増えている。[B] Conventional technology Recently, the area of wiring in an IC chip has been increasing with the high integration and large scale of LSI.
そのため、配線の多層化、パターン、配線巾の微細化
がますます重要となりつつある。For this reason, it is becoming more and more important to make the wiring multi-layered and to reduce the pattern and the wiring width.
配線や接続孔などのパターンの横方向寸法は、スケー
リング則に従って微細化するのに対し、電極配線や絶縁
膜の厚さなど縦方向寸法は、配線抵抗、浮遊容量、絶縁
耐圧や耐マイグレーション性など素子のスペックを満た
す必要があり、横方向並みに微細化することは容易でな
い。The horizontal dimensions of patterns such as wiring and connection holes are miniaturized according to scaling rules, while the vertical dimensions such as the thickness of electrode wiring and insulating film are wiring resistance, stray capacitance, withstand voltage, migration resistance, etc. It is necessary to meet the specifications of the device, and it is not easy to miniaturize it in the horizontal direction.
さらに配線や接続孔のパターンは微細化の為異方性の
強いエッチングにより形成されるのでLSIのパターンの
端面形状は急唆となる。Further, since the pattern of the wiring and the contact hole is formed by etching with strong anisotropy for miniaturization, the end surface shape of the LSI pattern becomes sharp.
また,配線が多層となるため,当然LSIチップ上表面
の凹凸が激しくなる。このようなLSIチップ上表面の凹
凸はパターンの加工精度の低下,配線の断線等、信頼性
の低下を招くことになる。Moreover, since the wiring is multi-layered, the unevenness on the upper surface of the LSI chip is naturally severe. Such unevenness on the upper surface of the LSI chip leads to a decrease in reliability such as a decrease in pattern processing accuracy and a disconnection of wiring.
このような問題を解決する手段として,層間絶縁膜の
上表面を平坦化する技術が重要視されている。As a means for solving such a problem, a technique for flattening the upper surface of the interlayer insulating film is emphasized.
この層間絶縁膜を作製する方法としては,従来の化学
的気相反応(以下CVDという)法による薄膜形成技術と
して熱CVD法が広く知られている。この熱CVD法は反応室
内に導入した被膜形成用反応気体に熱エネルギを加え、
該気体を分解または活性化させ、被膜を形成するもので
あった。この場合、反応のためのエネルギ供給を熱のみ
であるため、その温度も高く、500〜800℃の範囲で行わ
れていた。A thermal CVD method is widely known as a method for forming this interlayer insulating film as a thin film forming technology by a conventional chemical vapor phase reaction (hereinafter referred to as CVD) method. This thermal CVD method adds thermal energy to the reaction gas for film formation introduced into the reaction chamber,
The gas was decomposed or activated to form a film. In this case, since the energy supply for the reaction is only heat, the temperature is also high, and the reaction is performed in the range of 500 to 800 ° C.
このため、高温に弱い半導体素子を作製することは不
可能であり、次世代LSI素子として有望な低温で被膜を
形成する技術が求められていた。For this reason, it is impossible to fabricate a semiconductor device that is vulnerable to high temperatures, and a technology for forming a film at a low temperature, which is promising as a next-generation LSI device, has been required.
またより低温で被膜を形成する方法として、プラズマ
CVD法(プラズマを用いた気相被膜作製方法を以下プラ
ズマCVD法という)が知られている。この場合は、反応
室内に導入した反応性気体に外部より高周波電力を印加
し、該気体を分解、活性化せしめ、加熱された基板上に
被膜を形成するものである。この場合、被形成面を有す
る基板をアノード側に配設し、かつ基板の加熱温度は20
0〜450℃の範囲として、成膜する材料の高密度化を計っ
ていた。アノード側に基板を配設する理由は、下地材料
へのプラズマ損傷をなくすためである。さらにこの被膜
形成は、等方性ディポジッションを行う等方性CVD法を
その基本思想としていた。このため、凹部での被膜形成
に際しては、その底部のコーナ部にカスプ(巣)が発生
しやすく、多層配線に際し、ステップカバレージを良好
にすることが不可能であった。As a method of forming a film at a lower temperature, plasma
A CVD method (a gas-phase film forming method using plasma is hereinafter referred to as a plasma CVD method) is known. In this case, high frequency power is applied to the reactive gas introduced into the reaction chamber from the outside to decompose and activate the reactive gas, and a film is formed on the heated substrate. In this case, the substrate having the formation surface is disposed on the anode side, and the heating temperature of the substrate is 20.
In the range of 0 to 450 ° C., the density of the material for film formation was increased. The reason for disposing the substrate on the anode side is to eliminate plasma damage to the underlying material. Furthermore, the basic idea of this film formation is the isotropic CVD method for performing isotropic deposition. For this reason, when forming a film in the recess, cusps (nests) are likely to occur at the corners of the bottom, and it is impossible to improve the step coverage in the case of multilayer wiring.
一方、最近、下地の損傷を防ぐ技術として光CVD法が
ある。この方法は、反応性気体に対して、光エネルギを
与えて分解、活性化させて、基板上に被膜を形成するも
のであり、熱CVD法のように高温にする必要がなく、ま
たプラズマCVD法のように物理的に下地物質にダメージ
を与えず、理想的な成膜法であるが、成膜速度がプラズ
マCVD法の1/10〜1/50と遅い欠点を有する。On the other hand, recently, there is an optical CVD method as a technique for preventing damage to the underlayer. In this method, light energy is applied to a reactive gas to decompose and activate it to form a film on a substrate, which does not require high temperature as in the thermal CVD method, and plasma CVD Although it is an ideal film forming method that does not physically damage the underlying material like the method, it has a drawback that the film forming rate is as slow as 1/10 to 1/50 of the plasma CVD method.
他方、プラズマエッチング方法が半導体集積回路の作
製工程で知られている。これはカソード側に基板を配設
し、セルフバイアスを用いて異方性プラズマエッチング
を行わんとするものである。この異方性エッチングによ
り、所定の領域の凹部を急峻に作らんとしている。On the other hand, a plasma etching method is known as a manufacturing process of a semiconductor integrated circuit. In this method, a substrate is arranged on the cathode side, and anisotropic plasma etching is performed using self bias. By this anisotropic etching, a concave portion in a predetermined area is made sharp.
〔ハ〕本発明の目的 本発明は、これら従来より知られた技術とはまったく
異なるもので、プラズマCVDに際し、異方性を有せしめ
て室温または概略室温で形成する、いわゆる室温異方性
プラズマCVD法(本発明をより明らかにするため仮称す
る)を用いる。さらにプラズマエッチングを等方性を有
して行う、等方性プラズマエッチングを行うことを基本
とし、これを少なくとも各1回繰り返すことを基本とし
ている。[C] Object of the present invention The present invention is completely different from these conventionally known techniques, and is so-called room temperature anisotropic plasma, which is formed at room temperature or approximately room temperature by imparting anisotropy in plasma CVD. The CVD method (provisionally referred to for clarifying the present invention) is used. Further, isotropic plasma etching is basically performed by performing plasma etching with isotropy, and this is basically repeated at least once.
本発明は、これら従来の問題点を解決するものであ
り、急唆な段差のない上表面を有する絶縁膜、特に層間
絶縁膜を形成することを目的としている。The present invention solves these conventional problems, and an object thereof is to form an insulating film having an upper surface without abrupt steps, especially an interlayer insulating film.
本発明は、異方性ディポジッションを室温または概略
室温(室温±50℃以内)プラズマCVD法で行う。する
と、もちろん凹凸表面を有する被形成面の凸部にも成膜
するが、特に凹部における底部に十分緻密な被膜形成を
させ得ることを見出し、この特性を用いて平坦な上表面
を有する絶縁膜を作らんとするものである。本発明は、
この室温異方性プラズマCVD法での成膜と、さらに従来
の異方性プラズマエッチング(リアクティブ・イオン・
エッチングRIEともいう)とは逆の等方性プラズマエッ
チングを室温または概略室温で行い、それぞれを繰り返
すことにより、同一反応系(同一反応炉または複数のマ
ルチチャンバ方式の連続反応炉)にて、上表面が平坦ま
たは滑らかに連続した概略平坦な被膜を作製せんとした
ものである。In the present invention, anisotropic deposition is performed at room temperature or approximately room temperature (room temperature within ± 50 ° C.) by plasma CVD method. Then, of course, a film is also formed on the convex portion of the formation surface having an uneven surface, but it has been found that a particularly dense film can be formed especially on the bottom portion of the concave portion, and using this characteristic, an insulating film having a flat upper surface is formed. Is to make. The present invention
Film formation by this room temperature anisotropic plasma CVD method and conventional anisotropic plasma etching (reactive ion
Etching RIE, which is the reverse of the etching RIE), is performed at room temperature or approximately room temperature, and by repeating each, the same reaction system (same reaction furnace or multiple multi-chamber continuous reaction furnaces) This is an attempt to produce a substantially flat coating having a flat or smooth surface.
本発明は、光化学気相反応を用いて酸化珪素膜等の絶
縁膜を基板上に形成し、プラズマ損傷を軽減した後、室
温異方性プラズマCVD法にて、所定の膜厚(例えば0.5〜
3μm)にまで酸化珪素被膜を形成した後、同一反応系
内にて等方性プラズマエッチング処理(以下エッチバッ
ク処理という)を施すことを特徴とするものである。The present invention forms an insulating film such as a silicon oxide film on a substrate by using a photochemical vapor reaction to reduce plasma damage, and then a room temperature anisotropic plasma CVD method is performed to obtain a predetermined film thickness (for example, 0.5 to
After forming a silicon oxide film up to 3 μm), isotropic plasma etching treatment (hereinafter referred to as etch back treatment) is performed in the same reaction system.
さらに必要に応じて、これらの工程を繰り返すことに
より、上表面が急唆な凹凸段差のない絶縁膜、即ち平坦
または実質的に平坦な上表面を有する絶縁膜を形成する
ものである。Further, if necessary, these steps are repeated to form an insulating film having an upper surface without abrupt unevenness, that is, an insulating film having a flat or substantially flat upper surface.
本発明は、異方性プラズマCVD法と等方性プラズマエ
ッチングとを等温または概略等温(互いに±50℃以下内
の温度差)として処理し、1工程と次工程との間の待ち
時間をなくすることにより、その生産性を向上させる。
さらに本発明は、ともに室温の外部加熱なく(プラズマ
による自己加熱はある)行い得ることを見出し、かかる
室温での異方性プラズマCVD法で層間絶縁膜、埋置した
フィールド絶縁膜用に十分実使用可能な特性を有するこ
とを発見した。The present invention treats the anisotropic plasma CVD method and the isotropic plasma etching as isothermal or approximately isothermal (a temperature difference within ± 50 ° C. of each other), and eliminates the waiting time between one step and the next step. To improve its productivity.
Furthermore, the present invention has found that both can be performed without external heating at room temperature (there is self-heating by plasma), and is sufficiently practical for an interlayer insulating film and a buried field insulating film by such an anisotropic plasma CVD method at room temperature. It has been found to have usable properties.
以下に実験例を示し、本発明に示された酸化珪素被膜
の作製方法を示す。An experimental example will be shown below to show a method for producing the silicon oxide film shown in the present invention.
実施例1 第2図に本実験で用いた絶縁被膜形成用装置の概略図
を示す。Example 1 FIG. 2 shows a schematic view of an insulating film forming apparatus used in this experiment.
図面において、反応室(1)内には一対の電極
(2),(8)が設けられ、それらはともに接地レベル
から絶縁されている。そしてその一方には、被形成面を
有する基板(3)が配設されている。さらに反応室
(1)内には光CVDもできるように紫外光源室(4)を
有し、ここには複数の紫外光源(6)が設置されてお
り、前記紫外光源室(4)は反応室(1)の圧力とほぼ
等しくなるように調整されている。また被膜形成用基板
(3)は、反応容器から絶縁化された基板加熱用ヒータ
を兼ねた基板支持体(2)により、反応室(1)内に被
膜形成面を下向きになるように設置されている。本装置
では、成膜時に発生するフレーク等のゴミが基板に付着
しないようにデポジションアップ方式を採用した。In the figure, a pair of electrodes (2), (8) are provided in the reaction chamber (1), both of which are insulated from the ground level. A substrate (3) having a surface to be formed is arranged on one side thereof. Further, in the reaction chamber (1), an ultraviolet light source chamber (4) is provided so that photo CVD can be performed, and a plurality of ultraviolet light sources (6) are installed therein, and the ultraviolet light source chamber (4) reacts. It is adjusted to be approximately equal to the pressure in the chamber (1). The film-forming substrate (3) is installed in the reaction chamber (1) with the film-forming surface facing downward by the substrate support (2) that is also insulated from the reaction container and also serves as a heater for heating the substrate. ing. In this equipment, the deposition up method is adopted so that dust such as flakes generated during film formation does not adhere to the substrate.
プラズマ処理用電源(9)からマッチングコイル(1
0)をへて高周波エネルギが一対の電極(2),(8)
に連結されている。そして一方を接地してアノードと、
他方を負の100〜500Vのバイアスがかかるカソードとす
べくスイッチ(11)により接地(12)が選択される。From the plasma processing power supply (9) to the matching coil (1
High frequency energy goes through a pair of electrodes (2), (8)
It is connected to. And ground one and use it as an anode,
The ground (12) is selected by the switch (11) so that the other is the negatively biased cathode of 100-500V.
異方性CVDを行わんとする場合は、電極(8)を接地
しアノード側とし、基板のある電極(2)をカソード側
(−100〜−500Vの自己バイアスがかかる)とする。When anisotropic CVD is to be performed, the electrode (8) is grounded to the anode side, and the electrode (2) with the substrate is the cathode side (self bias of −100 to −500 V is applied).
異方性CVDとは、反応性気体がバイアス電圧で電界方
向に加速され、方向性を有する。そしてこの加速により
被形成面上に衝突すると、そこでこの運動エネルギをも
加わり緻密な膜を作ることができる。この方向性を有す
るため、成膜された被膜の膜厚はバイアス電界と垂直な
面には厚く形成され、バイアス電界と平行な面(側面)
には薄く形成される。とくに凹部の底部にも十分加速さ
れた反応性気体が到達するため、底部でも緻密な膜がで
き、カスプ等の発生を防ぐことができる。In anisotropic CVD, a reactive gas is directional because it is accelerated in the direction of an electric field by a bias voltage. Then, when the surface collides with the surface to be formed by this acceleration, this kinetic energy is also added thereto, and a dense film can be formed. Due to this directional property, the film thickness of the formed film is thick on the surface perpendicular to the bias electric field and parallel to the bias electric field (side surface).
Is formed thin. In particular, since the sufficiently accelerated reactive gas reaches the bottom of the recess as well, a dense film can be formed even at the bottom, and the generation of cusps and the like can be prevented.
そしてこの緻密さは基板の温度をこれまでのように30
0〜500℃に加熱することなく、室温または室温±50℃以
内でも十分に保障できることを見出した。And this compactness keeps the substrate temperature at 30%
It was found that room temperature or room temperature ± 50 ℃ can be sufficiently ensured without heating to 0 to 500 ℃.
他方、等方性プラズマエッチングを行う時は、電極
(2)を接地し、基板に自己バイアスのかからないアノ
ード側とし、電極(8)をカソード側とする。On the other hand, when performing isotropic plasma etching, the electrode (2) is grounded so that the substrate is on the anode side without self-bias and the electrode (8) is on the cathode side.
即ち、等方性エッチングは、エッチングされる表面に
反応性気体が電界により加速されることなく、均質に衝
突し、その表面でプラズマ反応をさせんとするものであ
る。このため凸部にはより多くのラジカルが衝突するた
め、エッチングされやすく、凹部はラジカルがなかなか
到達しにくいため、エッチングされにくい。このラジカ
ルの方向性をもつバイアスをかけないでエッチングをさ
せるのが等方性エッチングである。That is, isotropic etching is a method in which a reactive gas is uniformly impinged on the surface to be etched without being accelerated by an electric field, and a plasma reaction is caused on the surface. For this reason, more radicals collide with the convex portions and are easily etched, and radicals are less likely to reach the concave portions, and thus are less likely to be etched. Isotropic etching is to perform etching without applying a bias having the directionality of this radical.
異方性CVD法において、反応性気体のうち、珪化物気
体及び酸化物気体は配管内でMIXされ、ガスノズル
(7)より反応室内へ導入し、基板(3)近くで混合す
るようになっている。不要気体は(13)より排気され
る。In the anisotropic CVD method, among the reactive gases, the silicide gas and the oxide gas are mixed in the pipe, introduced into the reaction chamber through the gas nozzle (7), and mixed near the substrate (3). There is. The unnecessary gas is exhausted from (13).
光化学気相反応に際しては、紫外光源(6)より照射
される紫外光は、石英の透過窓(5)を通って反応性気
体に照射される直接励起法を採用した。In the photochemical gas phase reaction, a direct excitation method was adopted in which the ultraviolet light emitted from the ultraviolet light source (6) was applied to the reactive gas through the quartz transmission window (5).
さらに,透外光透過窓(5)の上は、異方性プラズマ
CVD、等方性プラズマエッチング用のメッシュ電極
(8)が載せられている。このメッシュ電極(8)に
は、基板支持体用電極(2)との間に電源(9)により
高周波電力を印加可能なように構成されている。さらに
図示されていないが、異方性プラズマCVDを助長させる
ため、必要に応じて電極(2)と基板支持体電極(2)
間に交流バイアス電圧(例えば50KHz,ピーク電圧±350
V,基板側に直流負バイアス−100〜−500V)を加えるこ
とは有効である。Furthermore, an anisotropic plasma is formed on the transparent window (5).
A mesh electrode (8) for CVD and isotropic plasma etching is placed. A high frequency power can be applied to the mesh electrode (8) by a power source (9) between the mesh electrode (8) and the substrate support electrode (2). Although not shown in the drawing, the electrode (2) and the substrate support electrode (2) are optionally used to promote anisotropic plasma CVD.
AC bias voltage (eg 50KHz, peak voltage ± 350
V, it is effective to add a DC negative bias of −100 to −500V to the substrate side.
本装置を用いて、第1図(A)に示すような凹凸を有
する基板に反応圧力が0.01〜0.3torr、基板温度は室温
(室温±50℃以下),投入高周波電力13.56MHz,100W〜5
00Wの条件下にて反応性気体としてモノシランと亜酸化
窒素との割合を変化させて酸化珪素被膜を形成した。Using this device, the reaction pressure is 0.01 to 0.3 torr on the substrate having irregularities as shown in FIG. 1 (A), the substrate temperature is room temperature (room temperature ± 50 ° C. or less), input high frequency power 13.56 MHz, 100 W to 5 W
A silicon oxide film was formed by changing the ratio of monosilane and nitrous oxide as a reactive gas under the condition of 00W.
SiH4/N2O比を0.005から0.5の範囲での酸化珪素被膜の
屈折率、赤外吸収から次の反応が考えられる。The following reactions can be considered from the refractive index and infrared absorption of the silicon oxide film in the SiH 4 / N 2 O ratio of 0.005 to 0.5.
SiH4+2N2O→SiO2+2N2+2H2 このような異方性プラズマCVDにより、第1図(A)
に示すような凹凸形状を有する被形成面を有する基板上
に酸化珪素被膜等の絶縁被膜を形成する。第1図(A)
において、凸部(23),狭い巾の凹部(21)、広い巾の
凹部(22)を有する。これらの上面に、平均膜厚で8000
Åの厚さに酸化珪素膜(30−1)を異方性プラズマCVD
法により形成した。すると凸部の上面(24)、凹部の底
面,(26)には膜厚が1.0μの厚さに被膜が形成され
た。側面(25)には0.2μの厚さにしか成膜させないこ
とができた。SiH 4 + 2N 2 O → SiO 2 + 2N 2 + 2H 2 By such anisotropic plasma CVD, Fig. 1 (A)
An insulating film such as a silicon oxide film is formed on a substrate having a formation surface having an uneven shape as shown in FIG. Fig. 1 (A)
In, there are a convex portion (23), a concave portion (21) having a narrow width, and a concave portion (22) having a wide width. 8000 average film thickness on top of these
Anisotropic plasma CVD of silicon oxide film (30-1) to a thickness of Å
It was formed by a method. Then, a film having a thickness of 1.0 μ was formed on the upper surface (24) of the convex portion and the bottom surface (26) of the concave portion. The side surface (25) could only be formed to a thickness of 0.2μ.
このプロセス条件はSiH4/N2O=1/2、高周波出力300
W、13.56MHzとし、基板はカソート側に配設した。この
時自己バイアスは−350Vであった。そして基板温度は室
温とした。常温での成膜にもかかわらず、比抵抗は5×
1017Ωcmを有し、耐圧は8×106V/cm(1μA/cm2以上の
電流の流れる電圧)を有していた。この場合、プラズマ
の圧力は0.05torr、成膜速度は0.1〜1μ/分と速い値
が得られた。This process condition is SiH 4 / N 2 O = 1/2, high frequency output 300
W, 13.56 MHz, and the substrate was placed on the Casotto side. At this time, the self-bias was -350V. The substrate temperature was room temperature. Despite film formation at room temperature, the specific resistance is 5 ×
It had a resistance of 10 17 Ωcm and a breakdown voltage of 8 × 10 6 V / cm (voltage at which a current of 1 μA / cm 2 or more flows). In this case, the plasma pressure was as high as 0.05 torr and the film formation rate was as high as 0.1 to 1 μ / min.
基板(3)の凸部(23)は高さ1μm程度狭い凹部
(21)のスペース0.8μmの形状を、広い凹部(22)の
スペースは2μmを有していた。この凹凸形状を均一に
覆うことができた。The convex portion (23) of the substrate (3) had a shape in which the space of the concave portion (21) was 0.8 μm narrow and the width of the wide concave portion (22) was 2 μm. The uneven shape could be uniformly covered.
この上面の厚さ/側面の厚さは2〜20一般には3以上
に有せしめ得た。The thickness of the upper surface / thickness of the side surface can be set to 2 to 20 and generally 3 or more.
次にこの絶縁膜に等方性エッチングを施した。 Next, this insulating film was subjected to isotropic etching.
第1図(A)のように凹凸基板表面を覆って酸化珪素
被膜を厚く形成した後,反応室内の反応性ガスを排気し
て除去し、エッチング用気体である有機ハロゲン化物気
体、例えばCF4,CF3HまたはNF3,SF6等を反応室内に導入
し,圧力を0.1torrに微調整して、メッシュ電極(カソ
ード)(8)と基板支持体電極(アノード)(2)間に
高周波電力を印加して、等方性プラズマエッチングを室
温で生ぜしめるべく放電を起こし,形成された被膜(30
−1)のエッチングを行い、凹凸段差の急唆な部分をな
くした。すると、第1図(B)に示す如く、凹部(28)
ではあまりエッチングされず、凸部上の酸化珪素膜(2
4)の一部または全部を主としてエッチングさせること
ができる。そのため、凹部に絶縁膜を意図的にうめこん
で作ることができた。As shown in FIG. 1 (A), after forming a thick silicon oxide film to cover the surface of the uneven substrate, the reactive gas in the reaction chamber is exhausted and removed, and an organic halide gas such as CF 4 is used as an etching gas. , CF 3 H or NF 3 , SF 6 etc. were introduced into the reaction chamber and the pressure was finely adjusted to 0.1 torr, and high frequency was applied between the mesh electrode (cathode) (8) and the substrate support electrode (anode) (2). A film was formed by applying an electric power and causing an electrical discharge to generate isotropic plasma etching at room temperature (30
The etching of -1) was performed to eliminate the abruptly uneven portion. Then, as shown in FIG. 1 (B), the recess (28)
The silicon oxide film (2
Part or all of 4) can be mainly etched. Therefore, the insulating film could be deliberately embedded in the recess.
この処理を行い、凹部でのエッチングを0〜0.2μm
と少なくし、かつ凸部上で絶縁膜を約0.2〜0.5μmの厚
さにエッチングを行い、(エッチング比2〜10例えば3
以上とし得た)第1図(B)に示すように凹凸段差の急
唆な部分を取り除いた。かくして一装置,同一反応室に
て急唆な段差のない層間絶縁膜(30−2)を作製するこ
とができた。Performing this process, etching in the recess is 0 to 0.2 μm
And etching the insulating film on the convex portion to a thickness of about 0.2 to 0.5 μm (etching ratio 2 to 10 for example 3
As shown in FIG. 1B, which was obtained as described above, the abrupt portions of the uneven steps were removed. Thus, it was possible to fabricate the interlayer insulating film (30-2) without abrupt steps in the same reaction chamber in one apparatus.
この図面では凸部上の被膜の厚さが薄すぎること、お
よびまだ十分に上表面が平坦化されていないため、この
工程を再び繰り返した。即ち、第1図(C)に示される
如く、これらの上に室温での異方性CVD法により第1図
(A)と同じく絶縁膜(30−3)を絶縁膜(30−2)上
に積層して絶縁膜(31)を得た。さらにこの後第1図
(D)に示す如く、第1図(B)の工程と同じく、等方
性プラズマエッチングを行った。そして絶縁膜(30−
4)を得た。すると凸部上の絶縁膜は(28′)と凹部上
の絶縁膜(26′)とをこの境界(25′)で滑らかに互い
に連続させることができた。この滑らかに連続した上表
面は、その上に他の微細電気配線を同一の線巾で作製す
るためにはきわめて重要である。This step was repeated again because the thickness of the coating on the protrusions was too thin in this figure and the top surface was not yet sufficiently flattened. That is, as shown in FIG. 1 (C), an insulating film (30-3) is formed on the insulating film (30-2) by an anisotropic CVD method at room temperature as in FIG. 1 (A). To obtain an insulating film (31). Further, thereafter, as shown in FIG. 1 (D), isotropic plasma etching was performed as in the step of FIG. 1 (B). And insulating film (30-
4) was obtained. Then, the insulating film (28 ') on the convex portion and the insulating film (26') on the concave portion could be smoothly continuous with each other at this boundary (25 '). This smoothly continuous upper surface is extremely important for producing other fine electric wirings with the same line width on the upper surface.
さらに必要に応じてこれらを繰り返し行うことによ
り、第1図(E)に示す如く、上表面の平坦な酸化珪素
膜(30−5)を作ることができた。Further, by repeating these as required, a silicon oxide film (30-5) having a flat upper surface could be formed as shown in FIG. 1 (E).
また、エッチング処理時に、同時に反応室内壁及び透
過光窓(5)上について被膜を除去することができ、装
置をクリーニングのためにその運転を停止する必要がな
く生産性向上に繋がった。Further, at the time of the etching treatment, the coating can be simultaneously removed on the inner wall of the reaction chamber and the transmitted light window (5), and it is not necessary to stop the operation of the apparatus for cleaning, which leads to the improvement of productivity.
また本実施例においては、酸化珪素被膜の作製を異方
性プラズマCVD法と等方性プラズマエッチング法とを併
用したが,この異方性プラズマCVDで成膜する際に凹凸
表面を有する基板上のプラズマ損傷を防ぐため、予め光
CVD法でこれら全体を覆って作製し、その後に本発明の
実施例を用いてもいいことは明らかである。In addition, in the present embodiment, the production of the silicon oxide film is performed by using the anisotropic plasma CVD method and the isotropic plasma etching method together. However, when the film is formed by this anisotropic plasma CVD, the substrate having an uneven surface is formed. To prevent plasma damage of the
Obviously, it is possible to cover all of them by the CVD method and then use the embodiment of the present invention.
実施例2 この実施例は他構成の被膜作製装置の概要を示す。Example 2 This example outlines a film forming apparatus having another structure.
この第3図において、第3図(A)はA−A′の縦断
面図を示し、(B)は上側よりみたものである。In FIG. 3, FIG. 3 (A) is a vertical sectional view taken along the line AA ′, and FIG. 3 (B) is seen from above.
基板のロード/アンロード室(47)とその前方にバッ
ファ室(46)を有する。領域(41)は光CVDを行うため
の反応室、領域(42)は異方性プラズマCVDを行うため
の反応室、領域(43)は等方性エッチングを行うための
反応室、領域(44)は異方性プラズマCVDを行うための
空間、または(45)は等方性プラズマエッチングを行う
ための空間である。各反応室はゲート弁(51),(5
2),(53),(54),(55),(56)で仕切られてお
り、それぞれの反応室で同時に被形成面を有する基板
(3−1),(3−2),(3−3),(3−4),
(3−5)が処理される。この処理中にロード/アンロ
ード室(47)とバッファ室(46)との間で、成膜した基
板(3−6)を取り出し、まだ成膜していない新たな凹
凸表面を有する基板を(47)より(46)に挿入配設す
る。それぞれの反応室で、実施例1に示す如く、所定の
異方性プラズマCVD、等方性プラズマエッチ処理が行わ
れた後、すべての反応室を真空引きした。そして各反応
室を等圧にした後、(51)・・・(56)のゲート弁を同
時に開とする。さらに全基板を隣の反応室に矢印の如く
移設した、即ち基板(3−1)は(3−2)の位置に、
基板(3−2)は(3−3)の位置に、基板(3−3)
は(3−4)の位置に、基板(3−4)は(3−5)の
位置に、基板(3−5)は(3−6)の位置に移設さ
れ、(3−6)の基板は前記した如く取り出される。It has a substrate loading / unloading chamber (47) and a buffer chamber (46) in front of it. A region (41) is a reaction chamber for performing optical CVD, a region (42) is a reaction chamber for performing anisotropic plasma CVD, a region (43) is a reaction chamber for performing isotropic etching, and a region (44). ) Is a space for performing anisotropic plasma CVD, or (45) is a space for performing isotropic plasma etching. Each reaction chamber has a gate valve (51), (5
Substrates (3-1), (3-2), (3) which are partitioned by 2), (53), (54), (55), and (56), and which have a surface to be formed in each reaction chamber at the same time. -3), (3-4),
(3-5) is processed. During this process, the film-formed substrate (3-6) is taken out between the load / unload chamber (47) and the buffer chamber (46), and a substrate having a new uneven surface not yet formed ( Insert it from (47) to (46). In each of the reaction chambers, as shown in Example 1, a predetermined anisotropic plasma CVD and isotropic plasma etching treatment were performed, and then all the reaction chambers were evacuated. And after making each reaction chamber an equal pressure, the gate valves of (51) ... (56) are simultaneously opened. Further, all the substrates were transferred to the adjacent reaction chamber as shown by the arrow, that is, the substrate (3-1) was at the position (3-2),
The board (3-2) is located at the position (3-3), and the board (3-3) is
Is moved to the position (3-4), the substrate (3-4) is moved to the position (3-5), and the substrate (3-5) is moved to the position (3-6). The substrate is removed as described above.
第3図(A)に示す如く、異方性プラズマCVDを行う
には、反応室(42),(44)に示す如く、基板側をカソ
ード側とする。また等方性エッチングを行うには反応室
(43),(45)に示す如く、基板側をアノード側とす
る。As shown in FIG. 3 (A), in order to perform anisotropic plasma CVD, the substrate side is the cathode side as shown in the reaction chambers (42) and (44). To perform isotropic etching, the substrate side is the anode side as shown in the reaction chambers (43) and (45).
かくして第1図に示す如く、平坦または実質的に平坦
な表面を有する絶縁膜を凹凸表面上に作製することがで
きた。Thus, as shown in FIG. 1, an insulating film having a flat or substantially flat surface could be formed on the uneven surface.
第3図に示す如くマルチチャンバ構成とすると、第2
図に示した1つの反応室でのみ作られるに比べて約3倍
のスループットを得ることができた。If a multi-chamber configuration is used as shown in FIG.
It was possible to obtain about 3 times the throughput as compared with the case where only one reaction chamber shown in the figure was used.
さらに第3図において、反応室(41),(42),(4
4)は主に成膜のみであるため、異方性プラズマCVDと、
等方性プラズマエッチングとを1つづつずらすことによ
り、自動的に反応室内壁のクリーニングを行い得る。Furthermore, in FIG. 3, reaction chambers (41), (42), (4
Since 4) is mainly only film formation, anisotropic plasma CVD,
By shifting the isotropic plasma etching one by one, the inner wall of the reaction chamber can be automatically cleaned.
第3図において示す如く、基板はすべての反応室で等
温となっており、特にこの実施例では室温±50℃以内と
した。するとこれまではプラズマCVDといえども成膜は3
00〜400℃、エッチングは室温であるため、反応室毎に3
00℃以上の温度差を有し、その昇温、降温に多くの待ち
時間を必要とした。しかし本発明に示す如く、室温で作
られた異方性プラズマCVDで成膜した膜は、予想以上に
固い緻密であることを発見したため、これら異方性CVD
と等方性エッチングをともに室温とすることが可能とな
り、生産性の向上を始め、量産化が可能なマルチチャン
バ構造装置を作ることができた。As shown in FIG. 3, the substrate was isothermal in all reaction chambers, and in particular, in this embodiment, the room temperature was within ± 50 ° C. Then, even though plasma CVD has been used so far, film formation has been 3 times.
00 ~ 400 ℃, etching is at room temperature, so 3 for each reaction chamber
There was a temperature difference of over 00 ° C, and much waiting time was required for raising and lowering the temperature. However, as shown in the present invention, it was discovered that the film formed by anisotropic plasma CVD made at room temperature was denser and harder than expected.
Since both isotropic etching and room temperature etching can be performed at room temperature, it is possible to manufacture a multi-chamber structure device that can be mass-produced, improving productivity.
もちろんこのチャンバの数は必要に応じて多くしても
よい。またその移設のため、すべてを同時に行うのでは
なく、一度各反応室間にバッファ空間を設ける間接的な
連続方式のマルチチャンバ装置としてもよい。Of course, the number of chambers may be increased if necessary. Further, due to the relocation, not all are performed simultaneously, but an indirect continuous multi-chamber apparatus in which a buffer space is once provided between the reaction chambers may be used.
以上の実施例において、絶縁膜として酸化珪素被膜を
開示したが、その他の絶縁膜、窒化珪素膜、PSG(リン
ガラス),BSG(ホウ素ガラス),アルミナ膜でも応用可
能である。In the above embodiments, the silicon oxide film is disclosed as the insulating film, but other insulating films, silicon nitride film, PSG (phosphorus glass), BSG (boron glass), and alumina film are also applicable.
さらに酸化珪素膜の成膜用の反応性気体として、モノ
シランのみでなく、その他のポリシラン類(Sin
H2n+2),ジメチルシラン,テトラメチルシラン等の有
機珪素化合物(SiHn(CH4)4-n)またはテトラエトキシ
シラン(TEOS)のような有機珪素酸素化物と酸化物気体
との反応を必要に応じて使用することも可能である。Further, as a reactive gas for forming the silicon oxide film, not only monosilane but also other polysilanes (Sin
H2n + 2 ), dimethylsilane, tetramethylsilane and other organosilicon compounds (SiHn (CH 4 ) 4-n ) or tetraethoxysilane (TEOS) such as organosilicon oxygenates and oxide gases need to be reacted It is also possible to use according to.
〔ホ〕効果 以上示したように、本発明は従来用いられていた「等
方性」プラズマCVD、「異方性」プラズマエッチとはま
ったく逆に「異方性」プラズマCVD,「等方性」プラズマ
エッチとすることにより、凹凸表面を有する基板上に平
坦または実質的に平坦な上表面を有する絶縁膜を形成す
ることができた。そしてプラズマCVD法が室温またはそ
れに近い温度で行い得るため、生産性を以前の3倍以上
にすることができた。[E] Effect As described above, the present invention is completely opposite to the “isotropic” plasma CVD and the “anisotropic” plasma etching that have been conventionally used. By the plasma etching, it was possible to form an insulating film having a flat or substantially flat upper surface on a substrate having an uneven surface. And since the plasma CVD method can be performed at room temperature or a temperature close to it, the productivity could be more than three times that of the previous one.
また凹部に発生しやすいカスプも除去することができ
た。Further, it was possible to remove the cusp which is likely to occur in the recess.
本発明方法により,超LSI等の急唆な凹凸段差のない
層間絶縁膜、埋置したフィールド絶縁膜を同一の装置の
同一反応室内で作製することができ、装置コスト製造コ
ストを下げるこできた。According to the method of the present invention, it is possible to fabricate an interlayer insulating film without abrupt unevenness and a buried field insulating film of VLSI or the like in the same reaction chamber of the same device, and it is possible to reduce the manufacturing cost of the device. .
また、エッチバック工程時に反応室内壁及び透過光窓
のエッチングも同時に行なえるという特徴を持つ。In addition, the etching of the reaction chamber wall and the transmitted light window can be performed simultaneously during the etch-back process.
第1図は本発明の層間絶縁膜作製の工程を示す。 第2図および第3図は本発明にて用いた装置の概略図を
示す。FIG. 1 shows a step of producing an interlayer insulating film of the present invention. 2 and 3 show schematic views of the apparatus used in the present invention.
Claims (2)
に保持してプラズマ気相化学反応を行うことにより、導
体の凸部を有する基板上または該基板上に被膜を形成し
た被形成面上に絶縁被膜を形成する工程と、前記凸部上
の絶縁膜の一部または全部を前記基板をアノード側に配
設して室温または概略室温に保持しつつプラズマエッチ
ング法により除去する工程とを少なくとも各1回有せし
めることにより、前記被形成面上に平坦または概略平坦
な表面を有する被膜を形成することを特徴とするプラズ
マ気相反応方法。1. A substrate having convex portions of a conductor or a surface on which a coating film is formed on a substrate on which a film is formed by conducting a plasma gas-phase chemical reaction while maintaining the temperature at or near room temperature disposed on the cathode side. At least a step of forming an insulating coating on the substrate, and a step of removing a part or all of the insulating film on the convex portion by plasma etching while maintaining the substrate at the anode side and keeping it at room temperature or approximately room temperature. A plasma vapor phase reaction method, characterized in that a coating film having a flat or substantially flat surface is formed on the surface to be formed by allowing each coating to be performed once.
気相化学反応方法は珪化物気体と酸化物気体とを反応せ
しめ酸化珪素を形成することを特徴とするプラズマ気相
反応方法。2. The plasma gas phase chemical reaction method according to claim 1, wherein the plasma gas phase chemical reaction method comprises reacting a silicide gas and an oxide gas to form silicon oxide.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63127577A JP2684381B2 (en) | 1988-05-24 | 1988-05-24 | Plasma gas phase reaction method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63127577A JP2684381B2 (en) | 1988-05-24 | 1988-05-24 | Plasma gas phase reaction method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01296622A JPH01296622A (en) | 1989-11-30 |
JP2684381B2 true JP2684381B2 (en) | 1997-12-03 |
Family
ID=14963500
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JPS5756948A (en) * | 1980-09-22 | 1982-04-05 | Toshiba Corp | Manufacture of semiconductor device |
JPS60249328A (en) * | 1984-05-25 | 1985-12-10 | Kokusai Electric Co Ltd | Apparatus for dry-etching and chemical vapor-phase growth of semiconductor wafer |
JPS62224029A (en) * | 1986-03-26 | 1987-10-02 | Mitsubishi Electric Corp | Semiconductor manufacture equipment |
JPS6376434A (en) * | 1986-09-19 | 1988-04-06 | Hitachi Ltd | Plasma treatment equipment |
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