JP2682759B2 - Instruction fetch circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction fetch circuit used in an information processing apparatus for inputting an instruction stream (instruction string) read from a storage controller into a pipeline and executing it sequentially. In order to speed up the processing in an information processing apparatus that executes instructions by pipeline control, it is necessary to supply instructions to the instruction execution pipeline without waiting for the instruction execution pipeline.

However, the conventional instruction fetch circuit can fetch only the instruction sequence currently being executed in the instruction execution pipeline, and in particular, by determining the branch instruction in the predictive branch control, other instruction streams currently being executed in the pipeline can be fetched. In the case of branching to the instruction stream of, the instruction execution pipeline is kept waiting until a new instruction stream is fetched and supplied, and improvement of this point is desired.

[0003]

2. Description of the Related Art Conventionally, in an information processing apparatus employing a pipeline control system, an instruction fetch control unit fetches an instruction from an instruction cache of a storage control unit and stores it in an instruction buffer, and then an instruction execution unit It is supplied to the instruction execution pipeline and executed.

Normally, an instruction fetch operation is performed in an instruction fetch pipeline consisting of several states, and it takes several τ (where τ is a machine cycle) from sending an instruction fetch request to sending data. However, in an instruction buffer that has a capacity for only one instruction fetch, an instruction fetch request is issued after the instruction string in the instruction buffer is consumed, so the time required for fetching is an empty stage of the instruction execution pipeline. Appears.

In such an instruction fetch circuit, there is a possibility that the pipeline is kept waiting each time an instruction string in the instruction buffer is consumed and a new fetch is performed, and the high speed of the instruction execution pipeline cannot be utilized. In order to solve this problem, an instruction fetch circuit has been proposed in which the capacity of the instruction buffer is increased and one instruction stream can be stored by a plurality of consecutive fetches.

[0006]

However, in the conventional instruction fetch circuit having only a single series of instruction buffers, even if one instruction stream can be fetched, the execution instruction stream is changed like a branch instruction. When an instruction is executed, a branch instruction is input to the pipeline and a fetch request for the branch destination instruction string is issued from the time when the branch is confirmed, so that the instruction execution pipeline waits during that time.

Therefore, prior to the instruction input to the pipeline, fetch instructions can be buffered a plurality of times for the instruction stream currently being executed in the execution pipeline.
Furthermore, an instruction fetch circuit that can fetch the branch destination up to once is considered. In such an instruction fetch circuit, a fetch request is issued to a subsequent instruction string of a branch destination instruction that has already been fetched from the time when the branch instruction is input to the pipeline and the branch is confirmed.
However, since fetching a subsequent branch instruction also requires several τ, the instructions in the instruction buffer are consumed during this period, which may delay the instruction input to the pipeline.

As described above, in the conventional instruction buffer of the instruction fetch circuit, when the instruction stream is changed, the instruction input to the instruction execution pipeline is delayed, and an empty stage occurs in the pipeline, resulting in deterioration of processing performance. However, there is a problem in that the effect of branch prediction control itself is diminished due to the delay in the instruction input in the control of branch prediction intended to speed up processing.

The present invention has been made in view of the above-mentioned conventional problems, and provides an instruction fetch circuit capable of inputting a plurality of series of instruction streams into a continuous instruction execution pipeline to improve processing performance. The purpose is to do.

[0010]

FIG. 1 is a diagram illustrating the principle of the present invention. First, the present invention is directed to an instruction fetch circuit that fetches an instruction from the storage control device 3 by the instruction fetch control unit 1 and stores it in the instruction buffer circuit 2 and then supplies it to the instruction execution pipeline of the instruction execution unit 4 for execution. To do.

In the present invention as such an instruction fetch circuit, a plurality of series of instruction buffers 2-1 to 2-n are provided in parallel as the instruction buffer circuit 2 and the instruction buffers 2-1 to 2-n are used. The series is identified by the identifiers ID1 to ID. Such a plurality of series of instruction buffers 2-
Corresponding to 1 to 2n, the instruction buffer control unit 1 issues an instruction fetch request to the storage control device 3 independently for each series of the instruction buffers 2-1 to 2-n, and the instruction that has issued the fetch request. It is characterized in that the instruction fetch request is sequentially repeated until the buffer sequence is saturated, and a plurality of instruction streams can be prepared for the instruction execution pipeline of the instruction execution unit 4.

Here, a plurality of series of instruction buffers 2-1 to 2-1.
The 2-n includes a plurality of buffers having a storage capacity larger than a storage capacity required for one instruction fetch from the storage control device 3, and buffers and holds the fetch data for a plurality of instruction fetches. It can be so. Further, each of the instruction buffers 2-1 to 2-n has a pointer that points to the head of the instruction stream in the own sequence buffer, and when the own sequence is selected by the instruction fetch control unit 2, the instruction of the instruction execution unit 4 An instruction stream is presented which starts with the pointer to be put into the execution pipeline as the head position.

As for updating the pointer, when the instruction fetch control unit 2 newly fetches an instruction from the storage control device 3 in its own sequence, the pointer is updated by the capacity of one instruction buffer. Further, when an instruction is consumed by the instruction fetch control unit 2 from any one of the plurality of series of instruction buffers 2-1 to 2-n and the instruction is input to the instruction execution pipeline of the instruction execution unit 4, the pointer is input. Update only the size.

[0014]

According to the instruction fetch circuit of the present invention having such a configuration, the following action can be obtained. The instruction fetch circuit of the present invention has a plurality of series of instruction buffers 2-1 to 2-n in parallel, each series is identified by an identifier, and in addition to the instruction stream currently being executed in the pipeline, for example, a plurality of series are provided. Each branch independently fetches and buffers the branch target instruction stream of.

Each of the instruction buffers 2-1 to 2-n has a buffer having a capacity larger than the amount of one instruction fetch, and the contents of one instruction stream by a plurality of instruction fetches can be buffered. . Each of the instruction buffers 2-1 to 2-n has a pointer that indicates the position of the head instruction of its own instruction queue in the own instruction buffer, and presents an instruction to the instruction fetch control unit.

The instruction fetch control unit 1 selects from among the instructions presented from the series of the instruction buffers 2-1 to 2-n.
Select the instruction stream to be executed and put it into the instruction execution pipeline. Further, since the instruction amount in the instruction buffer of each series can be recognized by the pointer indicating the instruction head position, it is possible to issue a sequential instruction fetch request from each instruction buffer 2-1 to 2-n independently from the series.

As a result, a plurality of instruction streams can be buffered, and especially when branch prediction control from the branch history is performed, the branch destination instruction stream is input to the pipeline before the branch is determined, so that after the branch is determined. It is possible to prevent waiting for pipeline instruction input due to instruction fetch, and to sufficiently bring out the original performance of branch prediction control.

[0018]

FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 2, reference numeral 10 is a CPU device as an information processing device incorporating the instruction fetch circuit of the present invention. The CPU device 10 is provided with a storage control unit 3 including an instruction cache 5, an instruction fetch unit 6 including an instruction fetch control unit 1 and an instruction buffer circuit 2, and an instruction execution unit 4 including an instruction execution pipeline 7. To be

The memory control unit 3 is provided with an instruction fetch pipeline 8. By operating the instruction fetch pipeline 8, an instruction is fetched from the instruction cache 5 of the memory control unit 3 into the instruction buffer circuit 2 and then the instruction is executed. Input to the instruction execution pipeline 7 of the section 4. Further, the instruction fetch control unit 1 sends an instruction fetch request and an instruction fetch address to the instruction cache 5 as the instruction fetch pipeline 8 is executed, controls the buffering of an instruction sent, and inputs an instruction to the instruction execution pipeline 7. Take control.

FIG. 3 is a circuit diagram of an embodiment showing an example of the circuit configuration of the instruction fetch unit 6 of FIG. In FIG. 3, the instruction fetch circuit according to the present invention has a plurality of buffer series 2-1 to 2-n in parallel, and each buffer series is given an ID as an identifier. The instruction fetch circuit of this embodiment takes as an example the case of being composed of three buffer sequences A, B and C, and each buffer sequence is identified by the sequence A ID = 00 sequence B ID = 01 sequence C ID = 10. To be done.

One of these three buffer sequences A to C
One is used for fetching the instruction stream (instruction string) currently executed in the instruction execution pipeline 7. The other two buffer series fetch the branch instruction stream in response to an instruction that changes the currently executed instruction stream, such as a branch instruction. The target address for fetching the instruction stream may be obtained from the operand address generation stage of the instruction execution pipeline 7 or may be obtained from the branch history.

Each of the three buffer sequences A to C is
It has a buffer with a capacity larger than the amount of one instruction fetch. In this embodiment, the amount of instructions sent from the instruction cache 5 for one instruction fetch request is 8 bytes. Therefore, each of the buffer series A to C has four stages of 8-byte unit instruction buffer registers in series. For example, the buffer series A is IBRA0, IBRA1, IBRA2, and IBRA3.
It shows with.

As a result, each of the buffer series A to C can hold fetch data corresponding to a plurality of instruction fetches, that is, at least one instruction stream. The instruction string fetched from the instruction cache 5 to the buffer series A is initially set in the instruction buffer register IBRA3. Therefore, for fetching a subsequent instruction, the data in the instruction buffer register IBRA3 is simultaneously shifted toward the instruction buffer register IBRA2 in the next stage before the subsequent instruction is set in the instruction buffer register IBRA3. This shift operation is called bubble up.

The bubble-up shift amount in this embodiment is 8 bytes, which is the fetch amount for one time. As described above, each of the buffer series A to C has an instruction buffer composed of a plurality of stages of instruction buffer registers in series, and sequentially shifts the instruction sequence sent to itself by performing the shift operation of the instruction buffer.

Further, each buffer series A to C presents an instruction presenting circuit 11A, 1 for presenting the head instruction of its own instruction queue.
It is equipped with 1B and 11C. The instruction fetch control unit 1 selects the instruction execution pipeline 7 from the instructions presented by the instruction presentation circuits 11A to 11C of the buffer series A to C.
Select the series that should be input to.

In order to recognize the position in the instruction buffer of the further presented instruction, the instruction buffer register IB
RA0 to A3, B0 to B3, and C0 to C3 have addresses 00 to 10 (16) in units of half words, which is an instruction size, as in the instruction buffer registers IBR0 to 3 representatively shown in FIG.
). Referring again to FIG. 3, each of the buffer sequences A to C has an NSI counter 12A, 12B,
12C has a pointer indicated by the contents of 12C, and the instruction buffer registers IBRA0 to A3, B0 to B3, and C0 to C of the instruction stream presented by the own sequence by this pointer.
3 indicates the head position.

The NSI counters 12A to 12C are the N of FIG.
As shown in SI counter 12, bit E and bit 0
3 to 5 bits, bits 0 to 3 represent addresses 00 to 10 on the instruction buffer registers IBR0 to 3, and bit E represents whether the instruction sequence in the local sequence instruction buffer is valid or invalid. When the instruction presenting circuit 11 presents the next instruction, the NSI counter 12 is extracted from the address obtained by adding the size ILC of the currently presented instruction generated in the decoder 13.

The generation of the instruction size ILC by the decoder 13 is obtained by decoding the operation code part indicated by the diagonal lines of the present presentation instruction stored in the instruction presentation circuit 11.
NSI counter 12 that obtains a pointer indicating the instruction start position
Will be updated in the following two occasions. (1) When the instruction fetch control unit 1 issues a next instruction presentation request signal, the NSI counter 12 is incremented by the size ILC of the currently presented instruction.

(2) When bubble up is performed, the NSI counter 12 corresponds to the shift amount of 8 bytes in this circuit.
Is decremented by 4. As shown in FIG. 3, each of the buffer series A to C has the NSN counter 12 of
By having the counters 12A to 12C, each buffer series A to C presents an instruction, and the instruction fetch control unit 1 grasps the instruction amount in each instruction buffer of each series and assigns an ID for each series to give an instruction. The fetch request is sent to the instruction cache 5.

Next, the timing of bubble-up will be described with reference to the instruction fetch pipeline shown in FIG. In the I state of the instruction fetch pipeline 8 in FIG. 5, the priority of the instruction fetch request sent from the instruction fetch control unit 1 to the storage control unit 3 is determined and notified to the instruction fetch control unit 1.

The instruction fetch controller 1 confirms that there is no instruction fetch prohibition condition, sends a signal (IF REQ VAL) indicating the validity of the instruction fetch request and the instruction fetch address to the memory controller 3, and the memory controller 3 3 P, T,
The instruction fetch pipeline 8 consisting of B and R is activated.
The IT state corresponds to address conversion in the storage control unit 3. In the IB state, the storage control unit 3 causes the instruction cache 5
To access and fetch the fetched instruction to the instruction buffer circuit 2
Sent to. In the IR state, the validity of fetch data is checked, the instruction decode stage of the instruction execution pipeline 7 is validated, and an instruction is input.

The signal (IF REQVAL) indicating the validity of the instruction fetch request transmitted in the I state becomes a tag and flows through the instruction fetch pipeline 8 as shown in FIG. In addition, a signal (IF
At the same time when the REQ VAL) is sent, a series ID signal (IF REQ ID) indicating which series of instruction stream fetch request this signal is sent,
Similarly, it flows through the instruction fetch pipeline 8.

The storage controller 3 holds the sequence ID signal (IF REQ ID) from the instruction fetch controller 1 and
In the state, the sequence ID signal (BREQ ID) is returned to the instruction fetch control unit 1 together with the instruction fetch data and the clock enable. Therefore, the fetched data is set in the instruction buffer of the series selected by the series ID signal.

The bubble up is performed in the instruction buffer of the sequence selected by the sequence ID signal (BREQ ID) at the timing of the signal (IB REL) indicating the exit from the IB state. In the above embodiment, the branch prediction control is scheduled and the instruction buffer circuit 2 is provided with three instruction buffer series A to C. However, the number of instruction buffer series is required. It can be appropriately determined depending on the situation.

[0035]

As described above, according to the present invention, 1
Has a capacity that is an integer multiple of the storage capacity required for one instruction fetch
Instructions by providing a plurality series buffers in parallel, it is possible to prepare a plurality of instruction streams to the instruction execution pipeline to fetch sequentially until the multiple instruction stream buffer is saturated, the predicted branch control such that Even if the stream is changed, the continuously changed instruction stream can be injected into the pipeline,
Moreover, since the sequence of each instruction buffer is identified by the identifier, there is an effect that necessary instructions can be input to the pipeline in a short time from the instruction stream that is sequentially configured.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a circuit diagram of an embodiment of an instruction buffer circuit of the present invention.

FIG. 4 is a circuit diagram of an embodiment in which a system of an instruction buffer circuit of the present invention is taken out and described in detail.

FIG. 5 is an operation time chart of the instruction fetch pipeline showing the valve up timing in the instruction buffer circuit of the present invention.

[Explanation of symbols]

 1: Instruction fetch control unit 2: Instruction buffer circuit 2-1 to 2-n: Instruction buffer 3: Storage control device (storage control unit) 4: Instruction execution unit 5: Instruction cache 6: Instruction fetch unit 7: Instruction execution pipe Line 8: Instruction fetch pipeline 10: CPU device 11, 11A to 11c: Instruction presentation circuit 12, 12A to 12C: NSI counter 13: Decoder

Claims (1)

(57) [Claims] 1. An instruction fetch control unit (1) fetches an instruction from a storage controller (3), stores it in an instruction buffer circuit (2), and then supplies it to an instruction execution pipeline of an instruction execution unit (4). In the instruction fetch circuit to be executed, multiple buffer registers are configured in series to duplicate.
Store a number of instructions and each time a new instruction is fetched
The instruction stored in is shifted to the buffer register in the next stage.
Of multiple buffers to be stored in parallel.
Command buffers (2-1 to 2-n) and instructions stored in the instruction buffers (2-1 to 2-n).
Command buffer to specify the beginning of the command stream
A pointer (12) provided for each (2-1 to 2-n) and an instruction stored in the instruction buffer (2-1 to 2-n)
Pointed to by the pointer (12) in the stream
The instruction buffer (2-1
To 2-n) instructions presented circuit provided for each (11), among the instructions presented by the instruction presented circuit (11)
The instruction is selected by selecting an instruction determined by an identifier (ID).
Instruction fetch control unit (1) supplied to the execution pipeline
Instruction fetch circuit comprising the and.