JP2676487B2 - Discharge display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discharge display device using a memory electrode.

[0002]

2. Description of the Related Art A conventional discharge display device (PDP:
Some examples of plasma display panels will be described.

[Prior Art 1] (FIG. 18) First, with reference to FIG. 18, the present applicant filed Japanese Patent Application No. 4-746.
A discharge display device (memory electrode type PDP) (conventional example 1) proposed in No. 03 and Japanese Patent Application No. 4-300266 will be described. Front glass plate and rear glass plate 1 not shown
The following structure is housed in a tube constructed by sealing the periphery of 1 with frit glass, and after evacuating the tube, discharge of helium, neon, argon, xenon, etc. or their mixed gas etc. A gas for use is enclosed.

This discharge display device has a plurality of through holes arranged in an XY matrix, and the entire surface of each of the through holes is an insulating layer 3.
a sheet-shaped memory electrodes 3 covered with a and 4a,
4, the two memory electrodes 3 and 4 are superposed so that their respective through holes communicate with each other to form a discharge cell,
The stripe-shaped first and second address electrodes (one and the other of which are anode and cathode, respectively) 1 and 2 arranged in parallel with each other and arranged in a plurality of XY matrixes intersect each other. A pair of two memory electrodes 3, which are arranged at a predetermined interval and are overlapped between the plurality of first and second address electrodes 1 and 2 so that each intersection corresponds to each discharge cell, 4 is placed and enclosed in a tube containing discharge gas. A predetermined voltage is applied between the selected first and second address electrodes 1 and 2 of the plurality of first and second address electrodes 1 and 2, and a discharge cell (discharge space) located at the intersection thereof. A discharge is generated therein, and a predetermined AC voltage is applied between the pair of two memory electrodes 3 and 4 so that the discharge can be maintained.

The operation of this discharge display device will be described below. First, when the discharge between the first address electrode (anode) 1 and the second address electrode (cathode) 2 excites a discharge due to the writing of an image signal in the discharge cell, ions, electrons, etc. in the tube body are excited. Charged particles are drawn into the respective through holes according to the polarities of the two memory electrodes 3 and 4 due to the applied AC voltage, and the insulating layer 3 on the inner surface thereof is drawn.
wall charges are accumulated on the surfaces of a and 4a, and then the two memory electrodes 3 due to the applied AC voltage,
When the polarity of 4 is reversed, the potential difference between them becomes high because the voltage based on wall charge is superimposed on the applied AC voltage, and therefore discharge occurs between the through holes of the two memory electrodes 3 and 4, and By repeating the phenomenon, the discharge in the discharge cell formed by each through hole due to the writing of the signal in the discharge cell is maintained. In short, the auxiliary discharge selectively generated at the intersection of the first and second address electrodes is
The memory electrodes 3 and 4 are moved to a pair of two memory electrodes 3 and continuously emit light only by sustaining pulses.

According to the discharge display device of FIG. 18, the plurality of first and second address electrodes (anode and cathode) 1 and 2 are insulated on each electrode like the electrodes of the conventional DC type PDP. Since it is not necessary to form a layer and discharge is generated in the through holes provided in the memory electrodes 3 and 4, basically no partition wall (barrier rib) is required, and the drive circuit is a DC type PD.
Since a circuit similar to P can be used, the structure is simple, mass productivity is excellent, high resolution and large size are easy, driving is simple, the driving circuit is simple, and the cost is easy.

Conventional Example 2 (FIG. 19) Next, a conventional discharge display device (three-electrode surface discharge PDP) (Conventional example 2) will be described with reference to FIG. The following structures are housed in a tube body formed by sealing the front glass plate and the rear glass plate 11 (not shown) with frit glass, and the inside of the tube is evacuated to helium, neon, or argon. , A discharge gas (gas) such as xenon or a mixed gas thereof.

On the rear glass plate 11, a plurality of sets of memory electrodes (X1 electrodes) 2 each having a stripe shape as a pair of memory electrodes and memory electrodes (X2 electrodes) 2'also functioning as address electrodes are arranged in parallel with each other. An insulating layer 9 is deposited on the entire surface of the rear glass plate 11 including the plurality of sets of X1 electrodes 2 and X2 electrodes 2'which are arranged in parallel with each other. A plurality of partition walls 6 are provided on the insulating layer 9 so as to be orthogonal to the plurality of sets of memory electrodes (X2 electrodes) 2 and the memory electrodes (X2 electrodes) 2 ', and a plurality of sets of partition walls 6 are provided on each partition wall 6. Orthogonal to the X2 electrode 2 and the X2 electrode 2 ',
A plurality of stripe-shaped address electrodes (electrodes Y) 1 are arranged so as to be parallel to each other.

The operation of this discharge display device will be described below. First, when the discharge between the address electrode (Y electrode) 1 and the address electrode (X2 electrode) 2'is excited by the writing of the image signal in the discharge cell, the electric charge generated at this time is stored in the memory electrode 2, 2'is accumulated as so-called wall charges on the insulating layer 9. In short, the address discharge is transferred to the memory discharge, and the memory discharge is continued.

[Conventional Example] (FIG. 20) Next, referring to FIG. 20, a conventional discharge display device (Townsend discharge pulse memory type PDP) (JP-A-61-2)
Japanese Unexamined Patent Application Publication No. 60-114078> (Japanese Patent Application No. 60-114078)) (conventional example 3) will be described. This divides the discharge space into two parts and causes an address discharge (auxiliary discharge) with a short discharge gap at the cell lower part that is unrelated to the display, and transfers the address discharge to a memory discharge (display discharge) having a relatively long discharge gap. The light emitting efficiency is improved.

The following structures are housed in a tube constructed by sealing the peripheries of the front glass plate 12 and the back glass plate 11 with frit glass, and the inside of the tube is evacuated and then helium, neon, and argon are supplied. , A discharge gas (gas) such as xenon or a mixed gas thereof.

A resistance layer 15 is deposited on the rear glass plate 11, a spacer 8f is deposited thereon, and an auxiliary discharge is formed so as to penetrate through the spacers 8b to 8e which are sequentially laminated from the upper portion to the lower portion. On the spacer 8f which is the bottom of the space 10 ', a plurality of stripe-shaped address electrodes (cathodes) 13 arranged in parallel with each other at a predetermined interval are adhered and formed. The resistance layer 15 is connected to the cathode 13 in series. Also, the spacer 8b in the auxiliary discharge space 10 '
On the lower surface of the, so as to intersect with the plurality of cathodes 13,
A plurality of (address electrodes) auxiliary anodes 14 are deposited and formed in parallel with each other at a predetermined interval.

Above the spacer 8b, spacers 8b-8
A spacer 8a thicker than f is formed by deposition, a display discharge space 10 communicating with the auxiliary discharge space 10 'is provided in the spacer 8a, and a phosphor layer 7 is formed by deposition on the inner wall of the display discharge space 10. Has been done. And the spacer 8a
A front glass plate 12 is provided so as to face the upper surface of the front glass plate 12, and a transparent display anode 5 is adhered and formed on the entire lower surface of the front glass plate 12.

Next, the operation of the discharge display device of Conventional Example 3 will be described. When a predetermined DC voltage is applied between the auxiliary anode 14 and the cathode 13 selected according to the image signal in the auxiliary anode 14 and the cathode 13, an address discharge is generated in the auxiliary discharge space 10 '. After that, the discharge path is transferred between the display anode 5 and the cathode 13 by applying a voltage to the display anode 5.

In this case, the address discharge has only the auxiliary discharge function for exciting the memory discharge and has no memory function. The memory function employs a so-called pulse memory system in which a very high voltage, for example, a voltage of 500 V or more and a pulse voltage of 0.5 μsec or less is intermittently applied to the display anode 5. Therefore, the driving circuit in this case is extremely complicated and expensive.

[0016]

When the memory electrode type discharge display device of the conventional example 1 described in FIG. 18 is provided with a phosphor layer of three primary colors in its necessary portion to form a color discharge display device, a fluorescent display device is used. It is necessary to improve the luminous efficiency and brightness of the body layer and the contrast of the luminous display.

Not only in PDPs but also in gas discharge tubes, like a fluorescent lamp, the length of the discharge path of the discharge space is increased, and a phosphor layer is formed by deposition on a portion close to the discharge space. Ultraviolet rays are efficiently generated from the positive column generated in the discharge space, and the ultraviolet rays are efficiently irradiated to the phosphor layer, so that highly efficient and high-luminance light emission can be realized.

However, in the discharge display device of Conventional Example 1, if the discharge path is lengthened, the discharge voltage must be increased, which causes a problem in driving.

Further, in the memory electrode type discharge display device of the conventional example 1, as in the case of the AC type PDP, so-called reset discharge for returning the screen by the memory discharge to the initial state and preparing to write the next screen is performed in both memories. It is carried out by once causing a full discharge between the electrodes, and as long as this memory discharge is the main light source of light emission, improvement in contrast cannot be expected so much.

Further, in the memory electrode type discharge display device of Conventional Example 1, since the memory electrode is provided between the pair of address electrodes forming the XY matrix, the distance between the pair of address electrodes, that is, the anode and the cathode is Since it is defined by the thickness of the memory electrode, it is difficult to set the optimal inter-electrode distance for address discharge. Further, the potential of the memory electrode acts to prevent the address discharge, so that the voltage of the address discharge tends to increase. This tendency becomes more remarkable as the diameter of the hole of the memory electrode becomes smaller,
This has been an obstacle to improving the resolution.

Further, as an effective means for increasing the efficiency of the discharge tube, there is a case where the diameter of the hole of the memory electrode is made as small as possible and the hollow effect is utilized. In the device, as the diameter of the hole becomes smaller, the address voltage becomes higher, and the efficiency cannot be increased effectively.

Furthermore, in the conventional memory electrode type discharge display device of the first example, the holes of the two memory electrodes have to correspond to each other in a one-to-one manner, and it is difficult to position them.

In the three-electrode surface discharge type discharge display device (PDP) of the conventional example 2 described in FIG. 19, since the memory discharge is performed between the pair of memory electrodes arranged in close proximity to each other, a long discharge path is provided. Therefore, it is impossible to improve the luminous efficiency and the brightness. In the three-electrode surface discharge type discharge display device, the so-called AC type PDP and the memory electrode type discharge display device of the conventional example 1 described above are used to return the screen by the memory discharge to the initial state and prepare to write the next screen. The reset discharge is generated by temporarily causing the entire surface discharge between both memory electrodes. As long as this memory discharge is the main light source of light emission, improvement in contrast cannot be expected so much.

In the Townsend discharge pulse memory type discharge display device (PDP) of the conventional example 3 described with reference to FIG. 20, the address discharge has only an auxiliary discharge function for exciting the memory discharge and has no memory function, and the memory function is displayed. The drive circuit is complicated because a pulse memory method is used in which a pulse with a very high voltage (eg, 500 V or more) and an extremely short pulse width (eg, 0.5 μsec or less) is applied to the anode. Get expensive.

In view of the above points, the first object of the present invention is to
It is possible to realize a high-luminance and high-efficiency with a simple structure and circuit, and to provide a discharge display device capable of selecting an optimum voltage without interfering with each other due to the voltage relationship between the address discharge and the memory electrode. It is a proposal.

A second object of the present invention is to provide a memory discharge and
The main discharge, that is, the discharge that contributes to the light emission display can be separated by a simple structure and driving method, thereby proposing a discharge display device that can improve the contrast and the brightness and the light emission efficiency. Is what you are trying to do.

[0027]

The first aspect of the present invention, as shown in FIGS. 1 and 2, includes a plurality of first and second addresses arranged in close proximity so as to intersect with each other through a partition wall 6. The electrodes 1 and 2 and a plurality of through holes are provided, and memory electrodes 3 and 4 each having an entire surface covered with insulating layers 3a and 4a (two memory electrodes 3 and 4 arranged in close proximity)
And a plurality of first and second address electrodes 1 and 2 and memory electrodes 3 and 4 are stacked and enclosed in a tube containing discharge gas. .

In the second aspect of the present invention, as shown in FIGS. 8 and 9, a plurality of first and second address electrodes 1 and 2 are arranged in close proximity so as to intersect each other with a partition wall 6 interposed therebetween.
And a plurality of through holes are provided, and the entire surface thereof is covered with an insulating layer. The memory electrodes 3 and 4 (two memory electrodes 3 and 4 arranged close to each other) and the memory electrodes 3 and 4 are formed. It has a plurality of through holes corresponding to the plurality of through holes, and a spacer 8 having a phosphor layer 7 adhered and formed on the inner walls of the plurality of through holes and a common electrode 5, respectively. The first and second address electrodes 1 and 2, the memory electrode 3,
4, a spacer 8 and a common electrode 5 are sequentially laminated and enclosed in a tube containing a discharge gas.

As shown in FIGS. 12 and 13, the third aspect of the present invention includes a plurality of first and second address electrodes 1 and 2 which are arranged in close proximity so as to intersect each other through a partition wall 6.
And a plurality of through holes are provided, and the entire surface thereof is covered with an insulating layer. The memory electrodes 3 and 4 (two memory electrodes 3 and 4 arranged close to each other) and the memory electrodes 3 and 4 are formed. A plurality of through holes respectively corresponding to the plurality of through holes, and a common electrode 5 and a spacer 8 having a phosphor layer 7 adhered and formed on a surface opposite to the memory electrodes 3 and 4. The plurality of first and second address electrodes 1, 2, the memory electrodes 3, 4, the spacer 8 and the common electrode 5 are sequentially stacked and enclosed in a tube containing discharge gas. It is a discharge display device.

The fourth aspect of the present invention is the discharge display device according to the first, second or third aspect of the present invention, which comprises a plurality of first and second address electrodes 1 and 2 as shown in FIGS. A plurality of through holes of the memory electrodes 3 and 4 are configured to face each of the configured lattice holes.

The fifth aspect of the present invention is the discharge display device according to the first, second, third or fourth aspect of the present invention, as shown in FIG.
The memory electrodes 3 and 4 are used as the partition walls 6, and a plurality of first and second address electrodes 1 and 2 are deposited and formed on the insulating layers on both surfaces thereof.

The sixth aspect of the present invention, as shown in FIGS. 14 and 15, also serves as the first memory electrode 2 and the second memory electrode, which are formed on the insulating layer 9 and are arranged close to each other. A plurality of sets of second address electrodes 2 ', a plurality of first address electrodes 1 intersecting a plurality of second address electrodes 2'through insulating layers 9 and partition walls 6, and a plurality of first and second address electrodes 1'. A spacer 8 having a plurality of through holes corresponding to the plurality of lattice holes formed by the second address electrodes 1 and 2, and a phosphor layer 7 is formed on the inner wall of each of the plurality of through holes. When,
A first and a second memory electrode 2 having a common electrode 5 and deposited on an insulating layer 9 and arranged in close proximity to each other;
The discharge display device is characterized in that a plurality of sets 2 ', a plurality of first address electrodes 1, a spacer 8 and a common electrode 5 are sequentially laminated and enclosed in a tube containing discharge gas.

[0033]

The operation of the first aspect of the present invention will be described. Of the plurality of first and second address electrodes 1 and 2, a DC voltage sufficient for discharging is applied between the first and second address electrodes 1 and 2 selected according to the image signal, and the discharge space 10 The interior is filled with ions, electrons or metastable atoms, and the potential of the discharge space in the plasma state is substantially the discharge sustaining voltage with respect to the electrode of the first and second address electrodes 1 and 2 which is the cathode. In such a state, the potential of each of the memory electrodes 3 and 4 is maintained higher than the plasma potential, or
The polarity and the amount of charges accumulated on the surfaces of the insulating layers 3a and 4a of the memory electrodes 3 and 4 vary depending on whether they are kept low. That is, during the address discharge, the memory electrodes 3, 4 are
When the potential of the memory electrode 3 is kept high, negative space charges, that is, electrons, and when it is lowered, positive space charges, that is, ions are attracted to the surfaces of the insulating layers 3a and 4a of the memory electrodes 3 and 4, respectively. It is stored as an electric charge. The amount of wall charges accumulated depends on the difference between the potential of the memory electrodes 3 and 4 and the plasma potential, the dielectric constant of the insulating layers 3a and 4a, the thickness, and the like.

Therefore, the first and second address electrodes 1,
In order to store the wall charges due to the address discharge of No. 2 in the memory electrodes 3 and 4 as position information based on the image signal,
For example, the potential of one of the two memory electrodes 3 and 4 during address discharge may be kept high and the potential of the other may be kept low. That is, since the wall charge is formed on the pixel where the address discharge occurs, that is, on the wall surface of the discharge space 10, and the wall charge is not formed on the pixel where the address discharge does not occur, that is, the discharge space 10, the memory electrode is formed after the address period ends. By applying the 3 and 4 sustain pulses, an image can be displayed, and the display becomes a memory display until the next address discharge.
If the potentials of the memory electrodes 3 and 4 are both set to the same potential, for example, the plasma potential, during the address discharge period, since the potential difference between the two is 0, the existing wall charges are erased by the space charges. Even with such a method, image information can be accumulated on the memory electrodes 3 and 4 as a wall charge distribution state.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 (FIGS. 1 to 4) First, Example 1 of the present invention will be described with reference to FIGS. 1 and 2 showing a perspective view and a sectional view of a discharge display device. This discharge display device includes a front glass plate 12 and a rear glass plate 11.
The following structure is housed in a tube constructed by sealing the periphery of with frit glass, and after the tube is evacuated, a discharge gas such as helium, neon, argon, xenon, or a mixed gas of these is discharged. (Gas) (200 torr
˜400 torr) is enclosed in the PDP.

On the rear glass plate 11, a plurality of stripe-shaped address electrodes (X
Electrode 2 is deposited. The deposition can be easily realized by a thick film technique such as a screen printing method or a thin film technique such as a photo process. A plurality of partition walls (consisting of insulators) 6 are formed on the rear glass plate 11 and the address electrodes 2 so as to be substantially orthogonal to the plurality of address electrodes 2 and arranged in parallel at regular intervals. To do. This plurality of partition walls 6
Is obtained by repeating screen printing to obtain a product having a predetermined height. A plurality of stripe-shaped address electrodes (Y electrodes) 1 are formed on the plurality of barrier ribs 6, respectively. The deposition method is the same as that of the address electrode 2. Thus, the plurality of address electrodes 1 and 2 are arranged at a predetermined interval so that they are substantially perpendicular to each other.

The thickness of the partition wall 6 is optimally set in consideration of gas pressure, gas composition, pixel pitch, etc., but generally 80 μm.
It is about 200 μm. The partition wall 6 may be formed in a grid shape in order to surely avoid crosstalk between adjacent pixels.

Each of the plurality of address electrodes 1 and 2 may be an anode or a cathode. However, since it is necessary to generate the discharge from one side of the plurality of barrier ribs 6, the plurality of address electrodes 1 arranged on the upper side of the plurality of barrier ribs 6 are correspondingly covered with an insulating layer on one side. May be.

Reference numerals 3 and 4 respectively denote a pair of grid-shaped memory electrodes, the entire surfaces of which are covered with insulating layers 3a and 4a. The two memory electrodes 3 and 4 are conductive layers having a plurality of rectangular through holes (lattice holes) arranged in a matrix, that is, a plate of a metal such as stainless steel, aluminum, nickel or a metal alloy. It is composed of a mesh-shaped conductive plate formed by etching or the like, and its entire surface is applied by, for example, spraying, dipping or the like of a paste of glass powder, and then baked at a high temperature to form the insulating layers 3a and 4a. Form. The insulating layers 3a and 4a may be formed by oxidizing the surfaces of the memory electrodes 3 and 4 which are made of the above metal or alloy.

The shape and the facing position of these two memory electrodes 3 and 4 are set so that each grid corresponds to the address electrodes 1 and 2. A front glass plate 12 is arranged on the upper memory electrode 3. The shape of the through holes of the two memory electrodes 3 and 4 is not limited to a square or a rectangle, but may be a circle or an ellipse.

Between the glass plates 11 and 12, a square or rectangular hole formed by intersecting a plurality of address electrodes 1 and 2 and holes of the two memory electrodes 3 and 4 communicate with each other to form a discharge space 10. Alignment is performed as described above. Then, the phosphor layer 7 is adhered to the portion of the front glass plate 12 corresponding to each discharge space 10. The phosphor layer 7 is a monochromatic phosphor or red, green and blue phosphors sequentially and repeatedly arranged in the horizontal and / or vertical directions.

Next, the outline of the operation of the discharge display device according to the first embodiment will be described. Of the plurality of first and second address electrodes 1 and 2, a DC voltage sufficient for discharging is applied between the first and second address electrodes 1 and 2 selected according to the image signal, and the discharge space 10 The interior is filled with ions, electrons, or metastable atoms, and the potential of the discharge space in the plasma state is approximately the discharge sustaining voltage with respect to the cathode of the first and second address electrodes 1 and 2. In such a state, the electric potentials of the memory electrodes 3 and 4 are accumulated on the surfaces of the insulating layers 3a and 4a of the memory electrodes 3 and 4 depending on whether the electric potentials of the memory electrodes 3 and 4 are maintained higher or lower than the plasma potential. The polarity and amount of the charged charge will change. That is, during address discharge,
When the potentials of the memory electrodes 3 and 4 are maintained high, negative space charges, that is, electrons, and when lowered, positive space charges, that is, ions, are generated, and the insulating layer 3 of the memory electrodes 3 and 4 respectively.
They are attracted to the surfaces of a and 4a and are accumulated as wall charges. The amount of wall charges accumulated depends on the difference between the potential of the memory electrodes 3 and 4 and the plasma potential, the dielectric constant of the insulating layers 3a and 4a, the thickness, and the like.

Therefore, the first and second address electrodes 1,
In order to store the wall charges due to the address discharge of No. 2 in the memory electrodes 3 and 4 as position information based on the image signal,
For example, the potential of one of the two memory electrodes 3 and 4 during address discharge may be kept high and the potential of the other may be kept low. That is, since the wall charge is formed on the pixel where the address discharge occurs, that is, on the wall surface of the discharge space 10, and the wall charge is not formed on the pixel where the address discharge does not occur, that is, the discharge space 10, the memory electrode is formed after the address period ends. By applying the discharge sustaining pulse to 3 and 4, image display can be performed,
Until the next address discharge, the display becomes the memory display. When the potentials of the memory electrodes 3 and 4 are both set to the same potential, for example, the plasma potential, during the address discharge period,
Since the potential difference between the two is 0, the existing wall charges are erased by the space charges. Even with such a method, image information can be accumulated on the memory electrodes 3 and 4 as a wall charge distribution state.

Next, the operation of the discharge display device according to the first embodiment will be described in detail with reference to FIGS. 3 and 4. First, the driving method shown in FIG. 3 will be described. It is premised that there is no wall charge on the surface of the insulating layers 3a, 4a of the respective lattice holes of the memory electrodes 3, 4, and when driving, an erasing discharge is performed before the application of an address signal, so that all discharge cells on the screen or The wall charges of all discharge cells on the line are erased. The specific method of the wall charge is to apply a sufficient voltage between the memory electrodes 3 and 4 in the state where no signal is applied to the address electrodes 1 and 2 to discharge all discharge cells on the screen or all discharges on lines. A discharge is generated in the cell, and immediately thereafter, the potentials of the memory electrodes 3 and 4 are both maintained at the same voltage as the discharge space potential. As a result, the wall charges disappear and new wall charges are not accumulated.

With no wall charge, as shown in FIGS. 3C and 3D, the discharge space potential (eg, 100) is applied to the memory electrode 3.
V), for example, a voltage of 150 V, and a voltage lower than the discharge space potential, for example, 50 V, is applied to the memory electrode 4 as shown in FIG. A positive voltage of 200 V, which is a sufficient voltage for address discharge, is applied, and a ground potential is applied to the address electrode 2 as shown in FIG. 3B. Negative charges generated by the address discharge are charged as wall charges on the insulating layer 3a above the memory electrode 3, and positive charges are charged as wall charges on the insulating layer 4a of the memory electrode 4. afterwards,
The voltage on the address electrode 1 drops to about 100V, as shown in FIG. 3A. Since the address electrode 2 is held at a bias voltage at which unnecessary discharge does not occur, for example, 100 V, the address signal voltage to another cell (pixel) (discharge space) is changed to another cell (pixel) (discharge space). Address X
Even when applied to the electrode (anode) 1, the wall charges are maintained as they are.

The address discharge because the address electrodes 1 and 2 are both exposed to the gas space, conventional DC type PDP
Line-sequential driving is performed in the same manner as. As shown in FIGS. 3C and 3D, during the address period, a voltage higher than the discharge space potential (for example, about 100V) of 150V is applied to the memory electrode 3, and a voltage lower than the discharge space potential of 50V is applied to the memory electrode 4. Since it is applied, it does not affect the start of the address discharge. When the address discharge occurs in this state, the generated charged particles are charged on the insulating layers 3a and 4a on the memory electrodes 3 and 4 to form wall charges.

Due to the potential distribution of each electrode described above, a negative charge is formed on the memory electrode 3 and a positive wall charge is formed on the memory electrode 4. This address operation is performed line-sequentially, for example, from the top line to the bottom line.

In the memory period, as shown in FIGS. 3C and 3D, the maximum voltage of the memory electrodes 3 and 4 is 150, respectively.
AC voltage (10 V
A voltage in which an AC voltage with an amplitude of 50V is superimposed on a DC voltage of 0V) is applied as a sustaining pulse, and a cell in which an electric field due to the accumulation of wall charges generated by the address discharge is superimposed on the sustaining pulse is discharged and addressed. Without the accumulation of wall charges, the cells are not discharged. Thus, the screen continues to be discharged for this period according to the image information.

Next, the driving method of FIG. 4 will be described.
In this driving method, it is premised that the wall charges are uniformly accumulated on the surfaces of the insulating layers 3a, 4a of the lattice holes of the memory electrodes 3, 4, so that the memory electrodes are applied before the address signal is applied during driving. By applying a reset pulse to the memory electrodes 3 and 4, discharge is caused in all discharge cells on the screen of the memory electrodes 3 and 4 or in all discharge cells on a line , and the surfaces of the insulating layers 3a and 4a in each discharge cell. A wall charge is formed on.
A specific method of forming wall charges by applying the reset pulse is to apply a reset pulse voltage sufficient to start a discharge between the memory electrodes 3 and 4, and a period during which charged particles due to the reset discharge exist in the discharge cell. The voltage is maintained as it is, or each of the memory electrodes 3 and 4 is at least higher than the discharge space potential (for example, 150 V).
V) and a low voltage (for example, 50 V) are applied, the wall charges in each discharge cell are retained as they are. And
After a lapse of a predetermined time, after no charged particles are present, the discharge space potential is substantially equal to 10 in the memory electrodes 3 and 4.
When a voltage of 0 V is applied, the wall charges in each of the discharge cells are maintained as they are.

As shown in FIGS. 4C and 4D, the memory electrode 3,
4 are both held at about 100 V, negative wall charges are accumulated on the insulating layer 3a of the discharge space 10 of the memory electrode 3, and positive wall charges are accumulated on the insulating layer 4a of the discharge space 10 of the memory electrode 4. In this state, as shown in FIG. 4A, a positive voltage of 200 V, which is a sufficient voltage for address discharge, is applied to the address electrode 1 and a ground potential is applied to the address electrode 2 as shown in FIG. 4B. . The charged particles generated by this discharge are the insulating layers 3 of the memory electrodes 3 and 4.
By recombining with the wall charges on a and 4a, the wall charges can be extinguished. Thereafter, as shown in FIG. 4A, the voltage applied to the address electrode 1 drops to about 100V, but as shown in FIGS. 4C and 4D, the memory electrode poles 3 and 4 are held at the same bias voltage of about 100V, and the wall charge Therefore, the surface of the memory electrode 3 is at a lower voltage of 50 V, and the surface of the memory electrode 4 is at a higher voltage of about 150 V, so that the positive and negative charged particles in the discharged space are respectively stored in the memory electrodes 3, 4. And is recombined with the wall charges of the insulating layers 3a and 4a of the discharge spaces 10 of the memory electrodes 3 and 4, respectively. After that, the address signal sequentially moves to the next discharge space, but the voltage of both memory electrodes 3 and 4 is held in the same state during that time, so that wall charges of each discharge space are maintained unless new discharge occurs. The state of is maintained as it is.

When the sustaining pulse for memory discharge is applied between the memory electrodes 3 and 4 after the addressing of one screen is completed, the sustaining pulse is applied to the electric field due to the wall charge as in the normal operation of the AC PDP. The cells on which are overlapped are discharged, and the cells that are not addressed and have no wall charge accumulated are not discharged. That is, the charged particles generated by the address discharge are recombined with the wall charges on the insulating layers 3a and 4a of the memory electrodes 3 and 4 and disappear. The wall charges of the cells in which the address discharge has not occurred remain as they are.

Now, in the memory period in which the wall charges are formed in each cell according to the screen information in the address period, as shown in FIG.
As shown in D, the maximum voltage between the memory electrodes 3 and 4 is 1
An AC voltage of 50V and a minimum voltage of 50V (superimposed on a DC voltage of 100V) is applied as a sustaining pulse, but the discharge space where the electric field due to the wall charge is superimposed on the sustaining pulse depends on the presence or absence of the wall charge. Discharge, and the cells whose wall charges have been erased do not. Thus, according to the image information on the screen of the PDP, lighting and non-lighting continue during the memory period for each discharge space 10 corresponding to each pixel.

Second Embodiment (FIGS. 5 and 6) First, a second embodiment of the present invention will be described with reference to FIGS. 5 and 6 showing a perspective view and a sectional view of a discharge display device. Is a modified example of the first embodiment of FIGS. 1 and 2, and
The difference is that the diameter of the lattice holes of the two memory electrodes 3 and 4 is set to be smaller than the diameter of the lattice of the address electrodes 1 and 2. For one lattice hole (square, rectangle, circle, ellipse, etc.) formed of 1 and 2, each of the two memory electrodes 3 and 4 has a plurality of lattice holes, here 9 The individual is adapted to correspond.

When a large number of holes in the grid of the two memory electrodes 3 and 4 correspond to the holes of the grid composed of the plurality of address electrodes 1 and 2, a pair of 2 for the address electrodes 1 and 2 is formed. It is not necessary to align the memory electrodes 3 and 4 on one sheet. In this case, the lattice holes composed of the plurality of address electrodes 1 and 2 and the plurality of two memory electrodes 3 and 4 are formed.
To avoid moire fringes of the reproduced image due to the holes and the diameter differences in the lattice, the arrangement direction of the holes formed lattice of a plurality of address electrodes 1, a plurality of two memory electrodes 3,
It is possible to provide an angle difference of about 30 ° to 45 ° with the arrangement direction of the holes of the lattice of No. 4.

It is easy to set the diameter of the hole of the pair of two memory electrodes 3 and 4 to about 50 μm. However, in this case, due to the hollow effect, two holes from the cathode in the hole are formed. The secondary electron emission efficiency is increased, which lowers the discharge sustaining voltage and the consumption voltage.

As shown in FIG. 6, the phosphor layer 7 is adhered to the portion of the front glass plate 12 corresponding to the discharge space 10, but instead of or together with it, between the two memory electrodes 3 and 4. , Those having the same structure as the two memory electrodes 3 and 4 are laminated so that the holes of these three members are aligned, and the phosphor layer is formed on the inner wall of the hole (covered with the insulating layer) of the intermediate electrode. Can also be deposited. This phosphor layer 7
Are monochromatic phosphors or red, green and blue phosphors sequentially and repeatedly arranged in the horizontal and / or vertical directions.

The operation of the discharge display device of the second embodiment is similar to that of the first embodiment.

[Third Embodiment] (FIG. 7) Next, a third embodiment of the present invention will be described with reference to FIG. 7 showing a partition wall and address electrodes. The partition wall 6 in each of the first and second embodiments was composed of a plurality of stripe-shaped partition walls provided corresponding to the plurality of address electrodes 1. However, in FIG. 7, the partition wall 6 is formed in a grid shape and its lower surface is formed. Then, a plurality of address electrodes 2 are deposited on the upper surface, and a plurality of address electrodes 1 are deposited on the upper surface so that the address electrodes 1 and 2 are substantially orthogonal to each other. As the partition wall 6, in addition to constituting a whole as an insulator, the entire surface may be utilized memory electrodes coated with an insulating layer. In that case, in order to increase the breakdown voltage between the plurality of address electrodes 1 and 2, the insulating layer is made thicker than in the case of being used as a memory electrode.

In this case, the width of the plurality of address electrodes 1 and 2 can be made narrower than the width of the surface of the partition wall 6 on which the address electrodes 1 and 2 are formed, so that crosstalk between adjacent pixels can be avoided. Also, the plurality of address electrodes 1, 2
Is displaced in one direction in the width direction of the surface of the partition wall 6 on which the address electrodes 1 and 2 are formed, crosstalk between adjacent pixels becomes more difficult to occur.

[Embodiment 4] (FIGS. 8 to 11) FIGS. 8 and 9 are perspective views and sectional views of a discharge display device, respectively, and FIGS. 10 and 11 are timing charts and discharge paths, respectively. Example 4 of the present invention
Will be described.

First, the structure of the discharge display device according to the fourth embodiment will be described with reference to FIGS. This discharge display device is constructed by surrounding the front glass plate 12 and the rear glass plate 11 with frit glass, and the following structure is housed in the tube body and the tube body is evacuated and then helium or neon is applied. (Argon, Xenon, etc.) or a mixed gas thereof (discharge gas) (200 torr-400)
is a PDP in which a torr) is enclosed.

On the rear glass plate 11, a plurality of stripe-shaped address electrodes (X
Electrode 2 is deposited. The deposition can be easily realized by a thick film technique such as a screen printing method or a thin film technique such as a photo process. A plurality of stripe-shaped partition walls (consisting of insulators) 6 are arranged in parallel at regular intervals over the rear glass plate 11 and the address electrodes 2 so as to be substantially orthogonal to the plurality of address electrodes 2. Are formed. The plurality of partition walls 6 have a predetermined height by repeating screen printing. The height of the plurality of partition walls 6 is
The optimum value is selected depending on the gas pressure, gas composition, pixel pitch, and the like. A plurality of stripe-shaped address electrodes (Y electrodes) 1 are formed on the plurality of barrier ribs 6, respectively. The deposition method is the same as that of the address electrode 2. Thus,
The plurality of address electrodes 1 and 2 are arranged at predetermined intervals so that they are substantially perpendicular to each other.

The thickness of the partition wall 6 is optimally set in consideration of gas pressure, gas composition, pixel pitch, etc., but generally 80 μm.
It is about 200 μm. The partition wall 6 may be formed in a grid shape in order to surely avoid crosstalk between adjacent pixels.

Any of the plurality of address electrodes 1 and 2 may be an anode or a cathode. However, since it is necessary to generate the discharge from one side of the plurality of barrier ribs 6, the plurality of address electrodes 1 arranged above the plurality of barrier ribs 6 should be correspondingly displaced to one side of the barrier ribs 6. To

Reference numerals 3 and 4 respectively denote a pair of grid-shaped memory electrodes, the entire surfaces of which are covered with insulating layers 3a and 4a, respectively. The two memory electrodes 3 and 4 are formed by etching a conductive layer having a plurality of rectangular through holes arranged in a matrix, that is, a plate of a metal such as stainless steel, aluminum, nickel or a metal alloy thereof. A conductive plate in the form of a mesh, the entire surface of which is applied, for example, by spraying, dipping or the like of a paste of glass powder, which is then baked at high temperature to cover the insulating layers 3a, 4a. is there. Insulating layers 3a, 4a
May be formed by oxidizing the surfaces of the two memory electrodes 3 and 4 themselves made of the above metal or alloy.

The shape and facing position of these two memory electrodes 3 and 4 are set so that each grid corresponds to each grid formed by the address electrodes 1 and 2. A front glass plate 12 is arranged on the upper memory electrode 3. The shape of the lattice holes of the two memory electrodes 3 and 4 is not limited to square, rectangular, etc., and may be circular, elliptical, etc.

The lattice holes formed by the plurality of address electrodes 1 and 2 and the lattice holes of each of the two memory electrodes 3 and 4 are formed on the upper memory electrode 3 so that the lattice holes communicate with each other. The grid-shaped spacers 8 are arranged. Then, the phosphor layer 7 is adhered and formed on the wall surface of the lattice hole of the spacer 8. The spacer 8 may be formed on the lower surface of the front glass plate 12 by screen printing or the like, but may be an insulating plate etched, a metal plate molded, or the like. You can use what you have done.

The height of the spacer 8 is about 0.1 mm to 2.0 mm although its optimum value is selected depending on the driving conditions. The higher the height of the spacer 8, the higher the voltage applied to the display anode 5, which will be described later. However, when the height is usually about 1.5 mm, a positive column appears and the ultraviolet radiation becomes stronger and the brightness becomes higher.

On the lower surface of the front glass plate 12, a display anode 5 composed of a transparent conductive layer of tin oxide, indium tin oxide or the like.
Is arranged. This display anode 5 may be a mesh-shaped perforated metal plate other than a flat plate.

Between the glass plates 11 and 12, the lattice holes of the spacer 8, the lattice holes formed by the intersection of the plurality of address electrodes 1 and 2, and the holes of the two memory electrodes 3 and 4 communicate with each other to form a discharge space. Alignment is performed so that 10 is formed. The phosphor layer 7 is formed on the inner wall of the lattice hole of the spacer 8 by adhesion. The phosphor layer 7 is monochromatic phosphor or horizontal or / and repeated sequentially disposed a red vertical direction, Ru green and blue phosphors der.

Next, the operation of the discharge display device of the fourth embodiment will be described with reference to FIG. Before selectively generating an address discharge at a position corresponding to an image signal among the intersections between the plurality of address electrodes 1 and 2, FIGS.
As shown in, a voltage sufficient for discharging is applied between the two memory electrodes 3 and 4 to cause reset discharge, and the entire screen is once reset to the same state.

Then, while the space charge due to the reset discharge exists, as shown in FIG. 10C, a potential approximately midway between the potentials applied to the two memory electrodes 3 and 4 for the reset discharge (this is This is referred to as an intermediate potential), and the potentials of the two memory electrodes 3 and 4 are held at the same potential. Thus, the wall charges on the insulating layers 3a and 4a of the two memory electrodes 3 and 4 are all erased due to the space charges due to the reset discharge, and there is no wall charge over the entire screen, or An equivalent wall charge in which no potential difference is generated between the two memory electrodes 3 and 4 remains.

While the space charges due to the reset discharge are present, as shown in FIG. 10D, the potentials of the two memory electrodes 3 and 4 are set such that one is slightly higher than the intermediate potential and the other is intermediate. When each is held at a potential slightly lower than the potential, space charges due to the reset discharge are accumulated as wall charges on the inner wall surfaces of the lattice holes of the two memory electrodes 3 and 4, depending on their polarities, so that the entire screen is displayed. A uniform wall charge is formed over the entire area. As described above, the initial state for performing the selective address discharge according to the image is created, and the reset is completed.

Now, in order to selectively generate an address discharge at a position corresponding to an image signal among the intersections between the plurality of address electrodes 1 and 2, one of the address electrodes 1 and 2 is formed as shown in FIG.
As shown by 0A, a voltage according to the image signal is applied, and a scanning voltage is applied to the other in sequence, and a voltage sufficient for discharging is applied between the address electrodes 1 and 2. When this address discharge occurs, the discharge space 10 is filled with ions, electrons, or metastable atoms, and the potential of the discharge space 10 in the plasma state is substantially equal to that of the cathode , that is, the address electrode 1 or 2. The potential becomes the discharge sustaining voltage.

Under such a condition, the electric potentials of the two memory electrodes 3 and 4 are maintained higher or lower than the discharge space potential.
The polarities and amounts of the electric charges accumulated on the surfaces of the insulating layers 3a and 3b change. That is, if the potentials of the two memory electrodes 3 and 4 are maintained high during the address discharge, the negative space charges, that is, electrons, and if lowered, the positive space charges, that is, the ions, have the two memory electrodes. Three and four insulating layers 3a,
It is attracted to the surface of 4a and accumulated as wall charges. The amount of accumulated electric charges depends on the difference between the electric potentials of the two memory electrodes 3 and 4 and the plasma electric potential, the insulating layer 3a,
It depends on the dielectric constant and thickness of 4a.

It is assumed that the reset discharge described above causes no wall charge on the insulating layers 3a and 4a of the two memory electrodes 3 and 4. Therefore, in order to store the wall charges due to the address discharge in the two memory electrodes 3 and 4 as the information based on the image signal, during the address discharge,
It is understood that the potential of one of the two memory electrodes 3 and 4 is kept high and the potential of the other 4 is kept low. That is, since the wall charge is formed on the pixel where the address discharge is generated, that is, on the wall surface of the hole, and the wall charge is not formed where the address discharge is not generated, after the address period is completed, the two memory electrodes 3, 4 are discharged. An image can be displayed by applying the pulse shown in FIG. 10C or D to, and the display until the next address discharge becomes the memory display.

The above description of the operation is based on the case where the display anode 5 is not taken into consideration, and is the same as the operation of the conventional example 1 of FIG. Next, the operation will be described in consideration of the display anode 5.
As shown in FIG. 10E, during the reset period and the address period, the voltage of the display anode 5 is set to a low voltage that does not affect the address electrodes 1 and 2 and the two memory electrodes 3 and 4. Subsequently, when the address discharge period ends and the wall charge is selectively formed in each cell, the memory operation is started. At that time, as shown in FIG. 10E, the voltage of the display anode 5 is increased. . However, the display anode 5
Is applied to the two memory electrodes 3 and 4 so as not to cause a discharge unrelated to display.
From this state, selective memory discharge is started along the distribution of wall charges formed during the address discharge period.

The voltage applied to the display anode 5 (see FIG.
E) is the reset and address period as described above,
Although it differs depending on the memory period, the voltage difference depends on the structure of the cell (discharge space), gas pressure, and the like. However, the voltage of the difference is relatively low, and in some cases, it is possible to apply a constant DC voltage (bias voltage) to the display anode 5 during the reset, address and memory periods.

Next, referring to FIG. 11, the display anode 5
Will be described. The discharge space 10 in FIG. 11 shows a discharge space corresponding to one pixel on the screen. In this case, since the discharge space is filled with ionized charged particles and metastable atoms, even if the voltage of the display anode is low, the discharge space between the memory electrodes 3 and 4 on the low voltage side is low. Discharge occurs. In other words, the discharge current from the display anode 5 is added to the memory discharge current. Even if a new wall charge is formed and the half cycle of the memory discharge is stopped, the current is similarly supplied from the display anode 5 to the memory discharge which continues in the next half cycle. That is, while the memory discharge is continuing, the current from the display anode 5 is continuously supplied to the two memory electrodes 3 and 4 side. Furthermore, in other words, the discharge between the two memory electrodes 3 and 4 is drawn by the display anode 5 between the display anode 5 and the two memory electrodes 3 and 4. As shown in FIG. 11, this discharge is generated along the inner wall of the spacer 8 where the phosphor layer 7 is formed in the lattice holes, so that the ultraviolet rays generated by the discharge excite the phosphor layer 7 to emit light. Let Since no charged particles are present in the discharge space of the pixel in which the memory discharge is not performed, the discharge does not occur at a voltage of, for example, about 200 V to 300 V applied to the display anode 5.

[Fifth Embodiment] (FIGS. 12 and 13) Next, a fifth embodiment of the present invention will be described with reference to FIGS. 12 and 13 showing a sectional view of a discharge display device and a plan view of a state in which a front glass plate is removed. 8 will be described with reference to FIG. 8, parts corresponding to those in FIG. 8 and FIG. In the discharge display device according to the fifth embodiment, the spacer 8 is made thinner than the spacer 8 according to the fourth embodiment, and the grid-shaped display anode 5 is
This is a case where the upper surface of the spacer 8 facing the front glass plate 12 is adhered and formed, and the phosphor layer 7 is adhered and formed on a portion of the upper surface of the spacer 8 excluding the grid-shaped display anode 5. The discharge space 10 is located in the grid hole of the grid-shaped display anode 5. The other structure and operation are the same as those of the discharge display device of the fourth embodiment, and the duplicated description will be omitted.

[Sixth Embodiment] (FIGS. 14 to 17) Next, FIGS. 14 and 15 showing a perspective view and a sectional view of a discharge display device, and FIGS. 16 and 17 showing a timing chart and a discharge path, respectively. Example 6 of the present invention will be described with reference to FIG.

First, the structure of the discharge display device according to the sixth embodiment will be described with reference to FIGS. This discharge display device is constructed by surrounding the front glass plate 12 and the rear glass plate 11 with frit glass, and the following structure is housed in the tube body and the tube body is evacuated and then helium or neon is applied. , Argon, Xenon, etc., or mixed gas thereof (gas) for discharge (200 torr-4
00 torr) is enclosed in the PDP.

A set of memory electrodes (X1 electrodes) 2 and stripe-shaped memory electrodes (X2 electrodes) 2'each forming a pair and arranged in parallel with each other at a predetermined interval on the back glass plate 11 respectively. Are formed in parallel with each other with a predetermined interval therebetween. The deposition can be easily realized by a thick film technique such as a screen printing method or a thin film technique such as a photo process. An insulating layer 9 is formed on the entire surface of the back glass plate 11 and the memory electrodes 2 and 2 '. Similar to the AC type PDP, on the insulating layer 9,
A protective layer (not shown) such as MgO is deposited, and a plurality of stripe-shaped barrier ribs arranged in parallel at regular intervals so as to be substantially orthogonal to the plurality of memory electrodes 2 and 2 '. 6 (consisting of an insulator) is deposited. The plurality of partition walls 6 have a predetermined height by repeating screen printing. An optimum value is selected for the height of the plurality of partition walls 6 depending on the gas pressure, the gas composition, the pixel pitch, and the like. A plurality of stripe-shaped address electrodes (Y electrodes) 1 are formed on the plurality of barrier ribs 6, respectively. The deposition method is the same as that of the address electrode 2. Thus, each of the plurality of address electrodes 1, 2 'as will become substantially perpendicular to each other, it is arranged with a predetermined interval.

The thickness of the partition wall 6 is optimally set in consideration of gas pressure, gas composition, pixel pitch, etc., but generally 80 μm.
It is about 200 μm. The partition wall 6 may be formed in a grid shape in order to surely avoid crosstalk between adjacent pixels.

Either of the plurality of address electrodes 1, 2'may be an anode or a cathode. However, since it is necessary to generate the discharge from one side of the plurality of barrier ribs 6, the plurality of address electrodes 1 arranged above the plurality of barrier ribs 6 should be correspondingly displaced to one side of the barrier ribs 6. To

On the plurality of partition walls 6 and the plurality of addresses 1, the lattice-shaped thick spacers 8 in a lattice shape are arranged so that the lattices communicate with the holes of each lattice formed by the plurality of address electrodes 1 and 2 '. Are arranged. Then, the phosphor layer 7 is adhered and formed on the wall surface of the lattice hole of the spacer 8. The spacer 8 may be formed on the lower surface of the front glass plate 12 by screen printing or the like, but may be an insulating plate etched, a metal plate molded, or the like. You can use what you have done.

The height of the spacer 8 is about 0.1 mm to 2.0 mm, although the optimum value is selected depending on the driving conditions. The higher the height of the spacer 8, the higher the voltage applied to the display anode 5, which will be described later. However, when the height is usually about 1.5 mm, a positive column appears and the ultraviolet radiation becomes stronger and the brightness becomes higher.

On the lower surface of the front glass plate 12, a display anode 5 comprising a transparent conductive layer of tin oxide, indium tin oxide or the like.
Is arranged. This display anode 5 may be a mesh-shaped perforated metal plate other than a flat plate.

[0090] between the glass plates 11 and 12, the grid hole of the spacer 8, respectively communicated with the lattice holes by intersection of a plurality of address electrodes 1 and 2, as the discharge space 10 is formed, alignment line Be seen. The phosphor layer 7 is formed on the inner wall of the lattice hole of the spacer 8 by adhesion. The phosphor layer 7 is monochromatic phosphor or horizontal or / and repeated sequentially disposed a red vertical direction, Ru green and blue phosphors der.

Next, the operation of the discharge display device of the sixth embodiment will be described with reference to FIG. Multiple address electrodes 1
16B and FIG. 16B before the address discharge is selectively generated at the position corresponding to the image signal in the intersection between 2 and 2 ′.
As shown in C, a reset pulse is applied between a plurality of sets of memory electrodes (X1, X2 electrodes) 2, 2'to cause all the pixels to discharge once, and then the space charge generated at that time causes the memory electrodes 2, The wall charges remaining on 2'are erased.

When the next address period starts, FIGS.
As shown in FIG. 4, a pulse having a sufficient potential difference is applied between the address electrodes 1 and 2'corresponding to the selected pixel among the plurality of address electrodes 1 and 2 ', and an address discharge is generated.
By the address discharge, the insulating layer 9 on the address electrode 2 '
Wall charges are accumulated on the upper side, and then the address discharge is stopped immediately. Since there is a difference in voltage due to wall charges between the cells selected and the cells not selected depending on the presence or absence of the wall charges, in the memory period after the address period,
As shown in FIGS. 16B and 16C, when an AC pulse for sustaining discharge, that is, a sustain pulse is applied between the memory electrodes 2 and 2 ', continuous memory discharge can be maintained in the selected cell.

The above operation is the same as that of the three-electrode surface discharge type PDP of the second conventional example, but the sixth embodiment differs from the second conventional example in the operation of the display anode 5. During the reset period and the address period, as shown in FIG. 16D, the voltage of the display anode 5 is set to a low voltage that does not affect the address electrodes 1 and 2'and the plurality of sets of memory electrodes 2 and 2 '. Subsequently, when the address discharge period ends and the wall charge is selectively formed in each cell, the memory operation is started. At that time, as shown in FIG. 16D, the voltage of the display anode 5 is increased. , Keep the voltage constant during the memory period. However, the voltage applied to the display anode is set to a high level so as not to cause a discharge unrelated to the display to the plurality of sets of memory electrodes 2, 2 '. From this state, selective memory discharge is started along the distribution of wall charges formed during the address discharge period.

The voltage applied to the display anode 5 (see FIG.
D) is the reset and address period as described above,
Although it differs depending on the memory period, the voltage difference depends on the structure of the cell (discharge space), gas pressure, and the like. However, the voltage of the difference is relatively low, and in some cases, it is possible to apply a constant DC voltage (bias voltage) to the display anode 5 during the reset, address and memory periods.

Next, referring to FIG. 17, the display anode 5
Will be described. The discharge space 10 in FIG. 17 shows a discharge space corresponding to one pixel on the screen. In this case, since the discharge space is filled with ionized charged particles and metastable atoms, even if the voltage of the display anode is low, the discharge space of the two memory electrodes 2, 2 ′ is A discharge occurs between them. In other words, the discharge current from the display anode 5 is added to the memory discharge current. Even if a new wall charge is formed and the half cycle of the memory discharge is stopped, the current is similarly supplied from the display anode 5 to the memory discharge which continues in the next half cycle. That is, while the memory discharge is continued, the current from the display anode 5 is continuously supplied to the two memory electrodes 2, 2 ' . Further, in other words, the discharge between the two memory electrodes 2 and 2'is drawn out by the display anode 5 between the display anode 5 and the two memory electrodes 3 and 4. As shown in FIG. 17, this discharge occurs along the inner wall of the spacer 8 where the phosphor layer 7 is formed in the lattice holes, so that the ultraviolet rays generated by the discharge excite the phosphor layer 7 to emit light. Let Since no charged particles are present in the discharge space of the pixel in which the memory discharge is not performed, the discharge does not occur at a voltage of, for example, about 200 V to 300 V applied to the display anode 5.

The configuration of the second embodiment shown in FIGS. 5 and 6 and / or the third embodiment shown in FIG. 7 is the same as that of the first embodiment shown in FIGS. 1 and 2, the fourth embodiment shown in FIGS. It can be applied to the fifth embodiment shown in FIGS. 12 and 13.

According to the first discharge display device of the embodiment, as shown in FIGS. 1 and 2, a plurality of first and second addresses are arranged in close proximity so as to intersect each other through the partition wall 6. Electrodes 1 and 2 and a plurality of through holes are provided,
Memory electrodes 3 and 4 each having an entire surface covered with insulating layers 3a and 4a (two memory electrodes 3 arranged in proximity to each other,
4) and a plurality of first and second address electrodes 1,
Since 2 and the memory electrodes 3 and 4 are stacked and enclosed in a tube containing discharge gas, high brightness and high efficiency can be realized with a simple structure, and the address discharge and the voltage relationship between the memory electrodes cause mutual mutual discharge. The optimum voltage can be selected without disturbing the discharge of the memory cells, and the space between the first and second address electrodes 1 and 2 can be optimized regardless of the thickness of the memory electrodes 3 and 4. It is possible to obtain a discharge display device that can be set.

According to the second discharge display device of the embodiment, as shown in FIGS. 8 and 9, a plurality of first and second addresses are arranged in close proximity so as to intersect each other through the partition wall 6. Electrodes 1 and 2 and a plurality of through holes are provided,
A memory electrode 3 whose entire surface is covered with an insulating layer,
4 (two memory electrodes 3 and 4 arranged close to each other) and a plurality of through holes corresponding to the plurality of through holes of the memory electrodes 3 and 4, respectively. A plurality of first and second address electrodes 1, 2, memory electrodes 3, 4, spacers 8 and a common electrode having a spacer 8 having a body layer 7 formed thereon and a common electrode (display anode) 5 Since the (display anode) 5 is sequentially laminated and enclosed in a tube having a discharge gas, the memory discharge and the main discharge, that is, the discharge contributing to the light emitting display are separated by a simple structure and drive circuit. As a result, the reset discharge does not affect the light emission display, the contrast is significantly improved, and the light emission is performed without affecting the screen operation between the address discharge and the memory discharge. The rate and intensity can be significantly improved.

According to the third discharge display device of the embodiment, as shown in FIG. 12 and FIG. 13, a plurality of first and second electrodes arranged in close proximity to each other through the partition wall 6 are provided.
Address electrodes 1, 2 and a plurality of through holes are provided, and memory electrodes 3, 4 each having an entire surface covered with an insulating layer (two memory electrodes 3, 4 arranged in close proximity)
And a spacer having a plurality of through holes respectively corresponding to the plurality of through holes of the memory electrodes 3 and 4, and the phosphor layer 7 being adhered and formed on the surface opposite to the memory electrodes 3 and 4. 8
And a common electrode (display anode) 5 and a plurality of first electrodes
And the second address electrodes 1, 2, the memory electrodes 3, 4,
Since the spacer 8 and the common electrode (display anode) 5 are sequentially stacked and enclosed in the tube containing the discharge gas, the same effect as the second discharge display device of the embodiment can be obtained.

According to the fourth discharge display device of the embodiment, in the first, second or third discharge display device of the embodiment, as shown in FIG. 5 and FIG. Since the plurality of through holes of the memory electrodes 3 and 4 are configured to face each lattice hole formed of the electrodes 1 and 2, the first, second, or third discharge display device of the embodiment is provided. In addition to the effect, the alignment between the first and second address electrodes 1 and 2 and the memory electrodes 3 and 4 is facilitated, and the discharge effect can be remarkably improved by the hollow effect. These effects become more remarkable as the number of through holes of the memory electrodes 3 and 4 facing each lattice hole formed by the plurality of first and second address electrodes 1 and 2 increases.

[0102] According to the fifth discharge display device of the embodiment, in the first, discharge display device of the second, third or fourth embodiment, as shown in FIG. 7, using the memory electrodes as a partition 6 However, since a plurality of first and second address electrodes 1 and 2 are deposited on the insulating layers on both sides thereof, the effect of the first, second, third or fourth discharge display device of the embodiment is obtained. In addition to the first
And a second address electrodes 1, alignment between the memory electrodes is facilitated.

According to the sixth discharge display device of the embodiment, as shown in FIGS. 14 and 15, the first memory electrode 2 and the second memory electrode 2 which are formed on the insulating layer 9 and are arranged close to each other are formed. A plurality of sets of second address electrodes 2'also serving as the memory electrodes, and a plurality of first address electrodes 1 crossing the plurality of second address electrodes 2'through the insulating layer 9 and the partition wall 6. , Having a plurality of through holes corresponding to a plurality of lattice holes composed of a plurality of first and second address electrodes 1 and 2,
A spacer 8 having a phosphor layer 7 formed on the inner walls of the plurality of through holes and a common electrode (display anode) 5 are formed on the insulating layer 9. The spacers 8 are arranged close to each other. A plurality of sets of first and second memory electrodes 2, 2 ',
Since the plurality of first address electrodes 1, the spacers 8 and the common electrode (display anode) 5 are sequentially stacked and enclosed in a tube having a discharge gas, a memory discharge and a discharge can be performed by a simple structure and a driving circuit. It is possible to separate the main discharge, that is, the discharge that contributes to the light emission display, by this
The reset discharge does not affect the light emission display, the contrast is significantly improved, and the light emission efficiency and the brightness can be significantly improved without affecting the screen operation between the address discharge and the memory discharge. .

[0103]

According to the discharge display device of the first aspect of the present invention,
A plurality of first and second address electrodes arranged in close proximity so as to intersect with each other via a partition wall, and a memory electrode having a plurality of through holes and covering the entire surface thereof with an insulating layer. Since a plurality of first and second address electrodes and memory electrodes are stacked and enclosed in a tube containing discharge gas, high brightness and high efficiency can be realized with a simple structure, The optimum voltage can be selected without interfering with each other due to the voltage relationship between the discharge and the memory electrodes, and the first and second address electrodes can be selected regardless of the thickness of the memory electrodes 3 and 4. It is possible to obtain a discharge display device in which the interval between 1 and 2 can be set to an optimum value.

According to the discharge display device of the second aspect of the present invention, the plurality of first and second address electrodes and the plurality of through holes, which are arranged close to each other so as to intersect each other through the barrier ribs, are provided. At the same time, it has a memory electrode whose entire surface is covered with an insulating layer, and a plurality of through holes corresponding to the plurality of through holes of the memory electrode, and a phosphor layer is provided on the inner wall of each of the plurality of through holes. A plurality of first and second address electrodes each having a deposited spacer and a common electrode;
Since the memory electrode, the spacer, and the common electrode are sequentially laminated and enclosed in the tube containing the discharge gas, the memory discharge and the main discharge, that is, the discharge contributing to the light emission display are made possible by the simple structure and the driving circuit. Therefore, the reset discharge does not affect the light emission display, the contrast is significantly improved, and the light emission efficiency is improved without affecting the screen operation between the address discharge and the memory discharge. And the brightness can be significantly improved.

According to the discharge display device of the third aspect of the present invention, the plurality of first and second address electrodes and the plurality of through holes, which are arranged close to each other so as to intersect each other through the barrier ribs, are provided. In addition, the entire surface of the memory electrode is covered with an insulating layer, and a plurality of through holes respectively corresponding to the plurality of through holes of the memory electrode are provided, and the phosphor layer is provided on the surface opposite to the memory electrode. A plurality of first and second address electrodes, each of which has a spacer deposited thereon and a common electrode,
Since the memory electrode, the spacer, and the common electrode are sequentially laminated and enclosed in the tube containing the discharge gas, the same effect as the discharge display device according to the second aspect of the invention can be obtained.

According to the discharge display device of the fourth aspect of the present invention, in the discharge display device of the first, second or third aspect of the present invention, each lattice hole constituted by a plurality of first and second address electrodes. On the other hand, since the plurality of through holes of the memory electrode are configured to face each other, in addition to the effect of the first, second or third discharge display device of the present invention, the first and second address electrodes are provided. And the alignment with the memory electrode is facilitated, and the discharge characteristics due to the hollow effect can be significantly improved. These effects become more remarkable as the number of through holes of the memory electrode facing each lattice hole formed by the plurality of first and second address electrodes increases.

According to the discharge display device of the fifth aspect of the present invention, in the discharge display device of the first, second, third or fourth aspect of the present invention, the memory electrode is used as a partition wall and the insulating layers on both sides of the memory electrode are used. In addition to the effects of the first, second, third, or fourth discharge display device of the present invention, a plurality of first and second address electrodes are deposited on the first and second address electrodes. The alignment between the address electrode and the memory electrode becomes easy.

According to the discharge display device of the sixth aspect of the present invention, the second address electrode also formed as the first memory electrode and the second memory electrode, which are formed on the insulating layer and are arranged close to each other. A plurality of first address electrodes that intersect a plurality of second address electrodes via insulating layers and partition walls, and a plurality of first address electrodes and a plurality of first address electrodes. A spacer having a plurality of through holes corresponding to the lattice holes, each of which has a phosphor layer deposited on the inner wall of the plurality of through holes, and a common electrode, which are deposited on the insulating layer. In addition, since a plurality of sets of first and second memory electrodes, a plurality of first address electrodes, a spacer and a common electrode, which are arranged close to each other, are sequentially stacked and enclosed in a tube having a discharge gas. , Simple structure and drive circuit, memory discharge , The main discharge, that is, the discharge contributing to the light emission display can be separated, so that the reset discharge does not affect the light emission display, the contrast is significantly improved, and the address discharge and the memory discharge. It is possible to significantly improve the luminous efficiency and the brightness without affecting the screen operation between the discharges.

[Brief description of the drawings]

FIG. 1 is a perspective view of a discharge display device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the discharge display device according to the first embodiment.

FIG. 3 is a timing chart for explaining the operation of the first embodiment (1) A voltage of the address electrode 1 (image signal) B voltage of the address electrode 2 (scan signal) C voltage of the memory electrode 3 D memory electrode 4 Voltage

4 is a timing chart for explaining the operation of the first embodiment (2) A voltage of the address electrode 1 (image signal) B voltage of the address electrode 2 (scanning signal) C voltage of the memory electrode 3 D memory electrode 4 Voltage

FIG. 5 is a perspective view of a discharge display device according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view of the discharge display device according to the second embodiment.

FIG. 7 is a perspective view of a part of the discharge display device according to the third embodiment.

FIG. 8 is a perspective view of a discharge display device according to a fourth embodiment of the present invention.

FIG. 9 is a cross-sectional view of the discharge display device according to the fourth embodiment.

FIG. 10 is a timing chart of the fourth embodiment: A voltage of address electrode 1 (image signal) B voltage of address electrode 2 (scan signal) C voltage of memory electrode 3 voltage of memory electrode 4 voltage of E display anode 5

FIG. 11 is a cross-sectional view showing the discharge path of the fourth embodiment.

FIG. 12 is a sectional view of a discharge display device according to a fifth embodiment of the present invention.

FIG. 13 is a plan view of the discharge display device according to the fifth embodiment.

FIG. 14 is a perspective view of a discharge display device according to a sixth embodiment of the present invention.

FIG. 15 is a cross-sectional view of the discharge display device according to the sixth embodiment.

16 is a timing chart of the sixth embodiment: A voltage of the address electrode (Y electrode) 1 (image signal) B voltage of the memory electrode (X2) 2 ′ (scanning and memory voltage) C voltage of the memory electrode (X1) 2 (Memory voltage) D Display anode 5 voltage

FIG. 17 is a sectional view showing the discharge path of the fifth embodiment.

FIG. 18 is a perspective view of a discharge display device of Conventional Example 1.

FIG. 19 is a perspective view of a discharge display device of Conventional Example 2.

FIG. 20 is a sectional view of a discharge display device of Conventional Example 3.

[Explanation of symbols]

 1 Address Electrode 2 Address Electrode (Memory Electrode) 2'Address Electrode (Memory Electrode) 3 Memory Electrode 3a Insulating Layer 4 Memory Electrode 4a Insulating Layer 5 Display Anode (Common Electrode) 6 Partition 7 Phosphor Layer 8 Spacer 9 Insulating Layer 10 Discharge Space 10 'Auxiliary discharge space 11 Rear glass plate 12 Front glass plate 13 Cathode 14 Auxiliary anode 15 Resistance layer

Claims (6)

(57) [Claims] 1. A plurality of first and second address electrodes, which are arranged close to each other so as to intersect with each other via a partition wall, and a plurality of through holes are provided, and the entire surface thereof is covered with an insulating layer. A discharge display device comprising: a plurality of first and second address electrodes and the memory electrode, which are stacked and enclosed in a tube having a discharge gas. 2. A plurality of first and second address electrodes, which are arranged close to each other so as to intersect with each other via a partition wall, and a plurality of through holes are provided, and the entire surface thereof is covered with an insulating layer. A memory electrode, a spacer having a plurality of through holes respectively corresponding to the plurality of through holes of the memory electrode, and a phosphor layer adhered to an inner wall of each of the plurality of through holes; And a plurality of the first and second address electrodes, the memory electrodes, the spacers, and the common electrode are sequentially stacked and enclosed in a tube containing a discharge gas. apparatus. 3. A plurality of first and second address electrodes, which are arranged close to each other so as to intersect with each other through a partition wall, and a plurality of through holes are provided, and the entire surface thereof is covered with an insulating layer. And a spacer having a plurality of through holes respectively corresponding to the plurality of through holes of the memory electrode and having a phosphor layer deposited and formed on the surface opposite to the memory electrode. And a plurality of the first and second address electrodes, the memory electrodes, the spacers, and the common electrode are sequentially stacked and enclosed in a tube containing discharge gas. Discharge display device. 4. The discharge display device according to claim 1, 2 or 3, wherein a plurality of through holes of the memory electrode are provided for each lattice hole formed by the plurality of first and second address electrodes. A discharge display device, characterized in that they are configured to face each other. 5. The discharge display device according to claim 1, 2, 3, or 4, wherein the memory electrode is used as the barrier rib, and the plurality of first and second addresses are provided on insulating layers on both sides thereof. A discharge display device comprising electrodes formed by deposition. 6. A plurality of sets of a first memory electrode and a second address electrode which also function as a second memory electrode and which are formed on the insulating layer and are arranged close to each other, and the insulating layer and the partition wall. Via a plurality of first address electrodes intersecting with the plurality of second address electrodes, and a plurality of lattice holes corresponding to a plurality of lattice holes formed by the plurality of first and second address electrodes. Spacers each having a through hole, each having a phosphor layer deposited on the inner wall of each of the plurality of through holes, and a common electrode, deposited on the insulating layer, and arranged in proximity to each other. A plurality of sets of the first and second memory electrodes, the plurality of first address electrodes, the spacers and the common electrode are sequentially stacked and enclosed in a tube having a discharge gas. Discharge display device.