JP2675056C - - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a technology that is effective when used for a color line sensor. 2. Description of the Related Art As an example of a color line sensor (one-dimensional sensor), there is the National Convention of the Institute of Electronics and Communication Engineers 1-232 in 1985. This color line sensor has a red (
R), green (G) and blue (B) color filters are attached, and the three line sensors are integrally sealed. [Problem to be Solved by the Invention] In the color line sensor as described above, three line sensors are arranged side by side,
Each of them is provided with R, G and B color filters, so (1) the pitch in the vertical direction becomes large and high resolution cannot be obtained, and (2) it is composed of a combination of three line sensors. (3) It is necessary to operate the three line sensors synchronously, the drive circuit becomes complicated, and the variations in the element characteristics of the three line sensors are output signals as they are. There is a problem that appears in the. Therefore, it has been considered that the color line sensor is configured as a one-chip semiconductor integrated circuit. By doing so, the photoelectric conversion elements can be arranged at a high density, so that a high resolution can be obtained. However, it has been clarified by the study of the present inventor that the following problems occur when the photoelectric conversion elements are arranged at high density.
Such a semiconductor integrated circuit device has an output terminal for an image signal and a terminal for inputting a clock pulse used for reading the image signal. While the image signal is a minute analog signal, the clock pulse is a signal that changes with a large signal amplitude such as a power supply voltage. Therefore, if the above terminals are arranged adjacently,
Pulse noise is added to the image signal side through the parasitic capacitance between the two. An object of the present invention is to provide a solid-state imaging device that has realized high resolution and high S / N. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. [Means for Solving the Problems] Briefly describing the outline of a representative one of the inventions disclosed in the present application,
It is as follows. That is, a terminal arranged adjacent to the signal output terminal of the solid-state imaging device is an empty terminal, and the empty terminal is a terminal to which a DC voltage is supplied from the semiconductor integrated circuit. [Operation] According to the above-described means, the signal output terminal is substantially shielded by the empty terminal to which a DC voltage is supplied from the semiconductor integrated circuit, so that the pulse noise due to capacitive coupling can be significantly reduced. [Embodiment] FIG. 2 is a block diagram showing a main part of an embodiment of a color line sensor to which the present invention is applied. The circuit block shown in FIG. 1 is formed on a single semiconductor substrate such as single crystal silicon, though not particularly limited, by a known semiconductor integrated circuit manufacturing technique. In the figure, the light receiving section is composed of a photodiode array arranged in a line. In this embodiment, in order to constitute a color line sensor, the above-described light receiving units are provided for blue, green, and red, respectively. In the above-mentioned photodiode array, the area occupied by a CCD (charge transfer device) analog shift register constituting a transfer section described later is larger than the area occupied by one photosensor. Is done. The output signals of the odd-numbered photodiodes in the photodiode array are read out in parallel to the transfer section CCD through the transfer gate provided above the light receiving section composed of the photodiode array in FIG. The output signals of the even-numbered photodiodes are read out in parallel to the transfer unit CCD through a transfer gate provided below the light receiving unit composed of the photodiode array in FIG. In the figure, the transfer gate and the transfer section are represented like a CCD together. The output signals of the CCD transfer units, which are allocated to the respective colors in the vertical direction, are output to output terminals OSAB, OSBB (blue), OSAG through an output amplifier.
, OSBG (green) and OSAR, OSBR (red). In addition, the color line sensor includes various clocks such as a transfer clock pulse for controlling a transfer gate, a shift clock pulse required for operation of a CCD analog shift register, and a clock pulse required for operation of an output amplifier, as described later. A pulse is input. Each of the clock pulses has a large amplitude that makes a full swing under the power supply voltage, whereas each of the output terminals OSAB, OSBB (blue), OSAG, OSBG
(Green) and image signals output from OSAR and OSBR (Red) are extremely small signals. Therefore, if the output terminal is arranged adjacent to the terminal to which the clock pulse is input as described above, the coupling noise that jumps in due to the parasitic capacitance between the terminals when viewed from the image output signal side becomes large that cannot be ignored. Would. Therefore, as shown in FIG. 1, the above terminals are arranged. As the signal output terminals OSAG and OSBG corresponding to green (G), terminals Nos. 2 and 45 at the top of the semiconductor integrated circuit device are used. The first terminal adjacent to the signal output terminal OSAG (second terminal) is an empty terminal NC, and is not particularly limited.
D (operating voltage of output amplifier) potential is output. The third terminal adjacent to the signal output terminal OSAG (second terminal) is supplied with the power supply voltage OD of the output amplifier. This power supply voltage OD is common to circuits corresponding to each color. On the other hand, a terminal 44 adjacent to the signal output terminal OSBG (terminal 45) supplies the ground potential VSS of the circuit. This terminal VSS is common to circuits corresponding to each color.
The terminal 46 adjacent to the signal output terminal OSBG (terminal 45) is supplied with the bias voltage OGG of the output section of the CCD transfer path corresponding to green. As the signal output terminals OSBR and OSAR corresponding to red (R), terminals 9 and 11 on the left side of the semiconductor integrated circuit device are used. The eighth terminal adjacent to the signal output terminal OSBR (the ninth terminal) is an empty terminal NC so as to output the OD potential as described above. The 10th terminal adjacent to the signal output terminal OSBR (the 9th terminal) is supplied with the bias voltage OGR of the output section of the CCD transfer path corresponding to red. This terminal OGR is also a terminal adjacent to the signal output terminal OSAR (No. 11). The twelfth terminal adjacent to the signal output terminal OSAR (the eleventh terminal) is an empty terminal NC so as to output the OD potential as described above. As the signal output terminals OSBB and OSAB corresponding to blue (B), terminals 36 and 38 on the right side of the semiconductor integrated circuit device are used. A terminal 35 adjacent to the signal output terminal OSBB (terminal 36) is an empty terminal NC, and outputs an OD potential as described above. The 37th terminal adjacent to the signal output terminal OSBB (the 36th terminal) is supplied with the bias voltage OGB of the output section of the CCD transfer path corresponding to blue. This terminal OGB is also a terminal adjacent to the signal output terminal OSAB (No. 38). The 39th terminal adjacent to the signal output terminal OSAB (the 38th terminal) is an empty terminal NC, and outputs the OD potential in the same manner as described above. The following describes a typical timing pulse. Timing pulses φTGR (terminal 19), φTGG (terminal 25) and φTGB (terminal 25)
(No. 30 terminal) is a timing pulse for reading the signal of the photodiode array in parallel to the transfer path. Timing pulses φ2R (terminals 15 and 20) and φ1R (terminals 16 and 21) are shift clock pulses for red CCD transfer, and timing pulses φ1G (terminals 22 and 27), φ2G
(Terminals 23 and 26) are shift clock pulses for green CCD transfer. Timing pulses φ1B (Terminals 28 and 32) and φ2B (Terminals 29 and 31) are blue CCDs. Is a shift clock pulse for transfer. No terminal for inputting any clock pulse is arranged adjacent to the signal output terminal including such a clock pulse or another clock pulse. In other words, a vacant terminal or a DC voltage terminal is always arranged in the signal output terminal, and since these terminals wait for the shielding effect of the signal output terminal, pulse noise is very small. It can be prevented from getting on the image signal. The operational effects obtained from the above embodiment are as follows. That is, (1) The signal output terminal of the solid-state imaging device, which is disposed adjacent to the signal output terminal, is a vacant terminal or a terminal to which a DC voltage is supplied. Since the shield is made substantially by the supplied terminal, the effect that the pulse noise jumped in by the capacitive coupling can be greatly reduced can be obtained. (2) By providing the line sensors of the three primary colors in the one semiconductor integrated circuit device, it is possible to obtain a high resolution since the photodiode arrays can be arranged at a high density. Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, reading from the photodiode array may be performed by using a CCD MOSFET instead of using the above-described CCD analog shift register, or may be performed by using a switch MOSFET. Further, the signal output terminal may be arranged at the end of the semiconductor integrated circuit device such as the first terminal and the number of adjacent terminals may be reduced to one. The present invention is widely applied to various solid-state imaging devices having a terminal for outputting a minute image signal and a terminal for inputting a clock pulse, such as various area sensors such as a CCD type and a MOS type, in addition to the color line sensor described above. Available. [Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the signal output terminal of the solid-state imaging device is provided as a vacant terminal, and the vacant terminal is a terminal to which a DC voltage is supplied from the semiconductor integrated circuit. Since an empty terminal to which a DC voltage is supplied from the circuit is substantially shielded, pulse noise jumping in by capacitive coupling can be greatly reduced.

[Brief description of the drawings]   FIG. 1 is a pin arrangement diagram showing one embodiment of a solid-state imaging device according to the present invention,   FIG. 2 is a block diagram of a main part of the color line sensor according to the present invention.   CCD transfer section (analog shift register)

Claims (1)

Claims 1. A semiconductor integrated circuit in which photoelectric conversion elements are arranged on a chip, a storage portion for storing the semiconductor integrated circuit, and a plurality of terminals provided on two opposite sides of the storage portion. And a terminal arranged adjacent to the image signal output terminal of the terminal as an empty terminal ,
A solid-state imaging device , wherein a DC voltage is supplied to a terminal from the semiconductor integrated circuit .