JP2674574B2 - Clock generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and more particularly to a clock generation circuit built in an LSI such as a microcomputer.

[0002]

2. Description of the Related Art Conventionally, a general clock generation circuit of this type includes a crystal oscillation circuit for generating a reference clock having a reference frequency and a clock divider for dividing the reference clock to generate a plurality of required clocks. Was configured.

Referring to FIG. 3, which shows a block diagram of a conventional clock generation circuit, in this conventional clock generation circuit, the frequency is determined by a crystal oscillator 5 connected to the outside, and an oscillation signal CLO and this signal CLO are waveform-shaped. An oscillator circuit 1 that generates a reference clock CLK; a counter 3 that counts a constant value to set an oscillation stabilization time of the oscillator circuit 1 and outputs an overflow signal as a start signal ST;
In response to the supply of the start signal ST, the clock CK is divided by a predetermined dividing ratio, and n + 1 clocks φ0,
and a clock divider 4 for generating φ1 ... φn.

Next, the operation of the conventional clock generation circuit will be described with reference to FIG. 3 and FIG. 4 which is a time chart showing the operation waveforms of the respective parts. The oscillation circuit 1 oscillates when the power supply voltage rises. Start, oscillation signal CLO
Also, the amplitude of the reference clock CLK, which is its waveform shaping signal, gradually rises and reaches a constant amplitude. This clock C
LK is supplied to the counter 3. The counter 3 is an X-bit counter, counts it in response to the supply of the clock CLK, and outputs an overflow signal, that is, a start signal ST when the count value n = 2X is reached. The count value n is set so as to sufficiently cover the oscillation circuit 1, that is, the stabilization time of the amplitude of the clock CLK. The clock divider 4 starts generating the clocks φ0, φ1 ... φn in response to the supply of the start signal ST.

This conventional first clock generation circuit has no problem when the above-described smooth oscillation start is performed. However, the crystal unit has various vibration modes such as longitudinal vibration, lateral vibration, thickness vibration, etc., each of which has a different natural vibration frequency. Originally, one of the vibration modes, and therefore the electrode attached to oscillate at one frequency Has been. However, due to factors such as the power-on characteristics of the power supply, parasitic oscillation or abnormal oscillation may occur when the oscillation starts. In that case, since the frequency of the oscillation signal CLO rises abnormally, the counter 3 overflows before the oscillation stabilizes and the start signal ST is generated, and incomplete clocks φ0, φ1 ... φn are generated.

[0006]

In the above-described conventional clock generation circuit, the oscillation frequency rises abnormally when the crystal oscillation circuit causes parasitic oscillation or abnormal oscillation at the time of oscillation startup due to factors such as the power supply startup characteristics. Therefore, the counter for setting the stable time overflows before the oscillation stabilizes, the clock divider starts operating and generates an incomplete clock, and the circuit inside the LSI operates in response to the supply of this clock. Had the drawback of malfunctioning.

[0007]

A clock generation circuit of the present invention includes a crystal oscillation circuit for generating a reference clock, and a frequency division start signal generation circuit for counting a predetermined number of the reference clocks and outputting a frequency division start signal. A divided clock synchronized with the reference clock in response to the supply of the divided start signal is divided by a predetermined dividing ratio.
In a clock generation circuit including a clock divider that generates two divided clocks, the divided start signal generation circuit outputs the start signal at least during the abnormal oscillation period in response to detection of abnormal oscillation of the oscillation circuit. It is configured with a frequency division start control circuit that prohibits it.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Next, referring to FIG. 1, which is a block diagram in which components common to those of FIG. 3 are designated by common reference characters / numerals, the embodiment of this invention shown in FIG. In addition to the conventional oscillation circuit 1, the clock divider 4, and the crystal oscillator 5, the clock generation circuit of FIG. 1 operates the clock divider 4 by setting the oscillation stabilization time of the oscillation circuit 1 instead of the counter 3. A start control circuit 2 is provided which outputs a start signal ST for starting the operation and inhibits the output of the start signal ST during the abnormal oscillation period when the abnormal oscillation is detected.

The start control circuit 2 uses the reference clock CL
A delay circuit 211 that delays K for a fixed time sufficiently larger than the abnormal oscillation cycle and smaller than the cycle of the clock CLK and outputs the delayed clock DC, ANDs the reference clock CLK and the delayed clock DC, and outputs the clock CDK A
A one-shot circuit 21 including an ND circuit 212, an X-bit counter 22 that counts a clock CDK and outputs a count value N1 and an overflow signal as a start signal ST, and a count value that counts a clock CLK that is reset by the start signal ST. A counter 23 that is the same as the counter 22 that outputs N2 and a comparator 24 that compares the count values N1 and N2 and outputs them as a clock CP when they match are provided.

Next, the operation of the present embodiment will be described with reference to FIG. 1 and FIG. 2, which is a time chart showing the operation waveforms of the respective parts during abnormal oscillation. First, when the oscillation circuit 1 is in normal oscillation, Reference clock CLK and delayed clock DC
Is always ANDed, the clock CDK has the same cycle as the reference clock CLK, and therefore the counter 2
Since the count values N1 and N2 of 2 and 23 are always the same, the comparator 24 supplies the clock CP with the same period as the clock CLK to the clock divider 4. On the other hand, the counter 22 counts the clock CDK and outputs the overflow signal as the start signal ST when the count value N1 reaches n = 2X, as in the conventional case. The clock divider 4 responds to the supply of the start signal ST with the clock C.
The frequency division operation of P is performed, and predetermined clocks φ0, φ1 ... φ
Generate n.

That is, the same operation as the above-described conventional clock generation circuit is performed.

The operation during abnormal oscillation will now be described. Since the reference clock CLK and the delayed clock DC cannot be ANDed during the abnormal oscillation period T, the one-shot circuit 21 does not output the clock CDK. Therefore, the counter 22 starts counting the clock CDK from the time when the oscillation becomes normal after the end of the period T, and the count value N
When 1 reaches n = 2X, a start signal ST is generated. On the other hand, since the counter 22 counts the reference clock CLK as it is, the count values N1 and N of both are maintained from the start of oscillation to the supply of this start signal ST.
2 are different, so the comparator 24 does not output the clock CP. The counter 23 is reset in response to the supply of the start signal ST, and the count value N2 starts from 0 at this point. Naturally counter 2 at the same time
Since the count value N1 of 2 also starts from 0, the count values N1 and N2 of both match, and the comparator 24 starts outputting the clock CP. In response to the supply of the start signal ST, the clock divider 4 divides the clock CP that is started to be supplied at the same time, and a predetermined clock φ
0, φ1, ... φn are generated.

[0013]

As described above, the clock generation circuit of the present invention is provided with the frequency division start control circuit for inhibiting the output of the start signal during the abnormal oscillation period, so that the LSI
There is an effect that it is possible to prevent generation of an incomplete clock that causes a malfunction of the internal circuit.

[0014]

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a clock generation circuit of the present invention.

FIG. 2 is a time chart showing an example of the operation of the clock generation circuit of this embodiment.

FIG. 3 is a block diagram showing an example of a conventional clock generation circuit.

FIG. 4 is a time chart showing an example of the operation of the conventional clock generation circuit.

[Explanation of symbols]

 1 Oscillation Circuit 2 Start Control Circuit 3, 22, 23 Counter 4 Clock Divider 5 Crystal Oscillator 21 One-shot Circuit 24 Comparator 211 Delay Circuit 212 AND Circuit

Claims (3)

(57) [Claims] 1. A crystal oscillation circuit for generating a reference clock, a frequency division start signal generation circuit for counting a predetermined number of the reference clocks and outputting a frequency division start signal, and in response to the supply of the frequency division start signal. And a clock divider that generates at least one divided clock that is obtained by dividing a divided clock that is synchronized with the reference clock by a predetermined dividing ratio, the dividing start signal generating circuit including: A clock generation circuit comprising a frequency division start control circuit which inhibits the output of the start signal at least during the abnormal oscillation period in response to detection of abnormal oscillation of the oscillation circuit. 2. The first clock generation circuit, wherein the frequency division start control circuit generates a first clock when the cycle of the reference clock exceeds a predetermined time width in response to the supply of the reference clock. A circuit, a first counter that counts the first clock and outputs a first count value and an overflow signal that is the start signal, and resets the reference clock in response to the supply of the start signal. And a second counter for counting the second count value and outputting a second count value, and a comparator circuit for outputting the divided clock in response to the coincidence of the first and second count values. The clock generation circuit according to claim 1. 3. A delay circuit, wherein the first clock generation circuit delays the reference clock by the time width and outputs a delayed clock, and performs a logical product operation of the reference clock and the delayed clock to perform the first AND operation. The clock generation circuit according to claim 2, further comprising an AND circuit that generates a clock.