JP2674122B2 - Memory device read circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read circuit of a digital information storage device, and more particularly to a read circuit that corrects a deviation of a duty ratio of a read signal in an optical storage device of an optical disc device.

[Prior Art] In an optical storage device such as an optical disk device, a laser beam is used for recording / reproducing means. To record information on an optical storage medium, this laser light is focused on a very small spot,
The light energy forms a pit on the storage medium. Further, in order to reproduce information, an optical sensor detects a change in intensity of reflected light depending on the presence or absence of pits on the medium. The read circuit detects the rising and falling polarity change points of the reproduced analog signal to obtain a binary signal. Furthermore, this 2
A clock signal is reproduced based on the binarized signal. And
Data discrimination of the binarized signal is performed based on this clock signal.

FIG. 4 shows the relationship between the reproduced analog signal obtained from the optical sensor and the pit. FIG. 4A shows the presence or absence of pits on the medium. FIG. 4B shows a reproduced analog signal. Since the information is included in the edge 11 of the pit, it is important how faithfully the pit edge is formed at the time of recording. Also, during reproduction, it is important how to read the pit edge faithfully. Then, ideally, the duty ratio of the read binarized signal becomes equal to the duty ratio of the original information. However, the duty ratios of the two do not always match due to various causes. The causes are as follows. Since the pit formation depends on the recording energy of the laser, the duty ratio of the original information and the duty ratio on the medium may deviate due to variations in the moving speed of the medium, variations in the laser power, and variations in the recording sensitivity of the medium. I will end up. Further, even during reproduction, the baseline of the reproduced analog signal fluctuates due to fluctuations in the reflectance of the medium, and the duty ratio on the medium,
The duty ratio of the read signal deviates. The deviation of the duty ratio causes a data bit shift at the time of reproduction, and is a major factor of reducing the reproduction error margin particularly when trying to achieve a high recording density.

A reading circuit disclosed in Japanese Patent Laid-Open No. 59-113529 is known as a means for correcting such duty ratio deviation during reproduction. In this read circuit, as shown in FIG. 5, when the reproduced analog signal of FIG. 5 (A) is binarized to obtain the read signal of FIG. _T
Is controlled to correct the deviation of the duty ratio. That is, the read signal of FIG. 5 (B) is compared with the reproduced clock signal to detect the deviation of the duty ratio, and the threshold value V _T is controlled so as to reduce the deviation.

[Problems to be Solved by the Invention] The conventional correction method described above is convenient because it can be corrected with a simple circuit configuration, but has the following drawbacks. The method of correcting the deviation of the duty ratio by changing the threshold value when the reproduced analog signal is binarized is achieved by utilizing the rising and falling slopes of the reproduced analog signal.
The rising and falling times of the digitized signal are adjusted. Therefore, the correction range for such time adjustment is limited to the range of the change time of the rise and fall of the reproduced analog signal. Therefore, the duty ratio is not always sufficiently corrected. Further, since the means for binarizing the reproduced analog signal and the means for correcting the deviation of the duty ratio are also used, the following problems occur. That is, if there is a deviation in the duty ratio, the threshold value for binarization changes. As a result, if the amplitude of the reproduced analog signal is locally reduced due to a medium defect or the like, correct binarization cannot be performed and a read error may occur.

The present invention has been made under such circumstances, and an object thereof is to provide a read circuit capable of correcting a deviation of a duty ratio independently of means for binarizing a reproduced analog signal. Especially.

[Means for Solving the Problems] In order to achieve the above object, the read circuit of the memory device according to the present invention has the following features. That is, information detecting means for detecting information stored in a storage device and outputting a reproduced analog signal, and detecting a rising edge and a falling edge of the reproduced analog signal and outputting a reproduction level signal which is a binary digital signal. And a variable delay means capable of generating a delay level signal by delaying the rising time and the falling time of the reproduction level signal with different delay times and changing the delay time. A clock generation circuit that outputs a clock signal that is phase-synchronized with the delay level signal; a data discrimination circuit that discriminates the delay level signal at the timing of the clock signal; a rising time of the delay level signal and the clock The rise time difference is obtained by detecting the time difference from the reference position of the signal, and the fall time of the delay level signal and the clock A time difference detection means for detecting a time difference between the reference position of the signal and a fall time difference, and a time difference difference detection means for calculating a difference between the rise time difference and the fall time difference, so that the difference becomes small. And controlling the different delay times.

[Operation] In the present invention, at the stage of binarizing the reproduced analog signal, the reproduction level signal after the binarization is corrected without correcting the deviation of the duty ratio. That is, the deviation of the duty ratio is corrected by the variable delay means, the time difference detection means, and the time difference difference detection means. The variable delay means delays the rising time and the falling time of the reproduction level signal by different delay times. This is because the duty ratio can be changed by changing the delay time. Then, in order to control the delay time, the deviation of the duty ratio of the delay level signal is detected and fed back to the variable delay means. In order to detect the deviation of the duty ratio, the rising and falling times of the delay level signal may be compared with the reference position of the clock signal (for example, the falling time).
The time difference detecting means performs this kind of comparison to obtain the rise time difference and the fall time difference. If the two time differences are equal, it means that the duty ratio is not displaced. If the two time differences are different, it means that the duty ratios are deviated, and it is necessary to change the above-mentioned two delay times by an amount corresponding to the difference between the two time differences. The time difference difference detection means detects the difference between these two time differences. Then, the two delay times are changed by feeding back the output of the time difference difference detection means to the variable delay means, thereby correcting the duty ratio deviation.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block circuit diagram of an embodiment of the present invention. First, the overall configuration of this circuit will be described. The output of the reading optical head 1 is input to the amplifier circuit 2. Amplifier circuit 2
Output a is a binarization circuit 4 and an envelope detection circuit 3
Entered as The output b of the envelope detection circuit 3 is
It is input to the binarization circuit 4. The output c of the binarization circuit is input to the variable delay circuit 5. Output f of variable delay circuit 5
Is input to the data discriminating circuit 7, the clock generating circuit 6, and the time difference detecting circuit 8. The output g of the clock generation circuit 6 is input to the data discrimination circuit 7 and the time difference detection circuit 8. The two outputs i, j of the time difference detection circuit 8 are input to the differential amplifier circuit 9. The output k of the differential amplifier circuit 9 is
It is fed back to the variable delay circuit 5 via the low-pass filter 10.

Next, the configuration of the time difference detection circuit 8 will be described in detail.
The time difference detection circuit 8 includes an inverter circuit 81, a one-shot circuit 82, and two D flip-flops 83 and 84. The output f of the variable delay circuit 5 is a D flip-flop.
Input to the clock input terminal CK of 83. Further, the output f of the variable delay circuit 5 is passed through the inverter circuit 81 to another D
It is also input to the clock input terminal CK of the flip-flop 84. The output g of the clock generation circuit 6 is a one-shot circuit.
Entered in 82. The output h of the one-shot circuit 82 is input to the data input terminal D and the reset input terminal R of the two D flip-flops 83 and 84, respectively. The outputs i and j of the Q output terminals of the two D flip-flops 83 and 84 are input to the differential amplifier circuit 9.

FIG. 2 shows a detailed circuit diagram of the variable delay circuit 5 described above. To explain the configuration, the output c of the binarization circuit 4 is
It is input to the positive current drive circuit 52. Also, the binarization circuit 4
The output c of is also input to the negative current drive circuit 53 via the inverter circuit 51. The output lines of the two current drive circuits 52 and 53 are combined to form one current supply line 58. The capacitor 54 is connected between the current supply line 58 and the ground. A diode 55 is connected between the current supply line 58 and the positive voltage source (+ Vo).
The forward direction of diode 55 is toward the positive voltage source. Further, another diode 56 is connected between the current supply line 58 and the negative voltage source (−Vo). Diode 56
The forward direction of is toward the current supply line 58. Current supply line 58
Are connected to the positive terminal 57 of the comparison circuit 57. Comparison circuit
The output e of the low-pass filter 10 is input to the negative terminal of 57. The output of the comparison circuit 57 becomes the output f of the variable delay circuit 5.

Next, the operation of this embodiment will be described. Description will be made with reference to the above-mentioned FIG. 1 and FIG. 2 as well as the time chart of FIG. The signals of (a) to (k) are drawn in the time chart of FIG.
This corresponds to the signals a to k in the circuits of FIGS. FIG. 3 shows an example in which the reproduced analog signal a has a duty ratio deviation. That is, the position of the rising polarity change point of the reproduced analog signal a is behind the position of the original information ““ 1 ”,“ 1 ”,“ 0 ”,“ 1 ”...”, and conversely The position of the trailing edge polarity change point is advanced. Therefore, the duty ratio is shifted to the smaller side.

First, the operation of obtaining a binary digital signal from the output of the reading optical head 1 will be described. The signal reproduced by the reading optical head 1 is weak, and the signal is amplified by the amplifier circuit 2,
The reproduced analog signal a is obtained. The envelope detection circuit 3 detects the positive and negative envelopes of the reproduced analog signal a, and the median value thereof becomes the binarized threshold signal b. The binarization circuit 4 compares the reproduced analog signal a with the binarized threshold signal b to obtain a reproduction level signal c. The reproduction level signal c is a binary digital signal. That is, the rising and falling timings of the reproduction level signal c coincide with the rising and falling polarity change points of the reproduced analog signal a.

Next, an operation of delaying the reproduction level signal c will be described with reference to FIGS. The positive current drive circuit 52 is driven at the rising timing of the reproduction level signal c,
The current of + Io is output to the current supply line 58. Further, since the reproduction level signal c is input to the negative current drive circuit 53 via the inverter circuit 51, the negative current drive circuit 53 is driven at the falling timing of the reproduction level signal c,
The current Io is output to the current supply line 58. The current supplied to the bulb supply line 58 charges the capacitor 54. Therefore, the voltage d of the current supply line 58 linearly increases or decreases as the capacitor 54 is charged. However, due to the action of the diodes 55 and 56, the voltage d of the current supply line 58 is clamped at ± Vo. Assuming that the capacitance of the capacitor 54 is C, the voltage d rises with a slope of (+ Io / C) from the rise of the reproduction level signal c, and reaches + Vo. Also, from the trailing edge of the reproduction level signal c, (-Io / C)
It descends at a slope of and reaches -Vo. Next, in the comparison circuit 57, this voltage d is compared with the delay control signal e (which is set to the zero level for the time being in FIG. 3), and the delay level signal f is output. That is, when the voltage d rises and reaches the delay control signal e, the delay level signal f rises, and when the voltage d falls and reaches the delay control signal e, the delay level signal f falls. After all, the rising edge of the delay level signal f is longer than the rising edge of the reproduction level signal c.
Delay by T ₁ . Further, the fall of the delay level signal f is
It is delayed by the time T ₂ from the fall of the reproduction level signal c.

By the way, the delay times T ₁ and T ₂ depend on the value of the delay control signal e. That is, when the value of the delay control signal e decreases, the delay time T ₁ decreases and the delay time T ₂ increases. On the contrary, if the value of the delay control signal e increases,
The delay time T ₁ becomes large and the delay time T ₂ becomes small. Therefore, the ratio of the positive level section from the rising edge to the falling edge of the delay level signal f and the negative level section from the falling edge to the rising edge can be controlled by the value of the delay control signal e. The value of the delay control signal e is determined according to the deviation of the duty ratio of the delay level signal f, and as will be described below, the time difference detection circuit 8, the differential amplifier circuit 9, and the low pass filter 10 are provided. Is determined by

Next, the operation of the time difference detection circuit 8 will be described. In this circuit 8, the delay level signal f and the delay level signal f
Based on the clock signal g which is reproduced in phase synchronization with, the timing difference between the rising edge and the falling edge of the delay level signal f is detected. Hereinafter, a specific operation will be described. The clock signal g is input to the one-shot circuit 82, and the downward reset pulse 12 of the pulse width T ₃ appears in the output signal h of the one-shot circuit 82 each time the clock signal g falls. The D flip-flop 83 receives the delay level signal f at the clock input terminal CK and
Triggered on the rising edge of. The output signal h of the one-shot circuit 82 is input to the data input terminal D of the D flip-flop 83. Therefore, the output signal i at the Q output terminal of the D flip-flop 83 goes high due to the rise of the delay level signal f. Thereafter, the reset pulse 12 is applied to the reset input terminal R, whereby the output signal i returns to the low level. The period T ₄ during which the output signal i of the D flip-flop 83 maintains the high level is the rise time difference. That is, the rise time difference T ₄ is the time from the rise of the delay level signal f to the fall of the clock signal g. Similarly, a high level appears in the output signal j of the other D flip-flop 84 for the falling time difference T ₅ . Here, the fall time difference T ₅ is the time from the fall of the delay level signal f to the fall of the clock signal g. If there is no duty ratio deviation in the delay level signal f, the fall time difference T ₄ and the fall time difference T ₅
Is equal to. In the time chart of FIG. 3, since the falling time difference T ₅ is larger, the duty ratio of the delay level signal f is deviated to the smaller one as compared with the duty ratio of the original information. Become.

Next, the operation of the time difference difference detection means will be described. In this embodiment, the time difference difference detecting means is the differential amplifier circuit 9
And a low-pass filter 10. The output signals i, j of the two D flip-flops 83, 84 are input to the differential amplifier circuit 9. Both signals are differentially amplified and become the output signal k. Therefore, by integrating the output signal k, a value proportional to the difference between the rising time difference and the falling time difference can be obtained. In this embodiment, this output signal k is input to a low-pass filter 10 to remove harmonic components, and a DC component is taken out from the output signal k at a cycle much longer than the cycle of the clock signal. The output of 10 becomes the delay control signal e. When the signal k in FIG. 3 is integrated, it has a negative value, and thus the value of the delay control signal e in this case is negative. As a result, in the time chart of the voltage d,
The delay control signal e falls from the zero level to a negative value. Then, the rising delay time T ₁ becomes shorter and the falling delay time T ₂ becomes longer. That is, the delay control signal e acts so that the duty ratio of the delay level signal f becomes large.

As described above, the deviation of the duty ratio of the reproduced analog signal a is corrected in the delay level signal f by the above feedback control.

According to this embodiment, the correction range for correcting the deviation of the duty ratio is independent of the rising and falling slopes of the reproduced analog signal a. That is, the correction range is determined by the charge power source Io for the capacitor 54, the capacitance C of the capacitor 54, and the clamp voltage Vo in the variable delay circuit 5. Therefore, the correction range can be freely changed by changing these circuit parameters.

Therefore, the threshold voltage b of the binarization circuit 4 becomes irrelevant to the correction of the deviation of the duty ratio, and the threshold voltage b can be optimally set only for the amplitude of the reproduced analog signal a. . In this embodiment, as the binarizing means, a method of comparing the level of the reproduced analog signal and the envelope median value is adopted.
The value conversion means is not limited to this.

[Effects of the Invention] As described above, according to the present invention, when the reproduced analog signal is binarized, the reproduction level signal after binarization is corrected without correcting the deviation of the duty ratio. Is taking place. Therefore, the deviation of the duty ratio can be corrected regardless of the binarizing means, and the correction range can be freely set.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of a variable delay circuit, FIG. 3 is a time chart of this embodiment, and FIG. 4 is a pit and a reproduction analog. FIG. 5 is a diagram corresponding to a signal, and FIG. 1 ... Readout optical head 2 ... Amplification circuit 3 ... Envelope detection circuit 4 ... Binarization circuit 5 ... Variable delay circuit 6 ... Clock generation circuit 7 ... Data discrimination circuit 8 ... Time difference detection circuit 9 ... … Differential amplifier circuit 10 …… Low-pass filter a …… Reproduction analog signal c …… Reproduction level signal f …… Delay level signal g …… Clock signal T ₁ … Rise delay time T ₂ … Fall delay time T ₄ …… Rise time difference T ₅ …… Rise time difference

Claims (1)

(57) [Claims] 1. An information detecting means for detecting information stored in a storage device to output a reproduced analog signal, and detecting a rising edge and a falling edge of the reproduced analog signal to detect 2
Output a playback level signal which is a digital signal of the value 2
Quantizing means, generating a delay level signal by delaying the rising time and the falling time of the reproduction level signal with different delay times,
And a variable delay means capable of changing the delay time thereof, a clock generation circuit for outputting a clock signal phase-locked with the delay level signal, and a data discrimination for discriminating the delay level signal at the timing of the clock signal. A circuit, the rise time difference is obtained by detecting the time difference between the rise time of the delay level signal and the reference position of the clock signal,
And a time difference detecting means for detecting a time difference between the falling time of the delay level signal and a reference position of the clock signal to obtain a falling time difference, and a time difference difference for obtaining a difference between the rising time difference and the falling time difference. A read circuit of a storage device, comprising: a detection unit, and controlling the different delay times so as to reduce the difference.