JP2673850B2 - A computer that runs a microtest program - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer capable of continuously executing a plurality of microtest programs. The micro test program is used to test a device or the like controlled by the micro program.

[0002]

2. Description of the Related Art FIG. 13 is a diagram for explaining a conventional method of executing a micro test program. In step S1,
The operator instructs the microtest program to be executed. In step S2, the control program loads the instructed microtest program onto the MS (main memory). In step S3, the control program sends the loaded microtest program onto the CS (control memory) using a special interface.
In step S4, execution of the sent micro test program is started. In step S5, IMPL / IPL is started at the same time when the execution of the microtest program is completed.

[0003]

In the conventional method of executing a micro test program, only one micro test program can be executed by one start, and IMPL / IPL is executed each time the start is executed. It took a lot of time to run the test. The present invention was created in view of this point, and an object of the present invention is to enable a plurality of microtest programs to be continuously executed by one start-up.

[0004]

FIG. 1 is a diagram illustrating the principle of the present invention. A computer for executing the microtest program according to claim 1, wherein an external storage means (10) for initial microprogram loading in which a microprogram for executing a microcontrol program and a macro instruction is stored.
An external storage means (11) for initial program loading which stores a macro level control program, a control storage (3) on which a micro program is loaded and a main storage (3) on which a macro level control program is loaded. 4), when the system is reset, the microprogram of the initial microprogram loading external storage means (10) is loaded into the control storage (3), and then the initial program loading external storage means (10). It can be accessed from both the instruction execution processor (1) that loads the control program in 11) into the main memory (4), the microprogram in the control memory (3) and the control program in the main memory (4), and a system reset is possible. Contains a shared memory (7) whose contents are not destroyed even if executed, and a micro test program A computer for executing a micro test program, comprising an external storage means (12) for a micro test program, wherein a macro level control program is added to the execution instruction when the execution instruction of the micro test program is input. It is configured to edit the execution control information based on the specified parameters, write the edited execution control information to the shared memory (7), and reset the system after the writing is completed. ), The microtest program specified by the execution control information is read from the external memory means for microtest program (12), loaded into the control memory (3), and the loaded microtest program is executed. It is characterized by that.

A computer for executing the micro test program according to claim 2 is the computer for executing the micro test program according to claim 1, wherein the micro test program, when an error is detected, notifies the micro control program of an error occurrence. The micro control program is characterized by being configured to write error information in the shared memory (7) when the error occurrence is notified.

A computer for executing the microtest program according to claim 3 is the computer for executing the microtest program according to claim 2, wherein the macro-level control program refers to the shared memory (7) and stores error information. If it is, the error information is output to the outside.

[0007]

The operation of claim 1 will be described. When the IMPL and IPL are completed, the control memory 3 stores a microprogram required to execute a macro instruction (synonymous with a machine language instruction), and the main memory 4 stores a control program.

In this state, when the operator designates the microtest program name or the schedule table name or the attachment name to instruct the execution of the microtest program, the control program designates the microtest program to be executed. Information is created, this is written in the shared memory 7, and the system is reset after the writing is completed.

When the system is reset, the micro control program is read from the initial micro program loading external storage means 10 and loaded into the control storage 3. When the loading of the micro control program is completed, the execution of the micro control program is started. The micro control program refers to the shared memory 7, and when the execution control information is stored, the micro test program designated by the execution control information is read from the micro test program external storage means 12 and loaded into the control storage 3. To do.

When the micro test program is loaded into the control memory 3, this micro test program is executed. When the execution of all the microtest programs specified by the execution control information of the shared memory 7 is completed, IMPL is restarted and then IPL is performed.

The operation of claim 2 will be described. When the micro test program detects an error during execution, it notifies the micro control program that an error has occurred. When the error occurrence is notified, the micro control program writes the error information in the shared memory 7.

The operation of claim 3 will be described. When the control program is loaded into the main memory 4 and activated,
Whether or not the error information is written in the shared memory 7 is checked, and if it is written, the error information is displayed on the display.

[0013]

FIG. 2 is a diagram showing a hardware configuration example of a computer system to which the present invention is applied. In the figure, 1
Is a main processor, 2 is an arithmetic execution unit of the main processor, 3 is a control memory, 4 is a main memory, 5 is a power supply control unit, 6 is a central processing unit of the power supply control unit, and 7 is a shared memory. . The system processor 1 executes an instruction. The arithmetic execution unit 2 performs arithmetic operations and accesses to I / O devices according to the instructions of the microprogram. A micro program is stored in the control memory 3, and a macro program is stored in the main memory 4. When the system is reset, IMPL execution is started, a microprogram or the like necessary to execute a macro instruction (machine language instruction) is loaded into the control memory 3, then IPL execution is started, and the macro is started. A control program (macro level control program) is loaded into the main memory 4. The power supply control unit 5 controls the power supply of the system. The shared memory 7 can be accessed by both the microprogram of the control memory 3 and the control program of the main memory 4. Even if the system is reset, the contents of the shared memory 7 will not be destroyed.

FIG. 3 is a diagram for explaining the execution of the microtest program according to the present invention. The macro control program writes the execution control information of the microtest program in the shared memory. The execution control information is a microtest program name, a schedule table name or an attachment name (Fig. 2 (a)). You can think of a schedule table as a sequence of test names to be run. There are various types of attachments. For example, when an attachment name dedicated to a display is written, a plurality of micro test programs for testing this attachment are executed.

The macro control program does a system reset. When a system reset occurs, the microcontroller program is first loaded into control store. The micro control program reads the execution control information in the shared memory and executes the micro test program according to the contents (FIG. 2 (b)). If the execution control information is not written in the shared memory, the micro control program starts IMPL / IPL.

When all the tests are completed and there is an error, the micro control program writes the error information in the shared memory and executes IMPL / IPL (FIG. 2 (c)).
If there is an error, the micro test program requests the micro control program to write the error information, and the micro control program writes the error information to the shared memory. After the IMPL / IPL is finished, the control program of the main memory refers to the shared memory, and if there is error information, a process for displaying it on the display is performed.

FIG. 4 is a diagram for explaining the processing flow of the present invention. In step S1, the operator gives an instruction to execute the microtest program. In step S2, the control program (macro level control program) is
The execution control information is edited based on the information specified by the operator, written in the shared memory, and the system is reset.

In step S3, the micro control program is loaded into the control memory, and the micro control program reads the execution control information from the shared memory. In step S4, the micro control program loads the micro test program on the control memory based on the execution control information and executes it. In step S5, when all the micro test programs have been executed, the micro control program starts IMPL / IPL.

A method of instructing execution of the Micrototos program will be described. Screen displayed by the macro control program on the display device (hereinafter referred to as monitor screen)
Input the following command at. MICRO operand

The following are the operands of the MICRO command.・ Program name (Example of input format'MICRO ISS
WST1 ') Specify when you want to execute the program by itself. The program name is the microtest program name. -Device name (example of input format "MICRO CPU") Specify when executing all the TETOS programs for the device to be diagnosed. In the above example, all the microtest programs facilitated to diagnose the CPU are executed.

Group name (example of input format'MICR
O GROUP 1 ') Several types of programs are grouped together in advance and designated when executing a microtest program belonging to the group.・ AUTO (Example of input format'MICRO AUT
O ') Specified when executing the test program for all devices connected to the main device to be executed. At this time, the micro control monitor (synonymous with the micro control program) automatically recognizes the connected device and activates the micro test program based on the information.

FIG. 5 is a diagram showing an example of execution control information.
The area for storing the execution control information is composed of a mode information field, a logging specification field, a loop count field, and an input command operand field. In the mode information field, the test mode of the micro system program is stored in hexadecimal. 01: All device test 02: Group name designation 03: Device name designation 04: TP name designation

Logging specification information is stored in the logging specification field. 00: When an error occurs, the error occurrence is indicated by a lamp or the like of the main unit and the operation is stopped. 01: IPL the macro control monitor when an error occurs
Then, request the macro control monitor to display the error information. The number of executions of the test program is stored in the loop number field. In the operand field of the command, the operand of the MICRO command, namely'AU
TO '/ device name / TP name / group name is stored.

FIGS. 6, 7 and 8 are views for explaining the processing flow from system reset. Step S1
So ROM is the IMPL microprogram loader
Read from the device. In step S2, the micro program loader reads the micro control monitor from the IMPL device.

In step S3, the micro-control monitor starts execution. In step S4, it is checked whether or not there is an instruction to execute the microtest program. If NO, continue IMPL, and if YES, proceed to step S5. In step S5, it is checked whether the mode information is hexadecimal 01 (all device designation). If YES, step S
9, the process proceeds to step S6 if NO.

In step S6, it is checked whether or not the mode information is hexadecimal 02 (group name designation). If YES, then proceed to step S10; if NO, proceed to step S10.
Go to 7. In step S7, the mode information is 0 in hexadecimal.
Check whether it is 3 (device name designation). If YES, the process proceeds to step S11, and if NO, the process proceeds to step S8.

In step S8, it is checked whether or not the mode information is hexadecimal 04 (designation of program name). If YES, the process proceeds to step S12, and if NO, the IMPL is continued. In step S9, the device is automatically recognized and the program to be executed is determined. In step S10, the programs belonging to the designated group are extracted. Step S11
Then, the program for the designated device is determined. In step S12, the program or program sequence is executed.

In step S13, it is checked whether or not there is an error. In the case of YES, the process proceeds to step S15 and N
In the case of O, the process proceeds to step S14. In step S14, it is checked whether or not the loop has been executed the designated number of times. YES
If NO, continue IMPL; if NO, step S1
Return to 2. In step S15, the error information is edited,
Write to shared memory. Then, the IMPL is continued.

9 and 10 are views for explaining the processing flow of the macro control program. Initially, the operation waits for an input from the operator, and when there is an input from the operator, the process of step S1 is performed. In step S1, it is checked whether or not the instruction is a microtest program execution instruction. If YES, the process proceeds to step S2, and if NO, the process proceeds to another process. In step S2, it is checked whether the test program name is designated. If yes, then continue with step S7; if no, continue with step S3.

In step S3, it is checked whether the device name is designated. If YES, the process proceeds to step S8, and if NO, the process proceeds to step S4. In step S4, it is checked whether the group name is designated. If yes, then continue with step S9; if no, continue with step S5. In step S5, it is checked whether all devices are designated. If YES, the process proceeds to step S10, and if NO, the process proceeds to step S6.
In step S6, processing for the parameter error is performed.

In step S7, the execution mode is set to 04 (1
Hexadecimal) and write the operand in the shared memory as the test program name. In step S8, the execution mode is set to 03 (hexadecimal), and the device name in the operand is written in the shared memory. In step S9, the execution mode is set to 02.
(Hexadecimal) and the group name in the operand is written in the shared memory.

In step S10, the execution mode is set to 01.
(Hexadecimal), and the character string of "AUTO" is written in the shared memory. In step S11, the macro control monitor resets the system. In step S12, the ROM
Starts IMPL.

11 and 12 are diagrams for explaining the operation of the system after the system reset. Step S1
Then, the microprogram loader is loaded by the ROM. In step S2, the micro control monitor is loaded by the micro program loader, and the micro control monitor is executed. In step S3, the micro test program is executed by the micro control monitor.

In step S4, the firmware is loaded by the micro control monitor. Step S
At 5, the IPL boot is loaded by the firmware and the IPL boot is executed. In step S6, the IPL program is loaded by the IPL boot.

In step S7, the IPL program loads the control program and transfers control to the control program. In step S8, the control program checks whether there is error information in the shared memory. In the case of YES, the process proceeds to step S9, and in the case of NO, the process proceeds to step S10. In step S9, the control program displays error information. In step S10, the operator waits for input (initial state).

[0036]

As is apparent from the above description, according to the present invention, (a) a plurality of microtest programs can be scheduled and executed at one time, so that the diagnosis time can be shortened. (b) When an error is detected during the test, by writing the error information in the shared memory, it is possible to reliably collect the error information and reduce the burden such as error logging. A remarkable effect can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing a hardware configuration example of the present invention.

FIG. 3 is a diagram illustrating execution of a microtest program according to the present invention.

FIG. 4 is a diagram illustrating a processing flow of the present invention.

FIG. 5 is a diagram showing an example of execution control information.

FIG. 6 is a processing flow (1) from a system reset.

FIG. 7 is a processing flow (2) from the system reset.

FIG. 8 is a processing flow (part 3) from system reset.

FIG. 9: Processing flow of macro control program (No. 1)
It is.

FIG. 10 is a processing flow (No. 2) of the macro control program.

FIG. 11 is an operation (1) of the system after the system reset.

FIG. 12 is a second operation of the system after the system is reset.

FIG. 13 is a diagram illustrating a method of executing a conventional microtest program.

[Explanation of symbols]

 1 processor system 2 processor execution unit 3 control memory 4 main memory 5 power supply control unit 6 power supply control unit central processing unit 7 shared memory

Claims (3)

(57) [Claims] 1. An external storage means (10) for initial microprogram loading, which stores a microcontrol program and a microprogram for executing a macro instruction.
And an external storage means (11) for initial program loading in which a macro level control program is stored, and a control storage (3) in which a micro program is loaded
And a main memory (4) into which a macro-level control program is loaded, and when the system is reset, the microprogram in the external memory means (10) for initial microprogram loading is controlled and stored (3). An instruction execution processor (1) for loading the control program of the external storage means (11) for initial program loading into the main memory (4), and a microprogram and main memory (4) of the control memory (3). Shared memory that can be accessed by both control programs and whose contents are not destroyed even after a system reset
A computer for executing a microtest program, comprising a microtest program external storage means (12) for storing a microtest program, wherein the macro-level control program is an instruction for executing the microtest program. When is input, edit the execution control information based on the parameter added to the execution instruction, write the edited execution control information to the shared memory (7), and reset the system after writing. The micro control program is configured to read the micro test program specified by the execution control information of the shared memory (7) from the micro test program external storage means (12), load it into the control storage (3), and load the loaded micro control program. Characterized by being configured to perform the process of executing the test program Computer to run the micro-test program to be. 2. The micro test program, when an error is detected, notifies the micro control program of the error occurrence, and when the micro control program is notified of the error occurrence, the micro control program sends the error information to the shared memory (7). The computer for executing the microtest program according to claim 1, wherein the computer is configured to perform a writing process to the computer. 3. The macro-level control program is configured to refer to the shared memory (7) and output the error information to the outside when the error information is stored. A computer that executes the microtest program according to claim 2.