JP2671753B2 - Prescaler - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a prescaler for dividing an AC signal in the microwave and millimeter wave bands, and more particularly to a prescaler suitable for a monolithic integrated circuit (IC) while having wide band characteristics.

[0002]

2. Description of the Related Art A conventional prescaler of this type divides an ultra high frequency AC signal in the microwave or millimeter wave band into two or more by a dynamic type frequency dividing circuit which is a frequency dividing circuit which operates only with an AC signal. After the frequency is divided by the frequency dividing ratio, the frequency is further divided by a static type frequency dividing circuit composed of a logic circuit to a predetermined frequency dividing ratio. In general, dynamic frequency dividing circuit, even in the super high frequency exceeding the frequency capable of dividing the static divider far, is characterized in that you dividing operation at relatively low power consumption.

Here, the dynamic type frequency divider circuit includes
Wave number converter (mixer) and Gilbert cell multiplier
Analog multipliers such as Gilbert multipliers known as Ya
And using a transfer gate type frequency divider
Can be. Dynamic frequency division using a frequency converter
The route is, for example, Japanese Patent Laid-Open No. 60-25310 (hereinafter referred to as "public").
It is shown in Figure 1 of Bulletin 1). This dynamic type
The circuit is a signal input terminal for inputting an AC signal of frequency 2f.
And a frequency output having a signal output end and a local oscillation signal input end.
The converter and the signal output end are connected and the pass band is
Band pass filter near the wave number f and band pass filter
Frequency conversion by amplifying an AC signal of frequency f from the
And an amplifier which feeds back to the local oscillation signal input terminal of the container.
A frequency converter, bandpass filter and amplifier
The return loop satisfies the condition of positive feedback at frequency f.
If you set the circuit conditions like this,
The circuit is the output of the amplifier, that is, the frequency converter
A divide-by-2 circuit that produces an AC signal of frequency f at the signal output end
Become.

Gilbert multiplier type dynamic frequency division
The circuit is disclosed in, for example, Japanese Examined Patent Publication No.
As shown in Fig. 2 of report 2) as a double balanced modulator.
Then, the Gilbert multiplier is used in the divide-by-2 circuit. Gilber
The multiplier has first and second transistors of the same configuration.
The differential pair (bi-differential pair) and the first and second differential pair
The transistor emitter to the collector of the two transistors
The basic element is the third differential pair of transistors connected to each other.
And In this Gilbert multiplier,
And corresponding transistor bases of the second differential pair
Connect each other for feedback of AC signal,
Input a 2f AC signal to the paired transistor bases.
When applied, the transistors of each of the first and second differential pairs
・ The collector has an AC signal of frequency f superimposed on the DC component.
Occurs, that is, this Gilbert multiplier is a divide-by-2 circuit
To work as. Dyna using this Gilbert multiplier
For the Mick type frequency dividing circuit, an equivalent circuit in the case of frequency dividing by 2 is disclosed
Can be represented by the circuit of FIG.

Transfer gate type dynamic type
The circuit is disclosed in, for example, Japanese Patent Laid-Open No. 2-37837 (hereinafter,
Publication 3) and FIG. 2 of Publication 2. this
These dynamic frequency dividers are
A feedback type with an inverter and a buffer circuit connected in a ring
It is a frequency divider.

In addition, the static type frequency divider circuit is capable of wide band operation in principle, and if the rising and falling times of the input AC signal are sufficiently short, a low frequency input AC It is characterized by stable frequency division even for signals. Note that the static type frequency divider circuit requires extremely large power consumption in order to perform the frequency dividing operation at the ultrahigh frequency like the dynamic type frequency divider circuit.

Therefore, the conventional prescaler uses a dynamic frequency dividing circuit in the front stage to perform the frequency dividing operation of an ultrahigh frequency signal with low power consumption, and uses a static type frequency dividing circuit in the rear stage to provide a wide band. A stable frequency division operation is performed.

[0008]

In this conventional prescaler, in the dynamic frequency divider circuit, the input AC signal is limited to a frequency band of octave or less in principle, and a narrower frequency band is required for realization. It has the drawback of being limited to. Therefore, this conventional prescaler exhibits excellent characteristics when the AC signal is in an ultrahigh frequency band, but has a drawback that frequency division cannot be performed when the AC signal has a low frequency. . Therefore,
This prescaler has poor versatility, and when a prescaler that operates over a wide band from low frequencies to ultrahigh frequencies is required, it is necessary to prepare multiple types of prescalers having different operable frequency bands. . This condition compels the prescaler, which is often monolithically integrated and used, to produce various small quantities, which makes it difficult to reduce the price of the prescaler due to the effect of mass production.

[0009]

The prescaler of the present invention is divided by a dynamic frequency dividing circuit for dividing a first AC signal received from a first input terminal by a first dividing ratio. The second AC signal and the second from the second input terminal
Receiving any of the AC signals of the
And a capacitor for coupling the frequency-divided first AC signal from the output terminal of the dynamic frequency dividing circuit to the input terminal of the static frequency dividing circuit. And a power source for the dynamic divider circuit and a power source for the static divider circuit,
Supplied independently of each other.

Further, the prescaler of the present invention is composed of a monolithic integrated circuit, the dynamic frequency dividing circuit divides the first AC signal by a Gilbert type multiplying circuit, and the static type frequency dividing circuit. , A D flip-flop circuit may be used to divide the received AC signal.

[0011]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

Referring to FIG. 1, the prescaler IC 10
Is a silicon monolithic IC formed on a silicon semiconductor substrate. The input terminal 1 receives an AC signal S1a which is a microwave band or millimeter wave band ultra high frequency signal. The AC signal S1a is coupled to the input end of the dynamic frequency dividing circuit 6 by a capacitor C1 composed of two conductor films sandwiching a silicon nitride film (SiN). The dynamic frequency dividing circuit 6 produces at its output end an AC signal S2 obtained by dividing the frequency of the AC signal S1a by two. AC signal S
2 is coupled to the input terminal of the static frequency divider circuit 7 by a capacitor C2 having the same configuration as the capacitor C1. The static frequency divider circuit 7 produces at the output terminal 5 an AC signal S4a obtained by dividing the frequency of the AC signal S2 by four. Further, the input terminal 2 receives the alternating current signal S1b in the microwave band and supplies the alternating current signal S1b to the input end of the static frequency divider circuit 7.

Here, the prescaler IC 10 is provided with the power supply terminal 3 of the dynamic type frequency dividing circuit 6 and the power supply terminal 3 of the static type frequency dividing circuit 7 independently of each other. When the voltage E1 of the power supply power supplied from the power supply terminal 3 and the voltage E2 of the power supply power supplied from the power supply terminal 4 are the same voltage depending on the circuit conditions of each of the dynamic frequency divider circuit 6 and the static frequency divider circuit 7. May also have different voltages. Now, when the AC signal S1a is received at the input terminal 1, the input terminal 2 is opened and the power supply terminal 3 and the power supply terminal 4 are opened.
Power supply power is supplied from each of them to operate the dynamic frequency dividing circuit 6 and the static frequency dividing circuit 7. On the other hand, when receiving the AC signal S1b at the input terminal 2, the input terminal 1 and the power supply terminal 3 are opened, the power supply power is supplied only from the power supply terminal 4, and only the static frequency divider circuit 7 is operated. When receiving the AC signal S1b at the input terminal 2,
The case of opening the monitor power supply terminal 3, a static divider 7, the DC blocking effect of capacitors C2, off
The AC signal S1b is frequency-divided by 4 without changing the bias voltage of the lip-flops FF1 and FF2 from the time of operation of the dynamic frequency divider circuit 6, and the AC signal S4a is generated at the output terminal 5. When the operation of the dynamic frequency dividing circuit 6 is stopped while receiving the AC signal S1b,
The prescaler IC 10 not only reduces the power consumption, but also can stably operate the static frequency divider circuit 7 without being interfered by the free-running oscillation of the dynamic frequency divider circuit 6 or noise generation.

The capacitor C1 may be externally attached to an external circuit, that is, to the input side of the input terminal 1 of the prescaler IC10. However, the required capacitance value of the capacitor C1 (and C2) can be sufficiently built in the prescaler IC 10 even if the lower limit of the operating frequency is taken into consideration. Therefore, it is better to mount the capacitor C1 in the prescaler IC 10 in consideration of generation of parasitic reactance due to external attachment and usability of the prescaler IC.

The capacitor C2 is, as described above,
AC signal S2 from the output terminal of the dynamic frequency dividing circuit 6
Is transmitted to the input terminal of the static frequency divider circuit 7.
The output terminal of the dynamic frequency divider 6 and static
The input terminal of the mold frequency dividing circuit 7 is cut off from the direct current. About this content
In detail, first, the capacitance value of the capacitor C2
AC signal S2 is sufficiently transmitted to the static frequency divider 7
You need a value that you can. In addition, in this embodiment,
The AC signal S2 is applied to the output terminal of the dynamic frequency divider circuit 6
DC voltage is superimposed, static type frequency divider 7
The input terminal is suitable for frequency division operation with AC signal input.
The DC bias voltage that gives the logical threshold is set.
You. Therefore, the capacitor C2 having the DC blocking effect is
The dynamic frequency dividing circuit 6 has two operating and non-operating states.
Even if the DC voltage at the output end changes depending on the
The change in the flow voltage is controlled by the input terminal DC of the static divider circuit 7.
The operation of the static frequency divider circuit 7 is not affected by the voltage.
It also has the effect that it can be stabilized .

FIG. 2 shows the prescaler IC 1 of this embodiment.
FIG. 6 is a diagram showing input sensitivity characteristics when a sine wave signal is input to the dynamic frequency divider circuit 6 and the D-type flip-flop (FF) that form 0 .

Referring to FIG. 1 and FIG. 2 together, the dynamic frequency dividing circuit 6 is based on the circuit of the above-mentioned publication 2.
In double-differential Gilbert cell Multiplier to be formed
An analog multiplier M1 is used. Note that analog
Although the multiplier M1 is shown as an equivalent circuit,
A bandpass filter and a local oscillator signal input terminal are connected.
Illustration of the amplifier and the amplifier is omitted. Analog multiplier M1
Receives the AC signal S1a at a first input end (a signal input end, that is, an input end of the dynamic frequency dividing circuit 6), and outputs a signal output end (that is, an output end of the dynamic frequency dividing circuit 6). ) Is fed back to the second input terminal (local oscillation signal input terminal) as a local oscillation signal, a part of the AC signal S2 generated in
An AC signal S2 is obtained by dividing the frequency 2f of the AC signal S1a into two half the frequency f. The operating frequency range of the dynamic frequency dividing circuit 6 is determined by the phase characteristic of the feedback loop of the analog multiplier M1, that is, the delay time, and the octave band is the limit even if it is wide (see FIG. 2). As the dynamic frequency dividing circuit 6, above
As described above, it may be a feedback-type frequency divider circuit (a single unit is, for example, a product name μPG504B integrated circuit, manufactured by NEC Corporation) in which a transfer gate, an inverter, and a buffer circuit are connected in a ring shape.

The static type frequency divider circuit 7 is formed by cascading master-slave type D flip-flops FF1 and FF2 which form a frequency divider circuit in two stages in two stages, and selects one of the AC signals S2 and S1b (hereinafter , S2)
AC signal S4a, which is obtained by dividing by four, is generated at output terminal 5. The flip-flop FF1 receives the AC signal S2 at the clock terminal C and feeds back the signal S3b generated at the inverting output terminal Q2 to the data terminal D to output an AC signal S3a obtained by dividing the frequency of the AC signal S2 by two. It occurs in Q1.
Similarly, the flip-flop FF2 receives the AC signal S3a at the clock terminal C and feeds back the signal S4b generated at the inverting output terminal Q2 to the data terminal D, thereby dividing the frequency of the AC signal S3a by two. Occurs at the output terminal Q1, that is, at the output terminal 5.

[0021] Here, each of the frequency divider circuits is configured.
Suitable for the flip-flops FF1 and FF2,
DC bias on signal input to create a logical threshold
Voltage is being applied. This logical threshold is set to 0 by design
It is also possible to set it to V. And flip flip
FF1 and FF2 have the logic of the input signal level.
If it is fixed near the threshold value, the logical state is not fixed.
Start self-oscillation. Further, the flip-flops FF1 and FF2 are connected to the AC signal S2 supplied to the clock terminal C.
If the waveforms (rising and falling) of S3a and S3a are gentle, the input signal stays near the above logic level.
Because it takes a long time, it may oscillate in a free-running oscillation state and cause malfunction.
You. However, the flip-flops FF1 and FF2 are
If the signals S2 and S3a are rectangular waves having steep waveforms, the frequency division operation is essentially performed in a very wide frequency range (FIG. 2).
reference).

In the conventional prescaler, the output terminal of the analog multiplier M1 and the input terminal of the flip-flop FF1 are directly coupled without passing through the capacitor C2, and in general, an analog circuit is provided by a level shift circuit and a bias circuit. The DC potentials at the output end of the multiplier M1 and the input end of the flip-flop FF1 are matched. However, in the prescaler IC 10, it is not necessary to match the DC potential, and the static frequency divider circuit 7 can be normally operated without affecting the DC potential of the circuit even when power is not supplied to the dynamic frequency divider circuit 6. be able to.

In the prototype dynamic frequency divider circuit 6, if the level of the sine wave AC signal S1a is -5 dBm,
The frequency division operation is performed in the frequency range of approximately 6.3 GHz to 11.8 GHz. The AC signal S2 at this time is an analog signal.
Due to the high frequency band limitation of the calculator M1, a sinusoidal waveform with a lot of distortion
It has a waveform (a signal superimposed on DC). The prototype flip-flops FF1 and FF2 are
About 0.8GHz to 7.6GH when sine wave signal is input
Frequency division operation is performed in the z frequency range. Further, since the frequency-divided AC signals S1a and S3a are signals close to a rectangular wave,
The lower limit operating frequency range of the flip-flops FF1 and FF2 is wider than the range shown in FIG.

Since the flip-flop FF1 operates at the frequency obtained by dividing the frequency of the flip-flop FF2 by two,
The maximum operating frequency is 3.8G, which is about half that of flop FF1.
Since the frequency becomes Hz, the power consumption can be reduced as the operating frequency decreases. The power supply voltage E1 of the dynamic frequency dividing circuit 6 and the power supply voltage E2 of the static frequency dividing circuit 7 are 5V, and the power supply current of the dynamic frequency dividing circuit 6 at this time is the power supply current of the static frequency dividing circuit 7. It is about 1.2 times. If the static frequency divider circuit has the same upper limit operating frequency of 11.8 G as the dynamic frequency divider circuit 6,
According to the simulation, in order to realize Hz, a power supply current three times or more that of the dynamic frequency dividing circuit 6 is required.

In the prescaler IC 10, the frequency of the AC signal S1a supplied from the input terminal 1 to the dynamic frequency dividing circuit 6 is 6.3 GHz to 11.8 GH.
When z, the frequency to the flip-flop FF1 is 3.15.
AC signal S2 of GHz to 5.9 GHz is supplied,
The AC signal S3a having a frequency of 1.575 GHz to 2.95 GHz is supplied to the flip-flop FF2, and the output terminal 5 has a frequency of 0.7875 GHz to 1.475.
An AC signal S4a of GHz is generated. On the other hand, the frequency from the input terminal 2 to the static frequency divider 7 is 1.0 GHz.
Through 7.6 GHz AC signal S1b may be provided. In other words, this prescaler IC10 is 1.0GH
The input AC signals S1a and S1b having a continuous frequency range of z to 11.8 GHz and a wide band can be divided by one kind of integrated circuit, and this frequency range is more than twice the operable frequency of the conventional prescaler. is there.

Prescaler IC1 of the embodiment described above
In the case of 0, the frequency division ratio of the dynamic frequency division circuit 6 is 2, and the frequency division ratio of the static frequency division circuit 7 is 4. However, the frequency division ratios of the frequency division circuit 6 and the frequency division circuit 7 are different from each other. Of course, it is possible to use the ratio. The change of the frequency division ratio is performed by the unit frequency division circuit built in the dynamic frequency division circuit 6,
That is, the number of cascade connections of the analog multiplier M1 is increased to change the number of cascade connections of the unit frequency divider circuit, that is, the D-type flip-flop, incorporated in the static frequency divider circuit 7. In this case, of course, the frequency of the AC signal supplied to these unit dividers must be within the operating frequency range of these unit dividers.

[0026]

As described above, in the prescaler according to the present invention, an AC signal to be frequency-divided by cascade-connecting a dynamic frequency dividing circuit and a static frequency dividing circuit that supply power independently of each other through a capacitor. Can be supplied to both the dynamic type frequency dividing circuit and the static type frequency dividing circuit, so that the frequency dividing operation can be performed with a small power consumption over a wide frequency range of the octave band or more with only one type of circuit.

Further, the prescaler of the present invention is excellent in versatility because it can perform frequency division operation over a wide band with only one type of circuit, and also has an effect of facilitating cost reduction due to mass production effect.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a dynamic frequency divider circuit and a D-type flip-flop (FF) included in the prescaler IC of this embodiment.
6 is a diagram showing input sensitivity characteristics when a sine wave signal is input in FIG.

[Explanation of Codes] 1, 2 Input Terminals 3, 4 Power Supply Terminals 5 Output Terminals 6 Dynamic Type Frequency Division Circuits 7 Static Type Frequency Division Circuits 10 Prescaler ICs C1, C2 Capacitors FF1, FF2 D Type Flip Flops M1 Analog Multipliers

Claims (3)

(57) [Claims] 1. A dynamic type frequency dividing circuit for dividing a first AC signal received from a first input terminal by a first frequency division ratio, the divided first AC signal and second frequency dividing circuit. A static type frequency dividing circuit which receives one of the second AC signals from the input terminal and divides the received AC signal by a second frequency dividing ratio, and frequency division from the output terminal of the dynamic type frequency dividing circuit. And a capacitor that couples the generated first AC signal to an input terminal of the static frequency divider circuit, and the power source of the dynamic frequency divider circuit and the power source of the static frequency divider circuit are independently supplied from each other. A prescaler that is characterized by being. 2. The prescaler according to claim 1, which is a monolithic integrated circuit. 3. The dynamic divider circuit divides the first AC signal by a Gilbert multiplier circuit, and the static divider circuit divides the received AC signal by a D flip-flop circuit. The prescaler according to claim 2, wherein frequency division is performed.