JP2662983B2 - Timing calibration method for IC test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention compares an output pattern of a driver with a reference level at a reference timing by a comparator, compares the output of the comparator with an expected value by a logical comparator, and compares the output. The present invention relates to a timing calibration method for an IC test apparatus that adjusts a pattern generation timing according to a result.

[Prior Art] In a conventional IC test apparatus, as shown in FIG. 1, a flip-flop 14 is set and reset by the outputs of variable delay circuits 12 and 13 in a waveform shaping unit 11, and a pattern is created. Is supplied to the driver 16 of the driver channel 15, and the output pattern of the driver 16 is switched.
17 to the device test board 18
Device 19 is tested.

At the time of timing calibration, the output pattern of the driver 16 of each driver channel 15 is supplied to the multiplexer 23 of the timing comparison unit 22 through the switch 21, and one pattern selected by the multiplexer 23 is used as the reference comparator 24.
Is compared with the reference level, and the comparison result is output to the logical comparator 25 at the reference timing and compared with the expected value. The pattern generation timing is adjusted by adjusting the delay amount of the variable delay circuits 12 and 13 according to the comparison result of the logical comparator 25, and
For the pattern generation timing of one driver channel,
Pattern generation timings of other driver channels are aligned.

[Problem to be Solved by the Invention] Conventionally, timing calibration when a capacitive load is applied to a driver has not been performed. If there is a capacitor 26 to a particular pin P ₁ of the IC element 19, as shown in Figure 2,
Curve of the rising third view of the specific pin P ₁ of the pattern 27
Next, the rise of the pattern of the pins P ₂ has no capacity curve 28
Then, there is a shift between these curves, so-called skew appears. Also, when a capacitive load is applied to all the pins of the IC element 19, all the outputs of the driver appear to be late due to dullness, resulting in skew between the driver and the reference comparator.

[Means for Solving the Problems] According to the present invention, the timing difference between the waveform at the time of no load and the waveform at the time of the capacitive load is stored in a data file with respect to the capacitance value and the amplitude, and the capacitance and the amplitude given at the time of calibration are provided. And adjusts the reference timing accordingly.

"Examples" rising characteristic as shown in FIG. 4, according to the present invention, the timing difference between the waveforms at no load for each of the waveform when equipped with a capacitive load falling characteristics (T _S10 through T _S90 , T
_{R10 to TR90} ) are stored in data files for various capacitance values and amplitudes _VAMP .

At the time of timing calibration, the data file is referred to based on the given capacity and amplitude, and the reference timing is adjusted accordingly.

For example, capacitance is 20pF, amplitude is L = 0V, H = 3V, and rise is 80
It is specified that the adjustment is made at% and the fall is made at 20%, and accordingly, T _S80 and T _R20 of the data file are read out, and the reference timing is advanced so that the delay amount is corrected in advance.

[Effect of the Invention] As described above, according to the present invention, a data file is read according to the capacity and amplitude given at the time of calibration, and the reference timing is determined according to the timing difference between the read no-load time and the read capacity time. Is adjusted, the skew described above can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a timing calibrator of an IC tester, FIG. 2 is a diagram showing an example in which a specific pin of an IC element has a capacitance, and FIG. 3 is a rising characteristic between a pin with a capacitance and a pin not attached. FIG. 4 is a diagram showing a timing difference between a waveform at the time of no load and a waveform at the time of capacitive load.

Claims (1)

(57) [Claims] An IC for comparing an output pattern of a driver with a reference level at a reference timing by a comparator, comparing an output of the comparator with an expected value by a logical comparator, and adjusting a pattern generation timing according to the comparison result. In the timing calibration method of the test equipment, the timing difference between the waveform under no load and the waveform under capacitive load is stored in a data file for the capacitance value and amplitude, and the above data file is referred to based on the capacitance and amplitude given during calibration. And adjusting a reference timing according to the timing.