JP2656740B2 - Manufacturing method of vertical field effect transistor - Google Patents
Manufacturing method of vertical field effect transistorInfo
- Publication number
- JP2656740B2 JP2656740B2 JP6265570A JP26557094A JP2656740B2 JP 2656740 B2 JP2656740 B2 JP 2656740B2 JP 6265570 A JP6265570 A JP 6265570A JP 26557094 A JP26557094 A JP 26557094A JP 2656740 B2 JP2656740 B2 JP 2656740B2
- Authority
- JP
- Japan
- Prior art keywords
- concentration
- region
- drain region
- base region
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 230000005669 field effect Effects 0.000 title claims description 3
- 239000012535 impurity Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 9
- 239000011159 matrix material Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Description
【０００１】[0001]
【産業上の利用分野】本発明は縦型電界効果トランジス
タ（以下縦型ＦＥＴと記す）の製造方法に関する。The present invention relates to a process for producing a vertical field effect transistor (hereinafter referred to as vertical FET).
【０００２】[0002]
【従来の技術】従来の縦型ＦＥＴの第１の例は、図２に
示すように、Ｎ+ 型のシリコン基板１の上に形成したＮ
型のドレイン領域２と、ドレイン領域２の上にゲート絶
縁膜３を介して形成したゲート電極４と、ゲート電極４
をパターニングして行列状に配置し形成した開孔部のド
レイン領域２内に形成したＰ型のベース領域１２と、ベ
ース領域１２内に形成したＮ+ 型のソース領域８と、ベ
ース領域１２の側面周囲を取囲んで形成した高濃度ドレ
イン領域５を備えて構成され、高濃度ドレイン領域５を
設けたことにより、ドレイン抵抗が小さくなり、オン抵
抗が低減できるという利点がある。A first example of a conventional vertical type FET, as shown in FIG. 2, was formed on the silicon substrate 1 of the N + -type N
A drain region 2, a gate electrode 4 formed on the drain region 2 via a gate insulating film 3, and a gate electrode 4.
Of a P-type base region 12 formed in the drain region 2 of the opening formed by patterning and forming a matrix, an N + -type source region 8 formed in the base region 12, and a base region 12. The high-concentration drain region 5 is formed so as to surround the periphery of the side surface. By providing the high-concentration drain region 5, there is an advantage that the drain resistance is reduced and the on-resistance can be reduced.
【０００３】なお、ゲート電極４を被覆する層間絶縁膜
９，ソース領域８およびベース領域１２とコンタクトす
るソース電極１０，シリコン基板１の裏面に接続するド
レイン電極１１がそれぞれ形成されている（特開昭６４
−５７６７５号公報参照）。[0003] An interlayer insulating film 9 covering the gate electrode 4, a source electrode 10 in contact with the source region 8 and the base region 12, and a drain electrode 11 connected to the back surface of the silicon substrate 1 are formed, respectively. Showa 64
-57675).
【０００４】しかし、この従来例では、モータのような
誘電性負荷を用いてスイッチング動作させる場合に、ド
レイン領域２とベース領域１２とソース領域８とで形成
される寄生トランジスタのために部分的に過大な電流が
流れて縦型ＦＥＴが破壊され易いという問題があった。However, in this conventional example, when a switching operation is performed using a dielectric load such as a motor, a parasitic transistor formed by the drain region 2, the base region 12, and the source region 8 partially causes the switching operation. There is a problem that an excessive current flows and the vertical FET is easily broken.
【０００５】この問題を解決する方法としてベース領域
内に高濃度ベース領域を形成して寄生トランジスタのベ
ース抵抗を極力小さくして寄生トランジスタを動作させ
難くする方法（特開昭６３−１３２４８１号公報参照）
がある。As a method of solving this problem, a method of forming a high-concentration base region in the base region to minimize the base resistance of the parasitic transistor and make it difficult to operate the parasitic transistor (see Japanese Patent Application Laid-Open No. 63-132481). )
There is.
【０００６】図３（ａ）〜（ｄ）および図４（ａ），
（ｂ）は従来の縦型ＦＥＴの第２の例の製造方法を説明
するための工程順に示した断面図である。FIG. 3A to FIG. 3D and FIG.
(B) is sectional drawing shown in order of process for demonstrating the manufacturing method of the 2nd example of the conventional vertical FET.
【０００７】まず、図３（ａ）に示すように、Ｎ+ 型の
シリコン基板１の上にエピタキシャル成長させたＮ型の
ドレイン領域２の上にゲート絶縁膜３を介して形成した
ゲート電極４をパターニングして行列状に配置した開孔
部を形成する。First, as shown in FIG. 3A, a gate electrode 4 formed via a gate insulating film 3 on an N-type drain region 2 epitaxially grown on an N + -type silicon substrate 1 is formed. Patterning is performed to form openings arranged in a matrix.
【０００８】次に、図３（ｂ）に示すように、ゲート電
極４をマスクとしてドレイン領域２の表面にＮ型不純物
をイオン注入しＮ+ 型の高濃度ドレイン領域５を形成す
る。Next, as shown in FIG. 3B, N-type impurities are ion-implanted into the surface of the drain region 2 using the gate electrode 4 as a mask to form an N + -type high-concentration drain region 5.
【０００９】次に、図３（ｃ）に示すように、ゲート電
極４をマスクとしてＰ型不純物を高加速エネルギーでイ
オン注入しＰ型の低濃度ベース領域６を形成し、低濃度
ベース領域６の周囲に高濃度ドレイン領域５が取囲むよ
うにする。Next, as shown in FIG. 3C, a P-type impurity is ion-implanted with high acceleration energy using the gate electrode 4 as a mask to form a P-type low-concentration base region 6, and the low-concentration base region 6 is formed. Is surrounded by the high-concentration drain region 5.
【００１０】次に、図３（ｄ）に示すように、低濃度ベ
ース領域６の中央部に選択的にＰ型不純物をイオン注入
してＰ+ 型の高濃度ベース領域７を形成する。Next, as shown in FIG. 3D, a P + -type high concentration base region 7 is formed by selectively ion-implanting a P-type impurity into the center of the low concentration base region 6.
【００１１】次に、図４（ａ）に示すように、高濃度ベ
ース領域７の周囲を取囲む低濃度ベース領域６の表面に
Ｎ型不純物を選択的にイオン注入しＮ+ 型ソース領域８
を形成する。Next, as shown in FIG. 4A, an N-type impurity is selectively ion-implanted into the surface of the low-concentration base region 6 surrounding the periphery of the high-concentration base region 7, and an N + -type source region 8 is formed.
To form
【００１２】次に、図４（ｂ）に示すように、ゲート電
極を含む表面に層間絶縁膜９を堆積してパターニング
し、コンタクトホールを形成し、コンタクトホールのソ
ース領域８および高濃度ベース領域７と接続するソース
電極１０と、シリコン基板１の裏面にドレイン電極１１
とを形成して縦型ＦＥＴを構成する。Next, as shown in FIG. 4B, an interlayer insulating film 9 is deposited and patterned on the surface including the gate electrode to form a contact hole, and the source region 8 and the high concentration base region of the contact hole are formed. 7, and a drain electrode 11 on the back surface of the silicon substrate 1.
To form a vertical FET.
【００１３】[0013]
【発明が解決しようとする課題】この従来の縦型ＦＥＴ
は、誘電性負荷に対する破壊耐量の向上のための高濃度
ベース領域を形成するために工程が増加し、複雑化する
という問題があった。SUMMARY OF THE INVENTION This conventional vertical FET
However, there is a problem that the number of steps is increased to form a high-concentration base region for improving the breakdown strength against a dielectric load, and the process is complicated.
【００１４】本発明の目的は、工程を簡略化してコスト
ダウンを実現できる縦型ＦＥＴの製造方法を提供するこ
とにある。An object of the present invention is to provide a method of manufacturing a vertical FET , which can simplify a process and realize cost reduction.
【００１５】[0015]
【００１６】[0016]
【課題を解決するための手段】 本発明の縦型ＦＥＴの製
造方法は、一導電型半導体基板上に形成した一導電型の
ドレイン領域の上にゲート絶縁膜を介して形成した多結
晶シリコン膜をパターニングし行列状に配置した開孔部
を有するゲート電極を形成する工程と、前記開孔部周囲
の前記ゲート電極の縁に沿って前記ドレイン領域の表面
に選択的に不純物をイオン注入して拡散し環状の一導電
型高濃度ドレイン領域を形成する工程と、前記ゲート電
極をマスクとして前記開孔部の前記高濃度ドレイン領域
を含む表面に不純物をイオン注入して逆導電型の深い高
濃度ベース領域および前記高濃度ベース領域内に逆導電
型の浅い環状の低濃度ベース領域を形成し且つ前記高濃
度ベース領域の外周に沿って接する前記高濃度ドレイン
領域を形成する工程と、前記低濃度ベース領域内に選択
的に不純物をイオン注入して一導電型のソース領域を形
成する工程とを含んで構成される。 A method of manufacturing a vertical FET according to the present invention is directed to a polycrystalline silicon film formed via a gate insulating film on a drain region of one conductivity type formed on a semiconductor substrate of one conductivity type. Patterning a gate electrode having openings arranged in rows and columns, and selectively ion-implanting impurities into the surface of the drain region along the edge of the gate electrode around the openings. A step of diffusing to form an annular one-conductivity-type high-concentration drain region; and ion-implanting impurities into the surface of the opening portion including the high-concentration drain region using the gate electrode as a mask. Forming a shallow annular low-concentration base region of the opposite conductivity type in the base region and the high-concentration base region, and forming the high-concentration drain region which is in contact with the periphery of the high-concentration base region; When configured to include a step of forming the low-concentration base region selectively source region of the one conductivity type impurity ions are implanted into.
【００１７】[0017]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【００１８】図１（ａ）〜（ｄ）は本発明の一実施例の
製造方法を説明するための工程順に示した断面図であ
る。FIGS. 1A to 1D are sectional views showing a manufacturing method according to an embodiment of the present invention in the order of steps for explaining the manufacturing method.
【００１９】まず、図１（ａ）に示すように、Ｎ型の高
不純物濃度（Ｎ+ 型）を有する単結晶のシリコン基板１
の上にエピタキシャル成長によりＮ型のドレイン領域２
を形成する。次に、ドレイン領域２の表面を熱酸化して
ゲート酸化膜を形成し、ゲート酸化膜の上にＣＶＤ法に
より多結晶シリコン膜を堆積し、多結晶シリコン膜およ
びゲート酸化膜を選択的に順次エッチングしてドレイン
領域２の表面に行列状に配置した開孔部を有するゲート
絶縁膜３およびゲート電極４を形成する。次に、開孔部
の周囲のゲート電極４の縁に沿ってドレイン領域３の表
面にＮ型不純物を選択的にイオン注入し環状の高濃度
（Ｎ+ 型）ドレイン領域５を形成する。First, as shown in FIG. 1A, a single-crystal silicon substrate 1 having an N type high impurity concentration (N + type) is formed.
N type drain region 2 by epitaxial growth on
To form Next, the surface of the drain region 2 is thermally oxidized to form a gate oxide film, a polycrystalline silicon film is deposited on the gate oxide film by a CVD method, and the polycrystalline silicon film and the gate oxide film are selectively sequentially formed. Etching is performed to form a gate insulating film 3 and a gate electrode 4 having openings arranged in a matrix on the surface of the drain region 2. Next, N-type impurities are selectively ion-implanted into the surface of the drain region 3 along the edge of the gate electrode 4 around the opening to form an annular high-concentration (N + -type) drain region 5.
【００２０】次に、図１（ｂ）に示すように、ゲート電
極４をマスクとして開孔部の高濃度ドレイン領域５を含
むドレイン領域２の表面にＰ型不純物を高加速エネルギ
ーでイオン注入し高濃度ドレイン領域５の一部の導電型
を反転させた浅い領域の（Ｐ型）低濃度ベース領域６と
深い領域の（Ｐ+ 型）高濃度ベース領域７とを同時に形
成する。ここで、低濃度ベース領域６の外周に接して環
状の高濃度ドレイン領域５が残される。Next, as shown in FIG. 1B, a P-type impurity is ion-implanted at a high acceleration energy into the surface of the drain region 2 including the high-concentration drain region 5 in the opening using the gate electrode 4 as a mask. A shallow (P-type) low-concentration base region 6 in which a part of the high-concentration drain region 5 is inverted in conductivity type and a deep (P + -type) high-concentration base region 7 are simultaneously formed. Here, the annular high-concentration drain region 5 is left in contact with the outer periphery of the low-concentration base region 6.
【００２１】次に、図１（ｃ）に示すように、開孔部の
低濃度ベース領域６内に選択的にＮ型不純物をイオン注
入してＮ+ 型のソース領域８を形成する。Next, as shown in FIG. 1 (c), selectively N-type impurity at a low concentration base region 6 of the opening portion by ion implantation to form an N + -type source region 8.
【００２２】次に、図１（ｄ）に示すように、全面にＣ
ＶＤ法によりＰＳＧ膜を堆積してパターニングし、ソー
ス領域８および低濃度ベース領域６，高濃度ベース領域
７の表面を共通に露出させるコンタクトホールを有する
層間絶縁膜９を形成する。次に、このコンタクトホール
を含む表面にスパッタ法でアルミニウム膜を堆積してソ
ース電極１０を形成し、シリコン基板１の裏面に蒸着法
によりドレイン電極１１を形成する。Next, as shown in FIG.
A PSG film is deposited and patterned by the VD method to form an interlayer insulating film 9 having a contact hole for commonly exposing the surfaces of the source region 8, the low-concentration base region 6, and the high-concentration base region 7. Next, a source electrode 10 is formed by depositing an aluminum film on the surface including the contact holes by sputtering, and a drain electrode 11 is formed on the back surface of the silicon substrate 1 by vapor deposition.
【００２３】[0023]
【発明の効果】以上説明したように本発明は、高濃度ド
レイン領域を形成した後、ドレイン領域と反対導電型の
不純物を高加速エネルギーでイオン注入し、深い接合面
を有する高濃度ベース領域と、高濃度ドレイン領域の一
部に導電型を反転させて形成した浅い低濃度ベース領域
を同時に形成することにより、製造工程を簡略化してコ
ストダウンおよび製造工期の短縮を実現させるという効
果を有する。As described above, according to the present invention, after a high-concentration drain region is formed, an impurity of a conductivity type opposite to that of the drain region is ion-implanted with high acceleration energy to form a high-concentration base region having a deep junction surface. By forming a shallow low-concentration base region formed by inverting the conductivity type in a part of the high-concentration drain region at the same time, there is an effect that the manufacturing process is simplified to reduce costs and shorten the manufacturing period.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の一実施例の製造方法を説明するための
工程順に示した断面図。FIG. 1 is a cross-sectional view showing a manufacturing method according to an embodiment of the present invention in the order of steps for explaining the manufacturing method.
【図２】従来の縦型ＦＥＴの第１の例を説明するための
断面図。FIG. 2 is a cross-sectional view illustrating a first example of a conventional vertical FET.
【図３】従来の縦型ＦＥＴの第２の例の製造方法を説明
するための工程順に示した断面図。FIG. 3 is a cross-sectional view illustrating a method of manufacturing a second example of a conventional vertical FET in the order of steps for explaining the method.
【図４】従来の縦型ＦＥＴの第２の例の製造方法を説明
するための工程順に示した断面図。FIG. 4 is a cross-sectional view illustrating a method of manufacturing a second example of a conventional vertical FET in the order of steps for explaining the method.
１ シリコン基板 ２ ドレイン領域 ３ ゲート絶縁膜 ４ ゲート電極 ５ 高濃度ドレイン領域 ６ 低濃度ベース領域 ７ 高濃度ベース領域 ８ ソース領域 ９ 層間絶縁膜 １０ ソース電極 １１ ドレイン電極 １２ ベース領域 Reference Signs List 1 silicon substrate 2 drain region 3 gate insulating film 4 gate electrode 5 high-concentration drain region 6 low-concentration base region 7 high-concentration base region 8 source region 9 interlayer insulating film 10 source electrode 11 drain electrode 12 base region
Claims (1)
型のドレイン領域の上にゲート絶縁膜を介して形成した
多結晶シリコン膜をパターニングし行列状に配置した開
孔部を有するゲート電極を形成する工程と、前記開孔部
周囲の前記ゲート電極の縁に沿って前記ドレイン領域の
表面に選択的に不純物をイオン注入して拡散し環状の一
導電型高濃度ドレイン領域を形成する工程と、前記ゲー
ト電極をマスクとして前記開孔部の前記高濃度ドレイン
領域を含む表面に不純物をイオン注入して逆導電型の深
い高濃度ベース領域および前記高濃度ベース領域内に逆
導電型の浅い環状の低濃度ベース領域を形成し且つ前記
高濃度ベース領域の外周に沿って接する前記高濃度ドレ
イン領域を形成する工程と、前記低濃度ベース領域内に
選択的に不純物をイオン注入して一導電型のソース領域
を形成する工程とを含むことを特徴とする縦型電界効果
トランジスタの製造方法。 1. A one conductivity type gate electrode having an opening disposed a polycrystalline silicon film formed through a gate insulating film on the patterned matrix on the drain region of the formed one conductivity type on a semiconductor substrate Forming a circular one-conductivity high-concentration drain region by selectively ion-implanting and diffusing impurities into the surface of the drain region along the edge of the gate electrode around the opening. Impurity is ion-implanted into a surface of the opening including the high-concentration drain region by using the gate electrode as a mask, and a deep high-concentration base region of a reverse conductivity type and a shallow reverse conductivity type are formed in the high-concentration base region. Forming an annular low-concentration base region and forming the high-concentration drain region in contact with the periphery of the high-concentration base region; and selectively implanting impurities into the low-concentration base region. Vertical field effect method for producing a transistor, which comprises a step of forming a source region of one conductivity type and down injection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6265570A JP2656740B2 (en) | 1994-10-28 | 1994-10-28 | Manufacturing method of vertical field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6265570A JP2656740B2 (en) | 1994-10-28 | 1994-10-28 | Manufacturing method of vertical field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08125172A JPH08125172A (en) | 1996-05-17 |
| JP2656740B2 true JP2656740B2 (en) | 1997-09-24 |
Family
ID=17418955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6265570A Expired - Lifetime JP2656740B2 (en) | 1994-10-28 | 1994-10-28 | Manufacturing method of vertical field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2656740B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6573144B2 (en) | 2000-04-07 | 2003-06-03 | Shigeki Takahashi | Method for manufacturing a semiconductor device having lateral MOSFET (LDMOS) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6479352B2 (en) * | 2000-06-02 | 2002-11-12 | General Semiconductor, Inc. | Method of fabricating high voltage power MOSFET having low on-resistance |
| US6627949B2 (en) * | 2000-06-02 | 2003-09-30 | General Semiconductor, Inc. | High voltage power MOSFET having low on-resistance |
| JP5246638B2 (en) | 2007-09-14 | 2013-07-24 | 三菱電機株式会社 | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6457675A (en) * | 1987-08-27 | 1989-03-03 | Nec Corp | Vertical field-effect transistor |
| JPH05283432A (en) * | 1992-03-31 | 1993-10-29 | Nec Kansai Ltd | Vertical type field-effect transistor and its manufacture |
-
1994
- 1994-10-28 JP JP6265570A patent/JP2656740B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6573144B2 (en) | 2000-04-07 | 2003-06-03 | Shigeki Takahashi | Method for manufacturing a semiconductor device having lateral MOSFET (LDMOS) |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08125172A (en) | 1996-05-17 |
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