JP2647180B2 - Method for providing and examining integrated circuit update status information - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a method for providing and examining update status information of an integrated circuit including a plurality of pattern layers. The patterned circuit layers, so-called pattern layers, are each made, for example, from separate masks made with specifications for each pattern layer. The ROM is used to read the updated state of the circuit for updating the circuit pattern.

(Prior Art) When updating a circuit, first, a circuit mask having a changed pattern is prepared. From the newly created revised mask and the remaining old mask of the original circuit, a new circuit of the same kind as before having a new update state is created. According to the prior art, a code representing the updated state of the circuit is then applied to the cover of the circuit and inspected before mounting on the circuit to ensure that the correct updated state has been applied.
This code inspection is performed visually.

Mask programmable ROMs are known with integrated circuits. The storage content of the ROM is determined by the structure of one of a plurality of pattern layers. The pattern is determined by one of a plurality of circuit masks, a programming mask. When this mask program type ROM is used to encode a circuit change, updating the pattern layer further in order to encode a new update state of the circuit means changing the mask pattern corresponding to the pattern layer. , And the pattern of the programming mask is changed (programmed). Thus, before creating a circuit containing the new update state, both the mask corresponding to the revised pattern layer and the programming mask are newly created.

SUMMARY OF THE INVENTION A problem with visually reading the updated state of a circuit is that reading errors can occur. When reading the updated state of a circuit, if the updated state is supplied to the circuit before an error is detected, it is very expensive. When such an inspection method is employed, there is a risk that an incorrect code is attached to the circuit cover.

The problem with using mask-programmable ROMs with current technology is that when updating one or more mask layers, it is necessary to create a new programming mask in addition to updating the mask of the updated pattern. . Because RO to direct the update
This is because the contents of M must be changed (reprogrammed). Making masks is quite expensive, so every renewal is expensive. This is because it is necessary to create a new memory mask every time programming is changed.

The present invention has been made to solve these problems. According to the invention, a separate memory is provided in each pattern layer that may require reconstruction. When the pattern layer is changed, the updated state of the pattern layer is written in this memory in, for example, a binary code format. These memories are included in the integrated circuit in the form of ROM, and each pattern layer in which the memory is included can be programmed to include a layer-specific update code. At the same time that the code relating to the update state is written to the memory, this code is written to the inspection device as reference information. When performing the inspection, the inspection program in the inspection apparatus reads the updated state of each pattern layer, compares these states with reference information, and the result of the comparison represents the updated state of the integrated circuit.

According to the method of the present invention, the updated state of the circuit can be electrically read without using another pattern layer in the circuit as the ROM. When the mask corresponding to the pattern layer is updated, to include information about this update,
The memories in the mask are programmed simultaneously. The fact that the update state programming is performed in the same mask where the update was performed is a significant economic advantage. This is because it is not necessary to add a new memory mask for each program change.

Example An integrated circuit is composed of a plurality of circuit layers. The patterned circuit layer, the so-called pattern layer, is made from a so-called mask using, for example, photolithography. Patterned layers can also be made from photographic lithography using photographic lithography. In this case, the pattern layer is directly exposed. A pattern of one pattern layer is formed from one mask. Typically, the mask pattern is drawn using a CAD system, and then a mask is created from the patterns stored in the CAD system.

Updating circuits is becoming more and more common, along with the need for users of the circuits to be able to check the updated state of the circuits they use. To update one predetermined circuit, the CAD system updates one or more masks and then creates an updated mask. Using these updated masks together with the remaining masks belonging to that circuit, a circuit of the same kind as the previous circuit is created in an updated state. Read-only memory (ROM) on the integrated circuit to electrically check the updated state of the circuit during the circuit inspection process
Is appended. The ROM is used to read information about the updated state of the circuit. In the ROM, each pattern layer has a memory (programmed) in which a code for checking the update status of each pattern layer is written, so that each pattern layer having a memory has an update status code. ing. This code is, for example, a binary code. The update state of each different pattern layer determines the update state of the integrated circuit. The memory comprises a mask programmable memory area in the pattern layer. ROM consists of these memory areas. The memory area is programmed into a mask corresponding to the pattern layer when arranging the circuit pattern of the pattern layer. The updated state of the layer can be seen in the memory area included in each reconfigurable pattern layer. However, a pattern layer that is automatically updated as a result of updating another layer does not include a memory area for encoding update information. Because the update of that layer is obvious. Therefore, in order to be able to confirm the update state of the circuit, it is necessary to see only a part of the memory area of the pattern layer in which the update coding is significant. The data of the ROM 1 shown in FIG. 1 includes 12 memory areas, each of which consists of 4 bits. Each 4-bit memory area is surrounded by a frame. The original circuit of ROM1 is 12
Pattern layers, each having a distinct memory area. This circuit is empty. Therefore,
This ROM is programmed with zeros in all memory areas. This indicates that none of the pattern layers has been updated. The memory area included in each of these pattern layers contains a code indicating the updated state of the pattern layer. That is, the pattern layer is updated as the sequence proceeds.

The above-described circuit inspection is performed by connecting the integrated circuit 3 to the inspection device 2 as shown in FIG. This figure shows the flow of information in the inspection device. The inspection program 5 included in the memory 4 in the inspection apparatus stores a routine for reading and inspecting the code of the update layer among the pattern layers.
The inspection program 5 also contains codes for the update status of each different pattern layer. These codes constitute reference information, and make it possible to confirm the updated state of the circuit by performing memory reading.

When it is desired to change the function of a circuit, a mask relating to the change is created to realize a desired circuit function. For example, suppose a case where a desired change in circuit availability results in updating three circuit pattern layers including a memory area. The mask patterns corresponding to these pattern layers are updated using the CAD system as described above. At the same time that the circuit patterns of the three masks are rewritten, the memory area of the mask is reprogrammed by changing the pattern of the memory area to check that the mask has been rewritten. Since this update is assumed to be the first rewrite performed on the circuit, the memory area is programmed with "1" in the least significant bit. This means that the new mask has been rewritten. Three update masks are new. Using the three updated masks and the remaining non-updated masks, a new circuit of the same type as before but including the first updated state is created. The first update state is named, for example, R1.

Prior to testing the updated circuit, reference information about the new updated state R1 is written to the test program 5. Each pattern change in the mask is performed by programming the ROM 1 and writing the changed update state to the inspection program.

As described above, the inspection device is used to inspect the updated state of the circuit. When performing this inspection, the integrated circuit 3 is connected to the inspection device 2 as shown in FIG. During this inspection, the inspection program 5 is controlled by the driver 6 in the inspection apparatus. The driver 6 is the RO of the integrated circuit 3.
The contents of M1 (see FIG. 1) are collected and supplied to the comparator 7 in the inspection apparatus. The contents of the ROM are collected as follows (see FIG. 1). The address of the word in the ROM is read from the inspection program 5 into the shift register 8 included in the integrated circuit. The address is supplied from the shift register to the address decoder 9 in the integrated circuit. The address decoder points to the addressed word in ROM1. In the example shown, one word is composed of one bit from each of the six memory areas. The word pointed out is RO
M1 supplies the data to the shift register 8, from which it is supplied to the comparator 7 (see FIG. 2) in the inspection apparatus 2 in the form of data. The inspection program 5 supplies the aforementioned reference information to the comparator 7, where the data read from the ROM 1 of the integrated circuit 3 is compared with the reference information, and the comparison result is sent to the inspection program. As a result of the circuit inspection, the inspection program indicates whether the update state of the integrated circuit is as expected. The inspection program may be configured so that the result of the circuit inspection directly indicates the updated state of the circuit.

Another memory programmed with codes relating to the type of circuit may be added to the ROM. This would allow the type of circuit to be read during circuit testing.

[Brief description of the drawings]

FIG. 1 is a block diagram of a read-only memory connected to a shift register. FIG. 2 is a schematic diagram showing a flow of information in an inspection device to which an integrated circuit is connected. DESCRIPTION OF SYMBOLS 1 ... Read-only memory 2 ... Inspection device 3 ... Integrated circuit 4 ... Memory 5 ... Inspection program 6 ... Driver 7 ... Comparator 8 ... Shift register 9 ... Address decoder

Claims (1)

(57) [Claims] A method for providing and examining updated state information of an integrated circuit including a plurality of pattern layers, comprising a separate memory for each pattern layer likely to be reconfigured,
The memory comprises a read-only memory, which operates to store the status code of that particular pattern layer, and indicates that none of these pattern layers has been updated in each of the plurality of pattern layers. When a reconfiguration is performed on a certain pattern layer, an update status code is written in a separate memory of the pattern layer, and each update status code in each memory of the integrated circuit indicates an update status of the integrated circuit. And displaying the updated status code in the read-only memory to the inspection device, wherein the updated status code is written to the inspection device as reference information. Comparing the information with reference information and using the comparison result to indicate an updated state of the integrated circuit (3); Provided to and examine how the updated state information of the integrated circuit to be.