JP2645864B2 - Integrated circuit test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron beam test apparatus for performing a failure diagnosis of an integrated circuit at high speed and in detail.

[Conventional technology]

One of the testing methods using an electron beam tester is a method called dynamic fault imaging (hereinafter referred to as DFI) (TCMay et al., “Dynamic Fault Imaging”).
Imaging of VLSI Random Logic Devices ", 1984IEEE / IR
PS, pp. 95-108).

FIG. 2 is a block diagram of a conventional apparatus according to this method. In the figure, 1 is an electron beam test device, 2 is a DU
T, 3 is a reference device, 4 is an XY stage, 5 is an image conversion circuit, 6 is a first memory circuit, 7 is a second memory circuit, 8 is a difference circuit, 9 is a third memory circuit, 10 is a display device, 11 Is a test pattern generation circuit. A test device (DUT: Device Under Test) 2 and a non-defective reference device 3 are placed in a sample chamber of the electron beam test apparatus 1, and the same test pattern is applied simultaneously. Both devices are XY
It is placed on the stage 4 and is configured to be able to alternately move below the scanning area of the electron beam in accordance with the movement of the XY stage while receiving an instruction from the test pattern generation circuit 11. The electron beam two-dimensionally scans a fixed area on the moving device placed directly under the electron beam, and converts it into an electric signal by a secondary electron image conversion circuit 5 generated from the surface at that time. The data is stored in the first memory circuit 6, and the image data of the reference device 3 is stored in the second memory circuit 7, respectively. One image represents an operation state at a certain timing of one cycle of the test pattern. At a certain timing of a desired cycle of the test pattern, a required number of images are fetched in ascending order of time and stored in the memory circuit. In the example shown in this figure, the observation image stored in the first memory circuit 6 of the DUT 2 and the observation image stored in the second memory circuit 7 of the reference device 3 correspond to the corresponding cycle of the test pattern in the difference circuit 8. The difference between the images is calculated every time, and the difference that does not match due to a failure, that is, a failure image (DFI image) is stored in the third memory circuit 9 in the order of observation. The difference images are similarly arranged in the order of observation, and displayed on the display device 10 as a three-dimensional test pattern image.

In general, when a certain portion of an integrated circuit has failed, the effect of the failure propagates in the direction of signal propagation and spreads to many circuit nodes over time as the step progresses. When this is viewed as a failure image, it becomes as shown in the display scan of FIG. 3, and the failure pattern can be seen to expand with time. When the failure pattern shows such a spread, the starting point is the failure occurrence point. As described above, the DFI method has a feature that a fault location can be intuitively recognized without design knowledge, and the fault location can be specified extremely easily and at high speed. Therefore, according to this method, engineers other than the designer of the integrated circuit can freely perform fault diagnosis, and applications from the development department to the production line are expected.

[Problems to be solved by the invention]

However, in this type of conventional apparatus, a reference image necessary for obtaining a failure image can only be obtained by using a good device of an actual integrated circuit. For this reason, the following points are problems, and have been a major obstacle to practical application.

1) Non-defective devices inevitably undergo characteristic changes over time, and sometimes malfunction. Therefore, the reliability of the reference image obtained based on good devices is low,
There is always a need to manage to ensure and confirm that devices are good and work properly.

2) This method cannot be used for testing at the stage where a good device cannot be obtained, such as during the development stage.

3) In recent years, since integrated circuits are diversified in a small number and varieties, it is difficult to obtain guaranteed good products. And it's 100
The number of test patterns for guaranteeing the% is enormous, and the test cost dramatically increases.

Such a problem can be solved by directly generating the reference image from the design data so that the test can be performed without a good device. That is, the design data does not change over time and always includes necessary reference data regardless of the size. Based on such an idea, a result of associating the logic simulation result, the wiring pattern data and the circuit with each other from the design data is read,
There has been proposed a method of generating a reference image called a design logic map in which a wiring pattern is color-coded by a logic value based on a simulation.

(Japanese Unexamined Patent Publication No. 61-199806, "Testing apparatus for integrated circuit and its use") However, this design logic map is completely different from the observed image signal. FIG. 3 is a diagram for explaining the difference between the design logic map and the observed image. Reference numeral 31 denotes a signal level low wiring pattern, and reference numeral 32 denotes a signal level high wiring pattern.
(A) shows an example of a design logic map. The signal level low wiring pattern 31 is colorless, the signal level high wiring pattern 32 is indicated by oblique lines, and the wiring pattern is a figure (hereinafter, referred to as a vector figure) expressed in the form of a polygon, rectangle, or a width line. Represents an image. (B) shows the analog signal value of the secondary electron signal when the device surface is scanned with the electron beam. When this image signal is taken into the memory circuit, as shown in (c), the signal value when the electron beam reaches a predetermined position is sampled, converted into a digital value, and rasterized as shown in (d). It is stored in the form of image data.

Conventionally, it was possible to convert image data based on vector graphics into raster image data, but there were the following problems when applied to the generation of difference images by the DFI method.

1) Since the luminance level of the image is obtained only from the presence or absence of the wiring at the pixel point at the predetermined position, the luminance level is at most three values. On the other hand, the observed image obtained by scanning with a finite diameter electron beam has essentially multi-valued brightness, and is rather close to a continuous amount.

2) In order to compare the absolute luminance value of an image with the luminance value of an observation image, there has been no so-called equalizing means for expressing the expression based on the same scale.

Therefore, in the difference image between the two images that have not been equalized, the noise component becomes larger, and there is a problem that a true mismatch pattern (failure pattern) cannot be identified, and it is difficult to generate a failure image. Atsuta.

In the above-mentioned publications, as a means for comparing the two, a wiring pattern of an observed image is converted into a vector graphic, and a means for comparing this with a design logic map is proposed.However, in order to apply a method according to the DFI method, It is necessary to widen the observation area because it is necessary to observe the behavior of the failure pattern in one view.
However, widening the observation area means taking in an image with a low resolution due to the limitation of the number of scanning lines, and it has been extremely difficult to convert the wiring pattern into a vector graphic.

In the conventional electron beam test apparatus, a failure image required for the DFI method can be generated for the first time as compared with a good sample, but the apparatus of the present invention solves this problem, and even if there is no good sample, Another object of the present invention is to provide means for always generating a failure image.

[Means for solving the problem]

Means for two-dimensionally scanning a predetermined region of an integrated circuit sample device placed in an operation state with an electron beam;
Means for converting the next electron into an electric signal at a sampling point in accordance with a test pattern and storing the image data of the sample device; and a means for storing the image data stored in the sample device and the reference data of the image prepared in advance in the integrated circuit. A means for extracting a design logic map from a design database, and a method for dividing an arbitrary region of the design logic map into pixels of an arbitrary size, and a design including each pixel. Means for calculating the graphic area in the logical map, and when calculating the graphic area included in each of some or all pixels by the calculating means, a histogram for the graphic area value and the absolute luminance of the observed image from the sample device And means for comparing and comparing the histograms for.

〔Example〕

FIG. 1 is a block diagram for explaining an embodiment of the apparatus of the present invention. In the figure, 12 is a design database, 13 is circuit information, 14 is wiring figure information, 15 is cross-reference, 16
Is simulation information, 17 is a design logic map generator,
18 is a fourth memory circuit, 19 is an image distortion correction circuit, 20 is a fifth memory circuit, 21 is a raster image conversion circuit, 22 is a sixth memory circuit, 23 is a luminance histogram generation circuit, 24 is a histogram equalization circuit, and others. Use the same symbol as above. A DUT 2 is placed in a sample chamber of the electron beam test apparatus 1, and a predetermined test pattern is supplied by a test pattern generation circuit 11. Secondary electrons generated when scanning a predetermined area on the DUT 2 in the operating state with an electron beam are converted into electric signals by the image conversion circuit 5, and the image data is stored in the first memory circuit 6. On the other hand, the circuit information 12, the wiring graphic information 13, and the cross-reference 15 from the design database 11, and the expected logical value of each circuit net from the simulation information 16 are taken out. 4
Stored in the memory circuit 18. This design logic map is input to the image distortion correction circuit 19 and corrected so that each part accurately corresponds to the image from the DUT 2. In this correction, a distortion parameter of the DUT image calculated in advance and stored in the fifth memory circuit 20 is used. The image obtained in this way is input to the raster image conversion circuit 21 and divided into arbitrary pixels.
The image data is converted into raster pixels, which are divided aggregates, and converted into image data. The conversion to the raster image is performed by calculating the overlapping area of the graphic reflecting the shape of the electron beam spot stored in the sixth memory circuit 22 and the wiring graphic of the design logic map at the position of each pixel. . The pixel distortion correction may be performed before or after raster image conversion. At this stage, the value of each pixel of the image converted into the raster image data is a mere overlapping area, and does not match the luminance value of the observation image from the DUT2.

Therefore, the observation image of the DUT in the first memory circuit 6 is input to the luminance histogram generation circuit 23 to generate a histogram for the absolute luminance. Next, the histogram and the raster image data (design raster image) generated from the design logic map are input to a histogram equalization circuit 24, and the histograms of both images are compared and collated, so that the histogram of the design raster image matches the histogram curve. A conversion coefficient for converting the histogram curve is obtained, and the relative luminance of the reference design raster image obtained from the design logic map is adjusted by the conversion coefficient to obtain the absolute value luminance design raster image of the second memory circuit 7. Is input to The difference circuit 8 calculates a difference between the DUT image of the first memory circuit 6 and the design raster image obtained from the design logic map of the second memory circuit 7. The difference images (DFI images) are arranged in test cycle order, input to the third memory circuit 9 as DFI images, and displayed through the display circuit 10.

4A and 4B are diagrams illustrating a specific example of raster image conversion of a design logic map. FIG. 4A illustrates a case where scanning is performed with a fine electron beam, and FIG. 4B illustrates a case where scanning is performed with a thick electron beam. In the figure, 41 is an electron beam spot, 42 is a logic 1 wiring area, 43 is a logic 0 wiring area, 44 is another area excluding the areas 42 and 43, 45 is a lattice point, and 45 is a grid point. The square approximates the shape of the spot irradiated by the electron beam.

(A) is a case where a relatively small area 41 is scanned with an electron beam narrowly focused on the design logic map, and the brightness of the electron beam spot 41 corresponding to each pixel is at most one line and the overlap of the beam spot shape figure. Determined by area. Wiring area 42
The diagonal line indicates the wiring logic 1 and the brightness is bright, the dot pattern of the wiring area 43 is the wiring logic 0 and the brightness is dark, and the area 44 is the brightness of the ground other than the wiring area. The brightness is intermediate. The brightness of each pixel changes depending on which part of the wiring pattern on the logic map irradiates the electron beam, and in the observation image of the electron beam tester, the larger the irradiation area applied to the wiring area 42, the higher the brightness. The luminance decreases as the irradiation area on the region 43 increases. That is, in FIG. 4A, the brightness of each pixel is in the order of E>F>G>A>D>C> B. In consideration of such a relationship, an overlapping area between figures can be calculated, and a relative value of luminance at each pixel can be determined based on the calculated value.

On the other hand, (b) shows a case where the design logic map is scanned with a thick electron beam. In this case, the distance between pixels becomes large, and a large area is obtained with a limited number of pixels.
This is the scanning method closest to observing the actual DFI. In this case, the pixel by the electron beam spot 41 has a high possibility of extending over a plurality of wirings, and the luminance of each pixel is an integrated value obtained by integrating them. By examining how long the wiring pattern overlaps the electron beam spot 41, the brightness of each pixel can be obtained. Specifically, each wiring is divided into wiring elements of minute length, integrated at the grid point 45 at the center of the pixel closest to the wiring element, and added, and the sum is used as the relative value of the luminance of each pixel. Pixel in the figure
An oblique arrow from a minute point of the wiring in 41 toward the grid point 45 indicates this pattern.

FIG. 5 is a diagram for explaining an embodiment of a histogram equalization method, in which the relative luminance determined in FIG. 4 is converted into an absolute luminance value. (A) shows a luminance histogram when a small area is scanned with a fine beam, and when the resolution of an image is sufficiently high, the luminance of each peak of the histogram is a logical 1 wiring, a part other than the wiring, a logical 0
, Respectively. (B) shows the histogram of the design raster image obtained from the design logic map, and the brightness of the pixel at the position of A, B, and C in FIG. 4 is expressed by the brightness of each peak (each value of 40, 130, 200 in this figure). ), The intermediate values such as C, D, E, and F are proportionally calculated based on the overlapping area to realize the equalization of the histogram, and the absolute value of the luminance can be obtained. (C) shows a histogram when scanning with a large beam. In this case, since the luminance is the integral of a plurality of wiring patterns, the peak does not appear clearly, and the correspondence with the logical 0 / logical 1 wiring luminance becomes unclear. Therefore, the brightness of each peak (40, 130, 200) in the case of (a) in which the electron beam is narrowed down is used, and the absolute value of the brightness is I = 40 · S _1i + 200 · ΣS _0j + 130 · S ₂ · Electron beam area = ΣS _{1j + ΣS 0j + S 2 ·} S 1j: area · S _0j wiring element of a logic 1: the logical 0 of the wiring elements in the area · S _2: given by equation area of a region other than the wiring, thereby equalizing the histogram equalization .

(D) shows a histogram when the observed image changes with time. The luminance of the peak A and its half width are (c)
By obtaining each of them in (d) and obtaining a conversion formula between the histograms between them, the two histograms can be equalized. That is, the conversion formula of the luminance is as follows: X = px + q X: Luminance at x: (d) Luminance at x: (c) In (c), the half width is 20, and the peak value is 130. In (d), the half width is 30, and the peak is 30. Since the value is 150, 135 = p · 120 + q 165 = P · 140 + q. By solving this, the parameters p and q are obtained.
By using this conversion formula, it is possible to always make the luminance value of the observed image coincide with the luminance value of the reference image obtained from the design logic map.

As is apparent from the above results, according to the present invention, it is possible to always generate a reference image having a multi-valued luminance level and having the same luminance as that of the observed image from the design logic map. Compared to the conventional technology, there is an improvement in that a test based on the DFI method can be performed without using a good device.

〔The invention's effect〕

As described above, the apparatus according to the present invention has the following advantages because the reference image is generated from the design data.

1) When there is necessary design data, a reference image can always be generated, so that it can be applied to tests at all stages irrespective of the presence or absence of non-defective products, greatly expanding the applicable range.

2) The design data itself is always a good product, and there is no need to verify the good product.

3) Since the design data does not change in quality, there is no need to manage non-defective samples, and the reliability of the reference image is extremely high.

[Brief description of the drawings]

FIG. 1 is a block diagram of the apparatus of the present invention, FIG. 2 is a block diagram of a conventional apparatus, FIG. 3 is a view for explaining the difference between a design logic map and an observed image, and FIG. 4 is a raster image conversion of the design logic map. FIG. 5 is a diagram for explaining an embodiment of a histogram equalization method. 1 is an electron beam test apparatus, 2 is a DUT, 3 is a reference device, 4 is an XY stage, 5 is an image conversion circuit, 6 is a first memory circuit, 7 is a second memory circuit, 8 is a difference circuit, and 9 is a third circuit.
Memory circuit, 10 is a display device, 11 is a test pattern generation circuit, 12 is a design database, 13 is circuit information, 14 is wiring diagram information, 15 is cross-reference, 16 is simulation information, 17 is a design logic map generation circuit, 18 is a fourth memory circuit, 19 is an image distortion correction circuit, 20 is a fifth memory circuit, 21 is a raster image conversion circuit, 22 is a sixth memory circuit, 23 is a luminance histogram generation circuit, 24 is a histogram equalization circuit, 31 Is a signal level low wiring pattern, 32 is a signal level high wiring pattern, 41 is an electron beam spot, 42 is a logic 1 wiring area, 43 is a logic 0 wiring area, 44 is a ground area, and 45 is a grid point.

Claims (1)

(57) [Claims] 1. A means for two-dimensionally scanning a predetermined region of an integrated circuit sample device placed in an operating state with an electron beam, and testing secondary electrons generated from the surface of the sample by the electron beam scanning. Means for converting the image data of the sample device by converting it into an electrical signal at a sample point in accordance with the pattern, and a difference image between the image data stored by the sample device and reference data of a previously prepared image of the integrated circuit. Means for extracting a design logic map from a design database; dividing an arbitrary region of the design logic map into pixels of an arbitrary size; Means for calculating the area, when the figure area included in each of some or all pixels is obtained by the calculating means, the figure area A histogram of the means for comparing and collating a histogram of the absolute brightness of the observed image of the sample device, the integrated circuit test apparatus characterized by having a city.