JP2641329B2 - Delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit for delaying an electric signal, and more particularly to a delay circuit capable of delaying a high-speed digital signal in arbitrary bits.

[0002]

2. Description of the Related Art Conventionally, various circuits have been used as circuits for delaying signals. An example is shown in FIG. In the figure, reference numeral 401 denotes a central processing unit (CPU);
Is a read-only memory (RO) storing a program
M) and 403 are random access memories (RAM) for storing data, 404 is a decoder, and 405 is an input / output (I / O) port.

The CPU 401 operates according to a program stored in the ROM 402, and the processing procedure will be described below. The CPU 401 inputs a signal for selecting the I / O port 405 to the decoder 404 according to the program. In response, the decoder 404
Selects the I / O port 405 and makes it active. I /
The O port 405 reads the input data Di, and
Input to M403. In order to hold the data Di for a preset time T, the data Di is stored in the RA designated by the write internal address counter (not shown) of the CPU 401.
It is stored at the address of M403. At the same time CPU
401 adds 1 to the value of the write internal address counter. Next, the CPU 401 reads the data stored in the RAM 403 before the time t from the address specified by the read internal counter (not shown) of the CPU 401,
Again, the I / O port 4 selected by the decoder 404
05 is output and the value of the read internal counter is set to 1
Add. The corresponding data D from the I / O port 405
o is output. The write internal address counter,
The above processing is repeated until the internal counters for reading each reach a predetermined value. After the internal counters that have reached the predetermined values are returned to the initial values, the above processing is repeated again. Thus, the signal input to the delay circuit can be delayed by the time T.

The delay time T is a value obtained by multiplying the difference between the value of the internal counter for writing and the value of the internal counter for reading in the CPU 401 by the time required for each processing.

[0005]

In this conventional delay circuit, since a CPU is used, a program is required, the address space is limited and the range in which the delay time can be changed is narrow, or the processing time of the CPU is reduced. Therefore, there was a problem that high-speed data could not be handled. further,
When a dynamic RAM (DRAM) is used as the RAM 403, there is a problem that an interface becomes complicated, and data of a fixed length such as a byte or a word is easy to handle, but data of another unit (for example, 1 bit) is handled. There was a problem that it was difficult.

The present invention has been made in view of such problems, and does not require two types of address signals for reading and writing, and can delay complicated bit patterns such as voice and alarm sounds. It is an object of the present invention to provide a delay circuit capable of performing a delay process on a high-speed signal on a bit-by-bit basis and setting a wide range of delay time.

[0007]

In order to achieve this object, a delay circuit according to the present invention comprises a delay time setting means for setting a delay time and outputting a first signal corresponding to the set delay time; A second signal corresponding to the counted value.
Counting means for outputting a signal, comparing means for comparing the first signal and the second signal and resetting the counting means when the two signals have a predetermined relationship, and reading the address corresponding to the second signal to the same address And a DRAM storage means for performing an operation of writing new data to obtain a delay time in an arbitrary bit unit.

[0008]

The counting means counts the clock signal, reads the address of the storage means corresponding to the count value, and writes new data to the same address. When the count value has a predetermined relationship with the set value set by the setting means, the count value, that is, the address value of the storage means is reset. By repeating this, a delay corresponding to the time set by the setting means is made.

[0009]

FIG. 1 is a block diagram showing an embodiment of a delay circuit according to the present invention. In the figure, reference numerals 101 and 102 denote 10-bit dip switches, which are used to designate a column address and a row address of a DRAM 109 described later, respectively. The value obtained by multiplying the designated column address and row address values by the processing cycle corresponds to the delay time, and the DIP switches 101 and 102 constitute a delay time setting means. The first from DIP switches 101 and 102
The signals as the signals are comparators 103, 10
4 is input to one input terminal A. Comparator 10
3 is grounded, and the output terminal bar (A =
The output signal from B) is input to the gate terminal bar G of the comparator 104. The comparator 103 is always in an active state because its gate terminal G is grounded. The comparators 103 and 104 constitute comparison means. The output terminal bar of the comparator 104 (A =
Output signals from B) are binary counters 105 and 106.
Is input to the clear terminal CLR. Counter 105, 1
06 is output as a second signal to the comparator 10
3, 104 and the other input terminal B and the multiplexer 10
8 input terminals A and B. The carry signal of the counter 106 is input from the carry output terminal CO to the carry input terminal Ci of the counter 105. Counter 105, 10
Reference numeral 6 denotes a 20-bit ripple carry counter as counting means. From the output terminal Y of the multiplexer 108, an address signal f is input to the address terminals A0 to A9 of the DRAM 109. From the timing signal generation circuit 107, the timing signal a is input to each clock terminal CLK of the counters 105 and 106, the timing signal b is input to the timing control terminals A / B of the multiplexer 108, and the RAS terminal and the CAS WR terminal, the timing signal c,
d and e are input. The input data signal g is input to the data input terminal Din of the DRAM 109, and the output data signal h is output from the data output terminal Dout. Timing signal generating circuit 107, multiplexer 108, DRA
M109 constitutes DRAM storage means.

FIG. 2 is a timing chart of the delay circuit shown in FIG. 1. The operation of the delay circuit will be described below with reference to FIGS. The DRAM 109 is used in a drive-type read-modify-write cycle in which new data is written to the same address after reading. Now, DIP switch 101
Is set to the numerical value K, and the dip switch 102 is set to the numerical value L. The counter 106 counts the clock signal a, and outputs a carry signal from the terminal CO every time the number of clocks corresponding to one row of memory cells is counted. The counter 105 counts the carry signal,
A signal corresponding to the count value is output. The output signal of the counter 105 is a signal indicating the column address of the DRAM 109 and is input to the input terminal B of the comparator 103 and the input terminal A of the multiplexer 108. Also, counter 1
The output signal 06 is a signal representing the row address of the DRAM 109, and is input to the input terminal B of the comparator 104 and the input terminal B of the multiplexer 108. Multiplexer 108 responds to timing signal b to count
05 and 106 are input to address terminals A0 to A9 of the DRAM 109 as an address signal f in a time-division manner. At the same time, control signals c and d are input from the timing signal generation circuit 107 to the DRAM 109. In response, DRAM 109 outputs data at an address corresponding to address signal f as signal h. After the output data is determined, the input data is determined as shown by the signal g. Therefore, the writing is controlled by the signal e from the timing signal generation circuit 107, and new data is stored at the same address. When the count value of the counter 105 becomes K, the comparator 104 outputs a low-level signal from the terminal bar (A = B). Comparator 104 is activated in response to this. Thereafter, when the count value of the counter 106 becomes L, the comparator 104 outputs a low-level signal from the terminal bar (A = B). The counters 105 and 106 are
It is reset in response to this signal. By repeating the above procedure, the processing time T is delayed until the data is read after it is written. That is, the data read from the DRAM 109 in the read operation is data stored before the time T, and therefore, the signal a is set to the address value set by the switches 101 and 102.
Can be set arbitrarily.

In this embodiment, the dip switch 101,
The set value of 102 is equal to the count value of counters 105 and 106
Reset the counters 105 and 106 when they become bad
However, when the difference between these values becomes constant,
It may be reset when a certain relationship is established
No. Furthermore, a DRAM capable of high-speed processing is used as a storage means.
Used but static RA depending on required speed
Other storage devices such as M can be used.

In this embodiment, since a CPU is not used, delay processing for a high-speed signal can be performed on a bit-by-bit basis.
A wide range of delay time of about 200 ms can be set. Also, the upper (row) of the address signal of the DRAM 109
Since the refresh cycle is omitted by exchanging the lower (column) and the higher (row) address signal first, the circuit related to the refresh of the DRAM can be prevented from being complicated.

FIG. 3 shows a block diagram of an evacuation guidance device using the delay circuit of the present invention. In FIG. 3, a plurality of delay circuits 302-1 to 302-n are connected to a sound source 301 such as a signal generator or a microphone that generates a burst signal. The speaker driving circuits 303-1 to 303-n are connected to the delay circuits 302-1 to 302-n. Further, each of the speaker driving circuits 303-1 to 303-
Speakers 304-1 to 304-n are connected to n. The delay circuits 302-1 to 302-n are the delay circuits of the present invention described above, and the delay time is determined by the delay circuits 302-1 and 303-1.
Are set to be longer in the order of 02-2,. Each of the speakers 304-1 to 304-n is a speaker 3
Are provided at predetermined intervals in an evacuation passage such as a hospital corridor in the order of 04-1, 304-2,....

An example of use of the evacuation guidance device configured as described above will be described. In the event of a fire in a hospital or the like, when the guide generates a “peep” sound of a predetermined time width from the sound source 301 disposed in the broadcasting room, first, the delay circuit 302-1 having the shortest delay time, the speaker A warning sound of a predetermined time width of "P" is emitted from the speaker 304-1 via the drive circuit 303-1. After the alarm sound disappears, 2
Thirdly, the speaker 304 emits an alarm sound having a predetermined time width of "P" via the delay circuit 302-2 and the speaker drive circuit 303-2 having the shortest delay time. This operation is sequentially performed until an alarm sound is emitted from the speaker 304-n. The speakers 304-1 to 304-n are speakers 304-1, 304-2,.
Since the evacuees are arranged at predetermined intervals along the evacuation passage in the order of 04-n, the evacuees can evacuate to a safe place if they proceed in the direction in which the warning broadcast can be heard.

The delay circuit of the present invention has the advantage that the delay time can be set in a wide range, and is very useful when applied to the evacuation guidance device.

[0016]

According to the delay circuit of the present invention, it is possible to delay complicated bit patterns such as voice and alarm sound without requiring two types of address signals for reading and writing, and to perform delay processing for high-speed signals. Can be performed in bit units, and a wide range of delay time can be set.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a delay circuit according to the present invention.

FIG. 2 is a block diagram for explaining the operation of the delay circuit shown in FIG. 1;

FIG. 3 is a block diagram of an evacuation guidance device using the delay circuit of the present invention.

FIG. 4 is a block diagram showing a conventional delay circuit.

[Explanation of symbols]

101, 102: Dip switch (delay time setting means) 103, 104: Comparator (comparing means) 105, 106: Binary counter (counting means) 107: Timing signal generating circuit ( DRAM storage means) 108 multiplexer (DRAM storage means) 109 DRAM (DRAM storage means)

Claims (1)

(57) [Claims] A delay time setting means for setting a delay time (T) and outputting a first signal corresponding to the set delay time.
01, 102) and counting means (105, 10) for counting clock signals and outputting a second signal corresponding to the counted value.
6) and comparing means (103, 104) for comparing the first signal and the second signal and resetting the counting means when the two signals have a predetermined relationship, and an address corresponding to the second signal.
Read new address and write new data to the same address
DR to obtain the delay time in arbitrary bit units
A delay circuit comprising AM storage means (107, 108, 109).