WO2023231263A1

WO2023231263A1 - Refresh address generation circuit

Info

Publication number: WO2023231263A1
Application number: PCT/CN2022/123849
Authority: WO
Inventors: 谷银川
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-05-30
Filing date: 2022-10-08
Publication date: 2023-12-07
Also published as: CN117198358A

Abstract

Disclosed in the embodiments of the present disclosure is a refresh address generation circuit, comprising: a refresh control circuit, a repetitive command processing circuit and an address generator. The refresh control circuit is used for sequentially receiving a plurality of first refresh instructions and performing a plurality of first refresh operations corresponding thereto, and outputting a first clock signal when the number of first refresh operations is less than k. The repetitive command processing circuit is coupled to the refresh control circuit and is used for receiving the first refresh instructions, and outputting an extra refresh flag signal when repetitive instructions appear in the first refresh instructions. The address generator is coupled to the refresh control circuit and the repetitive command processing circuit, pre-stores a first address, and is used for outputting, when the first clock signal is received and the extra refresh flag signal is not received and in response to the first clock signal, an address to be refreshed, or outputting an extra address in response to the extra refresh flag signal when the extra refresh flag signal is received.

Description

A refresh address generation circuit

Cross-references to related applications

This disclosure is based on a Chinese patent application with application number 202210604076. The entire contents of this application are hereby incorporated by reference into this disclosure.

Technical field

The present disclosure relates to, but is not limited to, a refresh address generation circuit.

Background technique

In the memory, the memory is divided into multiple memory banks (Banks), and there are two modes for refreshing storage addresses: All Bank Refresh (All Bank Refresh) in which all Banks refresh the same address together, and all Bank Refresh (All Bank Refresh) in which all Banks are refreshed at the same address. Different Banks of the Bank Group refresh the same memory bank with the same address one after another (Same Bank Refresh).

During the refresh process of the storage address, if the refresh command is mistakenly sent or missed, it will cause repeated refresh and bring waste.

Contents of the invention

In view of this, embodiments of the present disclosure provide a refresh address generation circuit that can use redundant repeated instructions to refresh additional addresses that require refresh, thereby avoiding the waste of instructions and improving refresh efficiency.

The technical solution of the embodiment of the present disclosure is implemented as follows:

An embodiment of the present disclosure provides a refresh address generation circuit. The refresh address generation circuit includes:

Refresh control circuit, configured to receive multiple first refresh instructions in sequence and perform multiple first refresh operations correspondingly, and output a first clock signal when the number of first refresh operations is less than m, where m is an integer greater than or equal to 1 ;

a repeated command processing circuit, coupled to the refresh control circuit, for receiving the first refresh command, and outputting an additional refresh flag signal when a repeated command occurs in the first refresh command;

An address generator, coupled to the refresh control circuit and the repeated command processing circuit, and pre-stored a first address for responding when the first clock signal is received and the additional refresh flag signal is not received. Output an address to be refreshed in response to the first clock signal, or when receiving the additional refresh flag signal, output an additional address in response to the additional refresh flag signal; wherein the address to be refreshed includes the first address Or a second address, the second address is adjacent to the first address; the difference between the additional address and the first address is greater than a preset threshold.

It can be seen that the embodiment of the present disclosure provides a refresh address generation circuit, including: a refresh control circuit, a repeated command processing circuit and an address generator. The refresh control circuit is configured to receive multiple first refresh instructions in sequence and perform multiple first refresh operations accordingly. When the number of first refresh operations is less than m, it outputs a first clock signal, where m is an integer greater than or equal to 1. The repeated command processing circuit is coupled to the refresh control circuit and is used for receiving the first refresh command and outputting an additional refresh flag signal when a repeated command occurs in the first refresh command. The address generator is coupled to the refresh control circuit and the repeated command processing circuit, and pre-stores the first address, for outputting the address to be refreshed in response to the first clock signal when the first clock signal is received and no additional refresh flag signal is received. , or when receiving the additional refresh flag signal, output an additional address in response to the additional refresh flag signal, wherein the address to be refreshed includes the first address or the second address, the second address is adjacent to the first address, the additional address and the second address The difference of an address is greater than the preset threshold. In this way, the extra repeated instructions in the first refresh instruction are used to refresh the additional addresses that need to be refreshed, thereby achieving effective use of repeated instructions, avoiding instruction waste, and improving refresh efficiency.

Description of the drawings

Figure 1 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 2 is a signal schematic diagram 1 of the refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 3 is a second structural schematic diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 4 is a second signal schematic diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 5 is a signal diagram 3 of the refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 6 is a schematic structural diagram three of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 7 is a signal diagram 4 of the refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 8 is a schematic structural diagram 4 of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 9 is a schematic structural diagram 5 of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 10 is a schematic structural diagram 6 of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 11 is a signal diagram 5 of the refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 12 is a schematic structural diagram 7 of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 13 is a schematic structural diagram 8 of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 14 is a signal diagram 6 of the refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 15 is a schematic structural diagram 9 of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 16 is a signal diagram 7 of the refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 17 is a signal schematic diagram 8 of the refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 18 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 19 is a schematic structural diagram 11 of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 20 is a signal diagram 9 of the refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 21 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 22 is a signal diagram 10 of the refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 23 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 24 is a signal schematic diagram 11 of the refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 25 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 26 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 27 is a signal schematic diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 28 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 29 is a signal diagram 13 of the refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 30 is a fourteenth signal schematic diagram of the refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 31 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 32 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 33 is a signal schematic diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 34 is a signal diagram 16 of the refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 35 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 36 is a signal schematic diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

Figure 37 is a signal schematic diagram of a refresh address generation circuit provided by an embodiment of the present disclosure;

FIG. 38 is a 19th signal schematic diagram of a refresh address generation circuit provided by an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated below in conjunction with the accompanying drawings and examples. The described embodiments should not be regarded as limiting the present disclosure. Those of ordinary skill in the art will All other embodiments obtained without creative efforts belong to the scope of protection of this disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or a different subset of all possible embodiments, and Can be combined with each other without conflict.

If similar descriptions of "first/second" appear in the application documents, add the following explanation. In the following description, the terms "first/second/third" involved are only used to distinguish similar objects and do not mean Regarding the specific ordering of objects, it is understood that "first/second/third" may interchange the specific order or sequence where permitted, so that the embodiments of the disclosure described herein can be used in other ways than those shown in the figures here. may be performed in any order other than that shown or described.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the disclosure only and is not intended to limit the disclosure.

Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is commonly used in the memory of electronic devices. In DDR4 SDRAM or previous DDR SDRAM, the refresh operation is performed on all banks together, and the addresses refreshed by all banks at the same time are the same, that is, All Bank Refresh. Same Bank Refresh is newly added to DDR5 SDRAM. In other words, in Same Bank Refresh mode, different Banks in the same Bank Group cannot be refreshed at the same time. However, if the refresh command is mistakenly sent or missed, repeated refreshes will be caused, resulting in waste.

Figure 1 is a schematic structural diagram of a refresh address generation circuit provided by an embodiment of the present disclosure. As shown in Figure 1, an embodiment of the present disclosure provides a refresh address generation circuit 10, which includes: a refresh control circuit 101 and a repeated command processing circuit. 102 and address generator 103. in:

The refresh control circuit 101 is used to receive multiple first refresh commands SB CMD<0:m-1> in sequence and perform multiple first refresh operations correspondingly. When the number of first refresh operations is less than m, output the first clock signal, m is an integer greater than or equal to 1;

The repeated command processing circuit 102 is coupled to the refresh control circuit 101 and is used to receive the first refresh command SB CMD and output the extra refresh flag signal Extra Refresh Flag when a repeated command occurs in the first refresh command SB CMD;

The address generator 103 is coupled to the refresh control circuit 101 and the repeated command processing circuit 102, and pre-stores the first address for responding to the first clock signal when the first clock signal is received and the extra refresh flag signal Extra Refresh Flag is not received. A clock signal outputs the address to be refreshed, or, when receiving the extra refresh flag signal Extra Refresh Flag, outputs an extra address in response to the extra refresh flag signal Extra Refresh Flag; wherein the address to be refreshed Address includes the first address or the second address , the second address is adjacent to the first address; the difference between the additional address and the first address is greater than the preset threshold.

It should be noted that in the embodiment of the present disclosure, the coupling method includes: direct electrical connection, and electrical connection through other electrical components (such as resistors, delays or inverters, etc.). The "coupling" that appears in the following paragraphs all include these methods, and will not be described again in the following paragraphs.

It should be noted that the number of address bits of the first address can be set according to actual needs, and this disclosure does not limit this. For example, the first address is a 16-bit address, recorded as Address<15:0>, and other addresses obtained based on the first address are also 16-bit addresses.

In the embodiment of the present disclosure, the refresh control circuit 101 can receive multiple first refresh commands SB CMD<0:m-1> in sequence, where SB CMD<0:m-1> represents m first refresh commands SB CMD< 0>～SB CMD<m-1>. Among them, each first refresh command SB CMD corresponds to a Bank in each Bank Group, and each first refresh command SB CMD will trigger the corresponding Bank in each Bank Group to perform a first refresh operation (i.e. Same Bank Refresh) . Correspondingly, multiple first refresh instructions SB CMD<0:m-1> received in sequence will trigger the corresponding Bank in each Bank Group to perform a first refresh operation respectively, that is, perform multiple first refresh operations in sequence.

In this disclosed embodiment, the Bank Group includes m Banks, and the number m of Banks is set according to chip design standards. Each Bank includes multiple rows of storage units, and the address to be refreshed is the row address of the storage unit in the Bank. During the first refresh operation of the refresh control circuit 101, the address generator 103 outputs the address to be refreshed Address during the first refresh operation, and the storage unit where the address to be refreshed in the Bank corresponding to the first refresh command SB CMD is located. refresh.

In the disclosed embodiment, the refresh control circuit 101 can output the SameBank refresh clock signal SB CBR CLK, and the SameBank refresh clock signal SB CBR CLK includes the first clock signal. If the number of first refresh operations is less than m, it means that there are still banks in the Bank Group that have not yet performed the first refresh operation on the memory unit where the address to be refreshed is Adress. At this time, the refresh control circuit 101 outputs the first clock signal.

Figure 2 shows the waveform of part of the signal when m=4. Combining Figure 1 and Figure 2, SB CMD<0>, SB CMD<1>, SBCMD<2> and SB CMD<3> are all the first refresh instructions received by the refresh control circuit in sequence, which respectively correspond to the same Bank Group. 4 Banks in , namely Bank0, Bank1, Bank2 and Bank3. Correspondingly, the pulses in SB CMD<0>, SB CMD<1>, SB CMD<2> and SB CMD<3> can sequentially trigger the refresh control circuit 101 to perform the first refresh operation. The SameBank refresh clock signal SB CBR CLK includes the first clock signal, and the first clock signal remains low.

In the embodiment of the present disclosure, repeated instructions refer to additional refresh instructions issued to a certain bank. As shown in Figure 2, the first refresh command SB CMD<0> includes two pulses. The previous pulse has triggered the first refresh operation of Bank0, and the latter pulse is a repeated command. In response to the repeated command, the extra refresh flag signal Extra Refresh Flag jumps to a high level, and the repeated command processing circuit 102 outputs the extra refresh flag signal Extra Refresh Flag that jumps to a high level to the address generator 103 .

In this disclosed embodiment, with reference to Figures 1 and 2, the address generator 103 pre-stores the first address. After receiving the first clock signal and not receiving the extra refresh flag signal Extra Refresh Flag that jumps to a high level, During each first refresh operation, the address to be refreshed will be output in response to the first clock signal, where the address to be refreshed includes the first address or the second address, and the second address is adjacent to the first address, that is, the first address. The difference between the second address and the first address is 1. As shown in the example of Figure 2, the first address is n, and the address to be refreshed includes the first address n or the second address n+1.

Continuing to combine Figures 1 and 2, when the address generator 103 receives the extra refresh flag signal Extra Refresh Flag that jumps to a high level, it will respond to the extra refresh flag signal Extra Refresh Flag and output the extra address k or k+1 as the pending Refresh the address Address, where the difference between the additional address (k or k+1) and the first address n is greater than the preset threshold. Since the address refresh sequence is based on the size of the address value, an appropriate preset threshold can be set so that the refresh sequence of the additional address k or k+1 is far enough away from the first address n, so that the additional address k or k+ The refresh of 1 will not affect the ongoing first refresh operation.

It can be understood that the refresh address generation circuit 10 provided by the embodiment of the present disclosure uses the redundant repeated instructions in the first refresh instruction to refresh additional addresses that need to be refreshed, thereby achieving effective use of repeated instructions and avoiding This eliminates the waste of instructions and improves refresh efficiency.

In some embodiments of the present disclosure, referring to FIGS. 1 and 2 , the refresh control circuit 101 is further configured to output a second clock signal when the number of first refresh operations is equal to m. Correspondingly, the address generator 103 is also configured to receive a second clock signal and change the first address to a third address in response to the second clock signal.

In the disclosed embodiment, the refresh control circuit 101 can output the SameBank refresh clock signal SB CBR CLK. The SameBank refresh clock signal SB CBR CLK includes a first clock signal and a second clock signal. If the number of first refresh operations is equal to m, it means that the memory cells where the Address to be refreshed in all Banks in the Bank Group have completed the first refresh operation. At this time, the refresh control circuit 101 outputs the second clock signal.

Combining Figures 1 and 2, the address output signal Addr Counter Output represents the first address stored by the address generator 103. When the number of times the refresh control circuit 101 performs the first refresh operation is less than m, the first address n stored in the address generator 103 remains unchanged, and the address output signal Addr Counter Output continues to be the first address n; when After the memory cells corresponding to two adjacent addresses in all banks are refreshed, that is, when the number of times the refresh control circuit 101 performs the first refresh operation is equal to m, the address generator 103 changes the first address n in response to the second clock signal. The address generator 103 can change the first address in an accumulative manner, and the accumulated value can be controlled by the pulses in the second clock signal. As shown in Figure 2, the second clock signal includes two pulses. Under the triggering of the pulse, the address generator 103 accumulates 1 twice for the first address n, and the address output signal Addr Counter Output becomes n+2, thereby matching the progress of refreshing the address. In the subsequent m first refresh operations, the address generator 103 continues to output the address to be refreshed, Adress, based on the first address that becomes n+2, to correspond to the next two adjacent addresses of each bank in the Bank Group. The storage units of the Bank Group are refreshed, and by analogy, the storage units corresponding to all addresses of each Bank in the Bank Group can be refreshed in sequence.

It can be understood that during a first refresh operation, the address generator 103 responds to the first clock signal and outputs the address to be refreshed Adress including the first address or the second address, while maintaining the first address. change; and after the number of first refresh operations reaches the preset number value k, the address generator 103 responds to the second clock signal and changes the first address. This not only ensures that the refresh operations are performed without missing a beat, but also maintains the consistency of the address. Integrity.

FIG. 3 is an optional structural schematic diagram of the refresh control circuit 101 shown in FIG. 1 , and FIGS. 4 and 5 are signal diagrams corresponding to FIG. 3 .

It should be noted that FIG. 4 shows the signal timing when the refresh control circuit 101 sequentially receives multiple first refresh commands SB CMD and performs the first refresh operation, wherein the preset number value of the first refresh command SB CMD is For example, m equals 4. FIG. 5 shows the signal timing when the refresh control circuit 101 receives the second refresh command AB CMD and performs the second refresh operation.

In addition, in Figures 4 and 5, except for the first refresh command SB CMD, the count signal Bank Counter, the count reset signal Bank Counter Reset and the SameBank refresh clock signal SB CBR CLK, all signals show 4 cycles of Waveform, where if the waveform of each cycle includes two valid pulses, the valid pulse with earlier timing is the first pulse, and the valid pulse with later timing is the second pulse. The signal waveforms in subsequent figures are also divided according to similar rules and will not be described again.

In some embodiments of the present disclosure, as shown in FIGS. 3 and 4 , the refresh control circuit 101 includes: a refresh window signal generation circuit 201 and a clock pulse generation circuit 202 .

The refresh window signal generation circuit 201 is used to receive a plurality of first refresh instructions SB CMD (ie, SB CMD<0> to SB CMD<m-1> shown in Figure 3) and a refresh window reset signal Refresh Window Reset. According to the plurality of The first refresh command SB CMD and the refresh window reset signal Refresh Window Reset generate the refresh window signal Refresh Window. Among them, referring to Figure 4, the pulse duration of the refresh window signal Refresh Window is the window time for the refresh control circuit 101 to perform a refresh operation, and the refresh window reset signal Refresh Window Reset is used to reset the refresh window signal generation circuit 201 after a refresh operation. Perform a reset. Here, the refresh operation performed by the refresh control circuit 101 is the first refresh operation, that is, the first refresh operation is performed on the Bank corresponding to the first refresh command SB CMD.

The clock pulse generation circuit 202 is coupled to the refresh window signal generation circuit 201 for receiving the refresh window signal Refresh Window and the first refresh command SB CMD. The number of the first refresh commands SB CMD received by the clock pulse generation circuit 202 is less than or equal to m. The first clock signal is generated before the m-th first refresh operation ends, or the second clock signal is generated after the m-th first refresh operation ends. Referring to Figure 4, the SameBank refresh clock signal includes a first clock signal and a second clock signal, that is, the first clock signal and the second clock signal are values of the SameBank refresh clock signal in different periods.

In some embodiments of the present disclosure, as shown in FIGS. 3 and 4 , the clock pulse generating circuit 202 includes: a counting circuit 203 , a counting reset signal generating circuit 204 and a first pulse generating sub-circuit 205 .

The counting circuit 203 is used to receive the first refresh command SB CMD and the count reset signal Bank Counter Reset, count the first refresh command SB CMD, and output the count signal Bank Counter, and reset according to the count reset signal Bank Counter Reset.

The count reset signal generation circuit 204 is coupled to the counting circuit 203 and the refresh window signal generation circuit 201, and is used to generate a count reset signal Bank Counter Reset after the mth first refresh operation is completed.

The first pulse generation sub-circuit 205 is coupled to the count reset signal generation circuit 204 and is used to generate a first clock signal according to the counting signal BankCounter when the first refresh instructions SB CMD are less than m, or when the first refresh instructions SB CMD are equal to m times, the second clock signal is generated according to the count reset signal Bank Counter Reset.

In some embodiments of the present disclosure, as shown in FIG. 3 and FIG. 4 , the refresh window signal generation circuit 201 includes: a plurality of refresh window sub-signal generation circuits 206 and a refresh window sub-signal processing circuit 207 .

The plurality of refresh window sub-signal generating circuits 206 are used to receive the refresh window reset signal Refresh Window Reset and respectively receive a plurality of first refresh instructions SB CMD in sequence. According to the plurality of first refresh instructions SB CMD and the refresh window reset signal Refresh Window Reset A plurality of refresh window sub-signals ReW (ie, ReW<0> to ReW<m-1> shown in FIG. 3) are output in sequence.

The refresh window sub-signal processing circuit 207 is coupled to multiple refresh window sub-signal generating circuits 206, and is used to receive multiple refresh window sub-signals ReW in sequence, perform logical operations on the refresh window sub-signals ReW, and output the refresh window signal Refresh Window.

In some embodiments of the present disclosure, as shown in Figures 3 and 5, the refresh control circuit 101 is also used to receive the second refresh command AB CMD and perform the second refresh operation.

Among them, multiple refresh window sub-signal generation circuits 206 are also used to simultaneously receive the second refresh command AB CMD and the refresh window reset signal Refresh Window Reset, and generate one-to-one correspondence according to the second refresh command AB CMD and the refresh window reset signal Refresh Window Reset. The same multiple refresh window sub-signals ReW.

The refresh window sub-signal processing circuit 207 is also used to receive multiple refresh window sub-signals ReW, perform logical operations on the refresh window sub-signals ReW, and output a refresh window signal Refresh Window.

It should be noted that the second refresh operation is performed on all banks in the Bank Group at the same time, that is, All Bank Refresh. When the refresh control circuit 101 receives the second refresh command AB CMD and performs the second refresh operation, the first refresh command SB CMD does not include a valid pulse and remains low, that is, the first refresh command SB CMD is invalid, and then the count The signal Bank Counter also remains low, and the count refresh signal Bank Counter Reset does not generate a valid pulse and remains low.

Correspondingly, when the refresh control circuit 101 receives multiple first refresh commands SB CMD in sequence and performs the first refresh operation, the second refresh command AB CMD does not include valid pulses and remains low, that is, the second refresh command SB CMD is invalid.

In the embodiment of the present disclosure, when multiple refresh window sub-signal generation circuits 206 receive multiple first refresh commands SB CMD, since the multiple first refresh commands SB CMD are different, the multiple refresh window sub-signals ReW generated are Each is different. When the multiple refresh window sub-signal generating circuits 206 receive the second refresh command AB CMD, they can generate multiple identical refresh window sub-signals ReW.

It can be understood that the refresh control circuit 101 can sequentially receive multiple first refresh commands SB CMD and perform the first refresh operation as needed, or receive the second refresh command AB CMD and perform the second refresh operation. That is to say, using one set of refresh control circuit 101 can flexibly perform two refresh operations, thus improving the compatibility of the circuit.

In some embodiments of the present disclosure, as shown in Figure 3, the refresh control circuit 101 also includes: a second pulse generation sub-circuit 208, an internal refresh window signal generation circuit 209, an address command signal generation circuit 210, and a refresh window reset signal generation circuit. Circuit 211.

In the embodiment of the present disclosure, with reference to Figures 3, 4 and 5, the second pulse generation sub-circuit 208 is coupled to the refresh window sub-signal processing circuit 207 for receiving the refresh window signal Refresh Window and the address command signal Addr CMD. During the refresh When the control circuit 101 starts to perform the first refresh operation or the second refresh operation, it generates the first pulse of the third clock signal AB CBR CLK, and outputs the second pulse of the third clock signal AB CBR CLK according to the first pulse of the address command signal Addr CMD. pulse, thereby outputting the third clock signal AB CBR CLK.

Referring to FIG. 4 , when the refresh control circuit 101 sequentially receives a plurality of first refresh commands SB CMD and performs a first refresh operation, the first pulse of the third clock signal AB CBR CLK is aligned with the plurality of first refresh commands SB CMD< The valid pulses of 0>~SB CMD<3>, that is, the first pulse of the third clock signal AB CBR CLK is generated when the refresh control circuit 101 starts to perform the first refresh operation; the second pulse of the third clock signal AB CBR CLK Aligned to the first pulse of the address command signal Addr CMD, that is, the second pulse of the third clock signal AB CBR CLK is generated based on the first pulse of the address command signal Addr CMD.

Referring to Figure 5, when the refresh control circuit 101 receives the second refresh command AB CMD and performs the second refresh operation, the first pulse of the third clock signal AB CBR CLK is aligned with the effective pulse of the second refresh command AB CMD, that is, the first pulse of the third clock signal AB CBR CLK is aligned with the valid pulse of the second refresh command AB CMD. The first pulse of the third clock signal AB CBR CLK is generated when the refresh control circuit 101 starts to perform the second refresh operation; the second pulse of the third clock signal AB CBR CLK is aligned with the first pulse of the address command signal Addr CMD, that is, the second pulse of the third clock signal AB CBR CLK. The second pulse of the three clock signals AB CBR CLK is generated based on the first pulse of the address command signal Addr CMD.

In the disclosed embodiment, referring to Figures 3, 4 and 5, the internal refresh window signal generation circuit 209 receives the third clock signal AB CBR CLK and is used to generate the internal refresh window signal Inner ACT Window according to the third clock signal AB CBR CLK. ; Among them, the first pulse of the internal refresh window signal Inner ACT Window is generated after the first pulse of the third clock signal AB CBR CLK, and ends before the second pulse of the third clock signal AB CBR CLK is generated; the internal refresh window signal The second pulse of the Inner ACT Window is generated after the second pulse of the third clock signal AB CBR CLK and ends before the pulse of the refresh window signal Refresh Window ends. It should be noted that the refresh controller in the memory will receive the internal refresh window signal Inner ACT Window and the address to be refreshed Adress and refresh the storage unit according to the internal refresh window signal Inner ACT Window, so the internal refresh window signal Inner ACT Window pulse The duration is the time for the storage unit to be refreshed.

In the embodiment of the present disclosure, with reference to Figures 3, 4 and 5, the address command signal generation circuit 210 is used to generate the first pulse and the second pulse of the address command signal Addr CMD according to the falling edge of the internal refresh window signal Inner ACT Window; Among them, the first pulse of the address command signal Addr CMD is used to generate the second pulse of the internal refresh window signal Inner ACT Window and the second pulse of the third clock signal AB CBR CLK. A falling edge of the internal refresh window signal Inner ACT Window indicates the end of the refresh of an address, thereby generating the address command signal Addr CMD to control the generation of the next address.

Referring to Figure 4 and Figure 5, the effective pulse of the internal refresh window signal Inner ACT Window can be compressed and shifted to obtain the effective pulse of the internal pre-command signal Inner PRE CMD. That is to say, first according to the internal refresh window signal Inner ACT Window The falling edge of the internal pre-command signal Inner PRE CMD is obtained; then, the address command signal generation circuit 210 can generate the first pulse and the second pulse of the address command signal Addr CMD according to the falling edge of the internal pre-command signal Inner PRE CMD.

In the embodiment of the present disclosure, with reference to Figures 3, 4 and 5, the refresh window reset signal generation circuit 211 receives the internal refresh window signal Inner ACT Window and is used to generate the signal based on the falling edge of the second pulse of the internal refresh window signal Inner ACT Window. Refresh window reset signal Refresh Window Reset pulse.

In some embodiments of the present disclosure, as shown in FIG. 3 , the refresh control circuit 101 further includes: a signal selection circuit 212 .

In the embodiment of the present disclosure, with reference to Figures 3, 4 and 5, the signal selection circuit 212 is coupled to the counting circuit 203, the first pulse generating sub-circuit 205 and the second pulse generating sub-circuit 208 for receiving the counting signal Bank Counter, the first The clock signal, the second clock signal (the first clock signal and the second clock signal are the SameBank refresh clock signal SB CBR CLK) and the third clock signal AB CBR CLK, when the refresh control circuit 101 performs the first refresh operation, according to the count signal The Bank Counter outputs the first clock signal or the second clock signal, or when the refresh control circuit 101 performs the second refresh operation, the Bank Counter outputs the third clock signal AB CBR CLK according to the counting signal.

Referring to Figures 3 and 4, when the refresh control circuit 101 performs the first refresh operation, if any count signal Bank Counter is high level, the signal selection circuit 212 outputs the first clock signal, that is, outputs the SameBank refresh clock signal. SB CBR CLK is low level. If all count signals Bank Counter jump to low level, the signal selection circuit 212 outputs the second clock signal, that is, outputs two consecutive valid pulses in the SameBank refresh clock signal SB CBR CLK.

Referring to Figures 3 and 5, when the refresh control circuit 101 performs the second refresh operation, all count signals Bank Counter remain low (not shown in Figure 5), then the signal selection circuit 212 outputs the third clock signal AB CBR valid pulse in CLK.

In some embodiments of the present disclosure, as shown in FIG. 3 , the refresh control circuit 101 further includes: an address flag signal generating circuit 213 .

In the embodiment of the present disclosure, referring to Figures 3, 4 and 5, the address flag signal generation circuit 213 is coupled to the address command signal generation circuit 210 and the refresh window sub-signal processing circuit 207 for receiving the address command signal Addr CMD and the refresh window. The signal Refresh Window generates the rising edge of the address flag signal Addr Flag according to the first rising edge of the address command signal Addr CMD, and generates the falling edge of the address flag signal Addr Flag according to the falling edge of the refresh window signal Refresh Window.

In some embodiments of the present disclosure, as shown in FIG. 6 , the repeated command processing circuit 102 includes: a repeated command determining circuit 401 and an additional refresh flag signal generating circuit 402 .

The repeated instruction determination circuit 401 is coupled to the counting circuit 203 for receiving the first refresh instruction SB CMD and the counting signal Bank Counter, and does not output when there is no repeated instruction in the first refresh instruction SB CMD, and when the first refresh instruction SB CMD When a repeated command occurs in SB CMD, the repeated command Extra CMD is output.

The extra refresh flag signal generation circuit 402 is coupled to the repetition instruction determination circuit 401 and the refresh window signal generation circuit 201, and is used to receive the repetition instruction Extra CMD and the refresh window signal Refresh Window, and generate additional refresh according to the repetition instruction Extra CMD and the refresh window signal Refresh Window. Flag signal Extra Refresh Flag; among them, the rising edge of the extra refresh flag signal Extra Refresh Flag is generated based on the valid pulse of the repeated instruction Extra CMD, and the falling edge of the extra refresh flag signal Extra Refresh Flag is based on the falling edge of the refresh window signal Refresh Window. generated along.

Figure 7 takes the preset quantity value m of the first refresh command SB CMD as an example, which is equal to 4, and illustrates the waveforms of each signal in Figure 6. In this disclosed embodiment, combined with Figure 6 and Figure 7, the repeated command refers to an additional refresh command issued to a certain bank. As shown in Figure 7, the first refresh command SB CMD<0> includes two pulses, The previous pulse has triggered the first refresh operation of Bank0, and the next pulse is a repeated instruction. The repeated instruction determination circuit 401 can determine whether a repeated instruction occurs in the corresponding first refresh instruction SB CMD according to the count signal Bank Counter. For example, in Figure 7, the normal first refresh instructions SB CMD<0>~SB CMD<3> except for the repeated instructions, the pulse timing is the same as the rising edge of the corresponding count signal Bank Counter<0>~Bank Counter<3> Aligned one by one; and the pulse timing of the repeated instruction in the first refresh instruction SB CMD<0> is only aligned with the high level state of the count signal Bank Counter<0>. Therefore, the normal first refresh instruction and the repeated instruction can be The difference in timing of instructions determines the duplicate instructions.

Continuing to refer to Figures 6 and 7, after determining the repeated command, the repeated command determination circuit 401 can output the valid pulse of the repeated command, that is, output the repeated command Extra CMD (not shown in Figure 7). After the extra refresh flag signal generation circuit 402 receives the repeated command Extra CMD, it can respond to the valid pulse in the repeated command Extra CMD and jump the extra refresh flag signal Extra Refresh Flag from low level to high level, that is, the extra refresh flag The rising edge of the signal Extra Refresh Flag is generated based on the valid pulse of the repeat command Extra CMD. The extra refresh flag signal generation circuit 402 also receives the refresh window signal Refresh Window, and can respond to the refresh window signal Refresh Window by jumping the extra refresh flag signal Extra Refresh Flag from high level to low level, that is, the extra refresh flag signal Extra Refresh The falling edge of Flag is generated based on the falling edge of the refresh window signal Refresh Window.

In some embodiments of the present disclosure, referring to FIG. 8 , the address generator 103 includes: an address counter 301 and an address processing circuit 302 .

The address counter 301 is coupled to the signal selection circuit 212, used to prestore the first address, and receives the SameBank refresh clock signal SB CBR CLK or the third clock signal AB CBR CLK (not shown in Figure 6) from the signal selection circuit 212. The address counter 301 can change the first address to the third address according to the second clock signal in the SameBank refresh clock signal SB CBR CLK, or change the first address and output the fourth address and the fifth address according to the third clock signal AB CBR CLK. .

The address processing circuit 302 is coupled to the address counter 301, the refresh window sub-signal generation circuit 206 and the repeated command processing circuit 102, and is used to receive the address flag signal Addr Flag when the refresh control circuit performs the first refresh operation, and obtain the first address. If the Extra Refresh Flag signal is not received, the first address or the second address will be output according to the address flag signal Addr Flag. If the Extra Refresh Flag signal is received, the first address or the second address will be output within the window time of the Extra Refresh Flag signal. Internally output additional addresses;

The address processing circuit 302 is also configured to sequentially obtain the fourth address and the fifth address when the refresh control circuit performs the second refresh operation, and sequentially output the fourth address and the fifth address according to the plurality of refresh window sub-signals ReW.

In the embodiment of the present disclosure, when the refresh control circuit performs the first refresh operation and the address processing circuit 302 does not receive the extra refresh flag signal Extra Refresh Flag, the first address is a prestored address, and the second address is an adjacent address. As for the first address, that is, the first address and the second address are two consecutive addresses. Therefore, the third address accumulates the value 2 on the basis of the first address to avoid repeating the first refresh operation on the same address. In this way, after all banks have completed the first refresh operation of the first address and the second address, the first address is converted into the third address by the accumulated value 2, and the refresh control circuit can use the third address as a pre-stored address. A new round of the first refresh operation is performed, thereby ensuring that the first refresh operation is performed without missing a beat.

In the embodiment of the present disclosure, when the refresh control circuit performs the second refresh operation, the first address is a prestored address, the fourth address has a value of 1 accumulated on the basis of the first address, and the fifth address is at the fourth address. The value 1 is accumulated on the basis of , that is to say, the first address, the fourth address and the fifth address are three consecutive addresses in sequence. In this way, the refresh control circuit 101 can sequentially perform the second refresh operation on the addresses of all banks in address order, thereby ensuring that the second refresh operation is performed without missing a beat.

In the embodiment of the present disclosure, in conjunction with Figure 4 and Figure 8, when the signal selection circuit 212 outputs the second clock signal (ie, the two valid pulses in SB CBR CLK) to the address counter 301, the address counter 301 can be based on the second clock signal. The two valid pulses of the clock signal sequentially accumulate the value 2 on the basis of the first address, thereby obtaining the third address. When the signal selection circuit 212 outputs the third clock signal AB CBR CLK to the address counter 301, the address counter 301 can accumulate the value 1 on the basis of the first address according to the first pulse of the third clock signal AB CBR CLK to obtain the third four addresses, and then the address counter 301 can accumulate the value 1 based on the fourth address according to the second pulse of the third clock signal AB CBR CLK to obtain the fifth address.

In the embodiment of the present disclosure, when the refresh control circuit performs the first refresh operation and the address processing circuit 302 receives the extra refresh flag signal Extra Refresh Flag, the address processing circuit 302 operates within the window time of the extra refresh flag signal Extra Refresh Flag. Output additional addresses. Combining Figure 2 and Figure 8, the address processing circuit 302 can select the target bit or the inverted target bit for output according to two different levels of the extra refresh flag signal Extra Refresh Flag. When the extra refresh flag signal Extra Refresh Flag is low level, the address processing circuit 302 can select the target bit for output, and combine it with the address bits other than the target bit to form a regular address n or n+1 for output; when the extra refresh flag signal When the Extra Refresh Flag is high, the address processing circuit 302 can select the inverted target bit for output, and combine it with the address bits other than the target bit to form an additional address k or k+1 for output, where the additional address k is It is obtained by inverting the target bit of the first address n, and the additional address k+1 is obtained by inverting the target bit of the second address n+1.

For example, the first address n is "0000 0000 0000 0010", then the second address n+1 is "0000 0000 0000 0011", and the regular address includes the first address n and the second address n+1. The target bit is the second bit from left to right (i.e., the second highest bit). In this way, by inverting the target bit in the first address n, we can get the additional address k as "0100 0000 0000 0010". Inverting the target bit can obtain the additional address k+1 as "0100 0000 0000 0011". It should be noted that the target bit can be any address bit higher than the preset bit. For example, if the preset bit is the third bit from left to right, then the target bit can be the first bit from left to right (i.e. The highest digit) or the second digit from left to right (i.e. the second highest digit).

It can be understood that the address generator 103 selects the target bit or the inverted target bit for output when triggered by the extra refresh flag signal Extra Refresh Flag, so that when redundant repeated instructions appear in the first refresh instruction, the address generator 103 can output Additional address. In this way, the extra repeated instructions in the first refresh instruction are used to refresh the additional addresses that need to be refreshed, thereby avoiding the waste of instructions and improving the refresh efficiency.

In some embodiments of the present disclosure, as shown in FIG. 9 , the address processing circuit 302 includes: a control signal generation circuit 303 , an address selection circuit 304 and an additional address generation circuit 305 .

The control signal generation circuit 303 is coupled to the refresh window sub-signal generation circuit 206 and the address flag signal generation circuit 213, and is used to receive a plurality of refresh window sub-signals ReW and an address flag signal Addr Flag, according to the plurality of refresh window sub-signals ReW and address flags. The signal Addr Flag generates the address control signal Addr Ctrl.

The address selection circuit 304 is coupled to the address counter 301 and the control signal generation circuit 303, and is used to output the first address before the rising edge of the address control signal Addr Ctrl arrives when the refresh control circuit 101 receives the first refresh command SB CMD, or , after the rising edge of the address control signal Addr Ctrl arrives, the accumulation is performed on the basis of the first address, and the second address is obtained and output. The address selection circuit 304 is also configured to sequentially output the fourth address and the fifth address in response to the address control signal Addr Ctrl when the refresh control circuit 101 receives the second refresh command AB CMD.

The extra address generation circuit 305 is coupled to the address selection circuit 304 and is used to receive and output the first address or Second address. Alternatively, the extra address generation circuit 305 is used to receive the first address or the second address according to the extra refresh flag when the refresh control circuit 101 performs the first refresh operation and the extra address generation circuit 305 receives the extra refresh flag signal Extra Refresh Flag. The signal Extra Refresh Flag inverts the target bit in the first address or the second address to obtain and output an additional address, where the target bit is any address bit in the first address or the second address that is higher than the preset bit. Alternatively, the additional address generation circuit 305 is configured to receive and output the fourth address or the fifth address when the refresh control circuit 101 performs the second refresh operation.

In some embodiments of the present disclosure, as shown in FIG. 10 , the counting circuit 203 includes: a plurality of first inverters D1, a plurality of first latches L1, and a second inverter D2. The input terminals of the plurality of first inverters D1 receive a plurality of first refresh commands SB CMD in sequence. The input terminal of the second inverter D2 receives the count reset signal Bank Counter Reset. The set terminals of the plurality of first latches L1 are connected to the output terminals of the plurality of first inverters D1 in sequence, and the reset terminals of the plurality of first latches L1 are connected to the output terminals of the second inverter D2. A plurality of first latches L1 correspondingly output a plurality of counting signals Bank Counter in sequence.

In the embodiment of the present disclosure, Figure 11 is a signal timing diagram when m=4. Combining Figures 10 and 11, each valid pulse in the first refresh command SB CMD can trigger the corresponding count signal Bank Counter to jump from a low level. to high level. For example, the pulse in the first refresh command SB CMD<0> can trigger the count signal Bank Counter<0> to change from low level to high level. Similarly, the first refresh command SB CMD<1> , The pulses in SB CMD<2> and SB CMD<3> can trigger the counting signals Bank Counter<1>, Bank Counter<2> and Bank Counter<3> respectively from low level to high level. The valid pulse in the count reset signal Bank Counter Reset can trigger all count signals Bank Counter<0>~Bank Counter<3> to jump from high level to low level. The valid pulse in the count reset signal Bank Counter Reset is generated after the refresh control circuit completes the m-th first refresh operation.

In some embodiments of the present disclosure, as shown in Figure 12, the count reset signal generation circuit 204 includes: a first AND gate A1, a third inverter D3, a second AND gate A2, a first delayer H1, a third Quad inverter D4 and third AND gate A3. The input terminal of the first AND gate A1 receives multiple counting signals Bank Counter. The input terminal of the third inverter D3 receives the refresh window signal Refresh Window. The input terminal of the second AND gate A2 is respectively connected to the output terminal of the first AND gate A1 and the output terminal of the third inverter D3. The input terminal of the first delayer H1 is connected to the output terminal of the second AND gate A2. The input terminal of the fourth inverter D4 is connected to the output terminal of the first delay device H1. The input terminal of the third AND gate A3 is respectively connected to the output terminal of the second AND gate A2 and the output terminal of the fourth inverter D4. The third AND gate A3 outputs a count reset signal Bank Counter Reset.

In some embodiments of the present disclosure, as shown in Figure 13, the first pulse generation sub-circuit 205 includes: a second delayer H2, a third delayer H3 and a first OR gate B1. The input terminal of the second delayer H2 receives the count reset signal Bank Counter Reset. The input terminal of the third delayer H3 is connected to the output terminal of the second delayer H2. The input terminals of the first OR gate B1 are respectively connected to the output terminals of the second delayer H2 and the output terminal of the third delayer H3. The first OR gate B1 outputs the first clock signal or the second clock signal, that is to say, The first OR gate B1 outputs the SameBank refresh clock signal SB CBR CLK.

In the embodiment of the present disclosure, Figure 14 is a signal timing diagram when m=4. Combining Figures 12, 13 and 14, when the first refresh operation is performed, the pulses in the count reset signal Bank Counter Reset are based on the count signal Bank Counter<0>, Bank Counter<1>, Bank Counter<2>, Bank Counter<3> and the refresh window signal Refresh Window are generated. A valid pulse in the count reset signal Bank Counter Reset, after passing through the second delayer H2, the third delayer H3 and the first OR gate B1, generates two valid pulses in the SB CBR CLK. Among them, the first delayer H1 can delay the received signal by 0~2ns, the second delayer H2 can delay the received signal by 1~3ns, and the third delayer H3 can delay the received signal by 0~2ns. The delay is 4~6ns.

In some embodiments of the present disclosure, as shown in FIG. 15 , the refresh window sub-signal includes: a first refresh window sub-signal ReW or a second refresh window sub-signal ReW<AB>. Each refresh window sub-signal generating circuit 206 includes: a first NOR gate E1 and a second latch L2. When the refresh control circuit performs the first refresh operation, the first input terminal of the first NOR gate E1 receives the corresponding first refresh instruction SBCMD, or when the refresh control circuit performs the second refresh operation, the first OR The second input terminal of the NOT gate E1 receives the second refresh command ABCMD. The set terminal of the second latch L2 is connected to the output terminal of the first NOR gate E1, and the reset terminal of the second latch L2 receives the refresh window reset signal Refresh Window Reset; when the refresh control circuit performs the first refresh operation, The second latch L2 outputs the corresponding first refresh window sub-signal ReW, or when the refresh control circuit performs the second refresh operation, the second latch L2 outputs the corresponding second refresh window sub-signal ReW< AB>. Here, i is greater than or equal to 0 and less than or equal to m-1, the first refresh command SB CMD is any one of multiple first refresh commands, and the first refresh window sub-signal ReW corresponds to the first refresh command SB CMD.

In the embodiment of the present disclosure, Figure 16 is a signal timing diagram when m=4. Combining Figures 15 and 16, when the refresh control circuit performs the first refresh operation, the effective pulse in the first refresh command SB CMD<0> triggers The first refresh window sub-signal ReW<0> jumps from low level to high level, and the first valid pulse in the refresh window reset signal Refresh Window Reset triggers the first refresh window sub-signal ReW<0> from high level. Jumps to low level, thereby obtaining the valid pulse of the first refresh window sub-signal ReW<0>. Similarly, the valid pulses in the first refresh instructions SB CMD<0>, SB CMD<1> and SB CMD<2> trigger the first refresh window sub-signals ReW<0>, ReW<1> and ReW<2> respectively. Jumping from low level to high level, the second to four valid pulses in the refresh window reset signal Refresh Window Reset trigger the first refresh window sub-signals ReW<0>, ReW<1> and ReW<2> respectively. The high level jumps to the low level, thereby obtaining effective pulses of the first refresh window sub-signals ReW<0>, ReW<1> and ReW<2>.

In the embodiment of the present disclosure, combined with Figure 15 and Figure 17, when the refresh control circuit performs the second refresh operation, the valid pulse in the second refresh command AB CMD triggers the second refresh window sub-signal ReW<AB> to jump from a low level to high level, the valid pulse in the refresh window reset signal Refresh Window Reset triggers the second refresh window sub-signal ReW<AB> to jump from high level to low level, thereby obtaining the second refresh window sub-signal ReW<AB > effective pulse.

In some embodiments of the present disclosure, in conjunction with FIG. 15 and FIG. 18 , the refresh window sub-signal processing circuit 207 includes: a second OR gate B2. When the refresh control circuit performs the first refresh operation, the input end of the second OR gate B2 receives a plurality of first refresh window sub-signals ReW from the plurality of refresh window sub-signal generating circuits 206 respectively, or when the refresh control circuit When performing the second refresh operation, the input terminal of the second OR gate receives the same plurality of second refresh window sub-signals ReW<AB> from the plurality of refresh window sub-signal generating circuits 206 respectively. The second OR gate B2 outputs the refresh window signal Refresh Window.

In the embodiment of the present disclosure, referring to FIG. 18 , the refresh window signal generation circuit 201 further includes a twelfth inverter D12. The refresh window reset signal Refresh Window Reset is transmitted to multiple refresh window sub-signal generating circuits 206 through the twelfth inverter D12.

In the embodiment of the present disclosure, with reference to Figures 16 and 18, when the refresh control circuit performs the first refresh operation, since the first refresh window sub-signals ReW<0>~ReW<3> are all active at high level, the The refresh window signal Refresh Window output by the second OR gate B2 will include all valid pulses in the first refresh window sub-signal ReW<0>~ReW<3>.

In the embodiment of the present disclosure, with reference to Figures 17 and 18, when the refresh control circuit performs the second refresh operation, the second OR gate B2 receives the same plurality of second refresh window sub-signals ReW<AB>, and the second OR gate B2 The refresh window signal Refresh Window output by B2 has the same waveform as the second refresh window sub-signal ReW<AB>.

In some embodiments of the present disclosure, as shown in Figure 19, the second pulse generation sub-circuit 208 includes: a fourth delayer H4, a fifth inverter D5, a fourth AND gate A4, and a sixth inverter D6 , the fifth AND gate A5, the second NOR gate E2 and the seventh inverter D7. The input terminal of the fourth delayer H4 receives the refresh window signal Refresh Window. The input terminal of the fifth inverter D5 is connected to the output terminal of the fourth delayer H4. The first input terminal of the fourth AND gate A4 receives the refresh window signal Refresh Window, and the second input terminal of the fourth AND gate A4 is connected to the output terminal of the fifth inverter D5. The input terminal of the sixth inverter D6 receives the address flag signal Addr Flag. The first input terminal of the fifth AND gate A5 is connected to the output terminal of the sixth inverter D6, and the second input terminal of the fifth AND gate A5 receives the address command signal Addr CMD. The input terminal of the second NOR gate E2 is respectively connected to the output terminal of the fourth AND gate A4 and the output terminal of the fifth AND gate A5. The input terminal of the seventh inverter D7 is connected to the output terminal of the second NOR gate E2, and the seventh inverter D7 outputs the third clock signal AB CBR CLK.

In the embodiment of the present disclosure, referring to Figures 19 and 20, the fourth delayer H4 can delay the received refresh window signal Refresh Window by 1 to 3 ns. Furthermore, after the refresh window signal Refresh Window passes through the fourth delayer H4, the fifth inverter D5 and the fourth AND gate A4, it can be converted into the internal activation command signal Inner ACT CMD. Among them, the pulse in the internal activation command signal Inner ACT CMD corresponds to the rising edge of the refresh window signal Refresh Window. After passing through the second NOR gate E2 and the seventh inverter D7, the pulse forms the third clock signal AB CBR CLK the first pulse. The second pulse of the third clock signal AB CBR CLK is formed based on the address flag signal Addr Flag and the address command signal Addr CMD.

In some embodiments of the present disclosure, as shown in FIG. 21 , the address command signal generation circuit 210 includes: an eighth inverter D8, a fifth delayer H5, and a sixth AND gate A6. The input terminal of the eighth inverter D8 receives the internal refresh window signal Inner ACT Window. The input terminal of the fifth delayer H5 is connected to the input terminal of the eighth inverter D8 and receives the internal refresh window signal Inner ACT Window. The input terminals of the sixth AND gate A6 are respectively connected to the output terminal of the eighth inverter D8 and the output terminal of the fifth delay device H5. The sixth AND gate A6 outputs the address command signal Addr CMD.

In this disclosed embodiment, the fifth delayer H5 can delay the received internal refresh window signal Inner ACT Window by 0 to 2 ns. Combining Figure 21 and Figure 22, through the eighth inverter D8, the fifth delay H5 and the sixth AND gate A6, the first pulse of the internal refresh window signal Inner ACT Window can be converted into the third pulse of the address command signal Addr CMD. One pulse, the second pulse of the internal refresh window signal Inner ACT Window can be converted into the second pulse of the address command signal Addr CMD.

In some embodiments of the present disclosure, as shown in FIG. 21 , the internal refresh window signal generation circuit 209 includes: a third latch L3. The set terminal of the third latch L3 receives the third clock signal AB CBR CLK, the reset terminal of the third latch L3 is connected to the output terminal of the eighth inverter D8, and the third latch L3 outputs the internal refresh window signal. Inner ACT Window.

In some embodiments of the present disclosure, as shown in Figure 23, the refresh window reset signal generation circuit 211 includes: a sixth delayer H6, a seventh AND gate A7, and a seventh delayer H7. The input terminal of the sixth delayer H6 receives the address flag signal Addr Flag. The first input terminal of the seventh AND gate A7 is connected to the output terminal of the sixth delayer H6, and the second input terminal of the seventh AND gate A7 receives the internal refresh window signal Inner ACT Window. The input terminal of the seventh delayer H7 is connected to the output terminal of the seventh AND gate A7, and the seventh delayer H7 outputs the refresh window reset signal Refresh Window Reset.

In the embodiment of the present disclosure, the sixth delayer H6 can delay the received address flag signal Addr Flag by 0 to 2 ns, and the seventh delayer H7 can delay the received signal by 4 to 6 ns. Combining Figure 23 and Figure 24, through the sixth delayer H6, the seventh AND gate A7 and the seventh delayer H7, the refresh window reset signal Refresh Window can be obtained from the internal refresh window signal Inner ACT Window and the address flag signal Addr Flag. Reset.

In some embodiments of the present disclosure, as shown in FIG. 25 , the signal selection circuit 212 includes: a third NOR gate E3, a third OR gate B3, and an eighth AND gate A8. The input terminals of the third NOR gate E3 respectively receive multiple counting signals Bank Counter. The first input terminal of the third OR gate B3 receives the first clock signal or the second clock signal, that is, the first input terminal of the third OR gate B3 receives the SameBank refresh clock signal SB CBR CLK, and the second input terminal of the third OR gate B3 The terminal receives the third clock signal AB CBR CLK. The first input terminal of the eighth AND gate A8 is connected to the output terminal of the third NOR gate E3, the second input terminal of the eighth AND gate A8 is connected to the output terminal of the third OR gate B3, and the eighth AND gate A8 outputs the first clock. signal, the second clock signal or the third clock signal AB CBR CLK.

In the embodiment of the present disclosure, with reference to Figure 4 and Figure 25, when the first refresh operation is performed, the waveforms of each signal received by the signal selection circuit 212 are as shown in Figure 4. In this way, the third OR gate B3 outputs The signal can include all valid pulses in the SameBank refresh clock signal SB CBR CLK and the third clock signal AB CBR CLK. However, the signal output by the third NOR gate E3 can shield the valid pulses in the third clock signal AB CBR CLK. , thus, the signal output by the eighth AND gate A8 has the same waveform as the SameBank refresh clock signal SB CBR CLK. That is to say, when the first refresh operation is performed, the eighth AND gate A8 outputs the first clock signal or the second clock signal.

In the case of the second refresh operation, the multiple count signals Bank Counter<0>~Bank Counter<3> and the SameBank refresh clock signal SB CBR CLK all remain low (not shown in Figure 4), and the third The waveform of the clock signal AB CBR CLK is still as shown in Figure 4. In this way, the signal output by the eighth AND gate A8 is the same as the waveform of the third clock signal AB CBR CLK. That is to say, when the first refresh operation is performed, The eighth AND gate A8 outputs the third clock signal AB CBR CLK.

In some embodiments of the present disclosure, as shown in FIG. 26 , the address flag signal generation circuit 213 includes: a ninth inverter D9 and a fourth latch L4. The input terminal of the ninth inverter D9 receives the address command signal Addr CMD. The set terminal of the fourth latch L4 is connected to the output terminal of the ninth inverter D9, the reset terminal of the fourth latch L4 receives the refresh window signal Refresh Window, and the fourth latch L4 outputs the address flag signal Addr Flag.

In this disclosed embodiment, combined with Figure 26 and Figure 27, the first pulse of the address command signal Addr CMD triggers the address flag signal Addr Flag to jump from low level to high level, and the falling edge of the refresh window signal Refresh Window triggers the address flag. The signal Addr Flag jumps from high level to low level, thereby obtaining the waveform of the address flag signal Addr Flag shown in Figure 27.

Figure 28 shows an optional implementation of the refresh control circuit 101. Figure 28 includes Figures 10, 12, 13, 15, 18, 19, 21, 23, 25 and Circuit elements shown in Figure 26. Figures 29 and 30 show an optional waveform diagram of some of the signals in Figure 28. Figure 29 is a schematic diagram of the corresponding signals when the refresh control circuit 101 performs the first refresh operation. Figure 30 is a schematic diagram of the refresh control circuit. 101 corresponds to the signal diagram when performing the second refresh operation.

Figure 28 takes the number of Banks in Bank Group m = 4 as an example. Therefore, Figure 28 includes 4 first latches L1, 4 first inverters D1, and 4 refresh window sub-signal generation circuits 206 .

Combined with Figure 28 and Figure 29, when the refresh control circuit 101 performs the first refresh operation, the four first refresh instructions SB CMD<0>, SB CMD<1>, SB CMD<2> and SB CMD<3> includes valid pulses, while the second refresh command AB CMD (not shown in Figure 29) does not include valid pulses, that is, the second refresh command AB CMD remains low. Therefore, the set ends of the four first latches L1 respectively receive the four first refresh instructions SB CMD<0>, SB CMD<1>, SB CMD<2> and SB through the four first inverters D1. CMD<3>, the four first latches L1 respectively output four counting signals Bank Counter<0>, Bank Counter<1>, Bank Counter<2> and Bank Counter<3> to the third NOR gate E3 input terminal and the input terminal of the first AND gate A1. Furthermore, the signal selection circuit 212 outputs the SameBank refresh clock signal SB CBR CLK (ie, the first clock signal or the second clock signal) through the eighth AND gate A8. At the same time, the set ends of the four second latches L2 receive the four first refresh instructions SB CMD<0>, SB CMD<1>, SB CMD<2> and SB respectively through the four first NOR gates E1. CMD<3>, the four second latches L2 respectively output four first refresh window sub-signals ReW<0>, ReW<1>, ReW<2> and ReW<3>.

Combining Figure 9, Figure 28 and Figure 29, it can be seen that when the refresh control circuit 101 performs the first refresh operation, the signal selection circuit 212 outputs the SameBank refresh clock signal SB CBR CLK (ie, the first clock signal or the second clock signal) to Address processing circuit 302, four refresh window sub-signal generation circuits 206 output four first refresh window sub-signals ReW<0>, ReW<1>, ReW<2> and ReW<3> to the address processing circuit 302, address flag The signal generation circuit 213 outputs the address flag signal Addr Flag to the address processing circuit 302.

Combining Figure 28 and Figure 30, when the refresh control circuit 101 performs the second refresh operation, the four first refresh instructions SB CMD<0>, SB CMD<1>, SB CMD<2> and SB CMD<3> (not shown in Figure 30) does not include valid pulses, that is, the four first refresh instructions SB CMD<0>, SB CMD<1>, SB CMD<2> and SB CMD<3> all remain low , and the second refresh command AB CMD includes valid pulses. As a result, the four count signals Bank Counter<0>, Bank Counter<1>, Bank Counter<2> and Bank Counter<3> output by the four first latches L1 all remain low (not shown in Figure 30 out). Furthermore, the signal selection circuit 212 outputs the third clock signal AB CBR CLK through the eighth AND gate A8. At the same time, the set ends of the four second latches L2 receive the second refresh command AB CMD through the four first NOR gates E1, and the four second latches L2 all output four identical second refresh windows. Sub-signal ReW<AB>.

Combining Figure 9, Figure 28 and Figure 30, it can be seen that when the refresh control circuit 101 performs the second refresh operation, the signal selection circuit 212 outputs the third clock signal AB CBR CLK to the address processing circuit 302, and four refresh window sub-signals are generated. The circuit 206 outputs four identical second refresh window sub-signals ReW<AB> to the address processing circuit 302, and the address flag signal generation circuit 213 outputs the address flag signal Addr Flag to the address processing circuit 302.

In some embodiments of the present disclosure, as shown in FIG. 31 , the repeated instruction determination circuit 401 includes: a plurality of eighth delays H8, a plurality of ninth AND gates A9, and a fourth NOR gate E4. The input terminals of multiple eighth delays H8 receive multiple counting signals Bank Counter<0>~Bank Counter<m-1> in sequence. The first input terminals of the plurality of ninth AND gates A9 are connected to the output terminals of the plurality of eighth delays H8 in sequence, and the second input terminals of the plurality of ninth AND gates A9 receive a plurality of first refresh instructions SB CMD<0 in sequence. >~SB CMD<m-1>. The input terminals of the fourth NOR gate E4 are respectively connected to the output terminals of a plurality of ninth AND gates A9, and the fourth NOR gate E4 outputs repeated instructions.

The additional refresh flag signal generating circuit 402 includes: a fifth latch L5. The set end of the fifth latch L5 receives the repeated command Extra CMD, the reset end of the fifth latch L5 receives the refresh window signal Refresh Window, and the fifth latch L5 outputs the extra refresh flag signal Extra Refresh Flag.

In the embodiment of the present disclosure, combined with Figure 31 and Figure 7, taking m=4 as an example, there is a repeated instruction in the first refresh instruction SB CMD<0>. When the repeated instruction is generated, the counting signal Bank Counter<0> is high. flat; after the repeated instruction and the high-level counting signal Bank Counter<0> pass through the ninth AND gate A9 and the fourth NOR gate E4, the fourth NOR gate E4 outputs the repeated instruction Extra CMD to the fifth latch. The set end of L5 triggers the extra refresh flag signal Extra Refresh Flag to jump from low level to high level. In addition, the falling edge of the refresh window signal Refresh Window triggers the extra refresh flag signal Extra Refresh Flag to jump from high level to low level. In this way, a high-level active extra refresh flag signal Extra Refresh Flag is generated.

On the other hand, for the pulses other than repeated instructions (i.e. regular instructions) in the first refresh instructions SB CMD<0>, SB CMD<1>, SB CMD<2> and SB CMD<3>, their corresponding pulses go through the The timing of the counting signals Bank Counter<0>, Bank Counter<1>, Bank Counter<2> and Bank Counter<3> of the delayer H1 is low level. After the regular instructions and the low-level counting signal Bank Counter pass through the ninth AND gate A9 and the fourth NOR gate E4, the signal output by the fourth NOR gate E4 remains low, that is, no repeated refresh instruction Extra will be generated. CMD, in this way, will not trigger the fifth latch L5 to jump the extra refresh flag signal Extra Refresh Flag from low level to high level.

It can be understood that the repeated command processing circuit 102 in the embodiment of the present disclosure uses the repeated command and the corresponding level of the count signal to trigger the generation of an additional refresh flag signal, thereby triggering the address generator 103 to generate an additional address. In this way, the extra repeated instructions in the first refresh instruction are used to refresh the additional addresses that need to be refreshed, thus avoiding the waste of instructions and improving the refresh efficiency.

In some embodiments of the present disclosure, as shown in FIG. 32, the control signal generation circuit 303 includes: a tenth AND gate A10, a tenth inverter A10, and a fifth NOR gate E5. The input terminals of the tenth AND gate A10 respectively receive multiple refresh window sub-signals ReW. The input terminal of the tenth inverter D10 receives the address flag signal Addr Flag. The first input terminal of the fifth NOR gate E5 is connected to the output terminal of the tenth AND gate A10, the second input terminal of the fifth NOR gate E5 is connected to the output terminal of the tenth inverter D10, and the output terminal of the fifth NOR gate E5 is Address control signal Addr Ctrl.

In the embodiment of the present disclosure, FIG. 33 takes m=4 as an example. In combination with FIG. 32 and FIG. 33 , when the refresh control circuit performs the first refresh operation, each input end of the tenth AND gate A10 receives a plurality of first refresh operations respectively. Refresh the window sub-signals ReW<0>, ReW<1>, ReW<2> and ReW<3>, then the signal ReW<And> output by the tenth AND gate A10 is always low level. In this way, the address control signal Addr Ctrl The waveform is the same as the address flag signal Addr Flag, that is to say, the address flag signal Addr Flag still maintains the same waveform after passing through the control signal generation circuit 303.

Combining Figure 32 and Figure 34, when the refresh control circuit performs the second refresh operation, each input terminal of the tenth AND gate A10 receives the same second refresh window sub-signal ReW<AB>, then the tenth AND gate A10 The output signal ReW<And> has the same waveform as the second refresh window sub-signal ReW<AB>, and the high-level area of the signal ReW<And> covers the high-level area of the address flag signal Addr Flag. In this way, through the fifth NOR gate E5, the signal ReW<And> can shield the high level area of the address flag signal Addr Flag, so that the address control signal Addr Ctrl is always low level, that is to say, the address flag signal Addr Flag passes through the control signal generation circuit Blocked after 303.

It should be noted that the multiple first refresh window sub-signals ReW<0>, ReW<1>, ReW<2> and ReW<3> shown in Figure 33 are different from the multiple first refresh window sub-signals shown in Figure 16 The waveforms of the signals ReW<0>, ReW<1>, ReW<2> and ReW<3> are the same, that is to say, the multiple first refresh window sub-signals ReW<0>, ReW<1>, ReW in Figure 33 <2> and ReW<3> can be obtained according to the example of Figure 16. The second refresh window sub-signal ReW<AB> shown in FIG. 34 has the same waveform as the second refresh window sub-signal ReW<AB> shown in FIG. 17 , that is to say, the second refresh window sub-signal ReW< in FIG. 34 AB> can be obtained according to the example in Figure 17.

In some embodiments of the present disclosure, as shown in Figure 35, the address selection circuit 304 includes an adder 306 and a first data selector MUX1.

The input terminal of the adder 306 is connected to the address counter 301 . The adder 306 is used to obtain the first address from the address counter 301 when the refresh control circuit receives the first refresh instruction, and performs accumulation on the basis of the first address to obtain the second address.

The first input terminal of the first data selector MUX1 is connected to the address counter 301, the second input terminal of the first data selector MUX1 is connected to the adder 306, and the control terminal of the first data selector MUX1 receives the address control signal Addr Ctrl. The output terminal of the data selector MUX1 serves as the output terminal of the address selection circuit 304. The first data selector MUX1 is used to obtain the first address from the address counter 301 and the second address from the adder 306 when the refresh control circuit receives the first refresh instruction, and select the first address in response to the address control signal Addr Ctrl. or the second address for output.

In the embodiment of the present disclosure, with reference to Figures 35 and 36, when the refresh control circuit receives the first refresh instruction, the address counter 301 receives the SameBank refresh clock signal SB CBR CLK, that is, receives the first clock signal or the second clock Signal.

When the address counter 301 receives the first clock signal, since the first clock signal does not include a valid pulse, the address counter 301 is not triggered to change the first address. The address output signal Addr Counter Output represents the first address stored by the address counter 301. Referring to FIG. 36, when the address counter 301 receives the first clock signal, the first address remains n unchanged. The first address n is directly transmitted to the first input terminal of the first data selector MUX1 (ie, the input terminal marked "0"). At the same time, the first address n becomes the second address n+1 after passing through the adder 306. The second address n+1 is transmitted to the second input terminal of the first data selector MUX1 (ie, the input terminal labeled "1"). The address Add_1 output by the first data selector MUX1 is controlled by the address control signal Addr Ctrl. Referring to Figure 36, the first data selector MUX1 alternately outputs n and n+1 according to the level of the address control signal Addr Ctrl. That is to say, when the address control signal Addr Ctrl is low level, the first data selector MUX1 outputs the first address n input by its first input terminal; when the address control signal Addr Ctrl is high level, the first data selector MUX1 The device MUX1 outputs the second address n+1 input to its second input terminal. Each group of n and n+1 output by the first data selector MUX1 will be used for the corresponding SameBank in the Bank Group to perform the first refresh operation until all Banks in the Bank Group complete the first refresh operation, that is, the number of first refresh operations Reaching m (taking m=4 as an example in Figure 36), during this process, the first address stored in the address counter 301 remains n unchanged, that is, the address output signal Addr Counter Output reaches the Before m, n is kept unchanged.

When the number of first refresh operations reaches m, that is, after all banks have completed the first refresh operation of this round, the address counter 301 receives the second clock signal. Since the second clock signal includes two valid pulses, the address counter 301 301 will accumulate 2 on the first address, that is, change the first address to the third address. At this time, all banks in the Bank Group have completed the previous round of first refresh operations. After the refresh control circuit receives the next round of first refresh instructions, it can perform the next round of first refresh operations according to the third address.

For example, the current first address is 0000, and 1 is accumulated on the first address to become the second address 0001. In this way, the first refresh operation (Same Bank Refresh) is performed on each bank. After all banks complete the first refresh operation of this round, the address counter 301 is triggered by two pulses in the second clock signal, accumulates 2 to the first address, outputs 0010, and then performs the first refresh operation of the next round.

It should be noted that the waveform of the first clock signal or the second clock signal shown in FIG. 36 is the same as that of the first clock signal or the second clock signal shown in FIG. 2. That is to say, the first clock signal or the second clock signal shown in FIG. Come and get.

It can be understood that when the SameBank in the Bank Group performs the first refresh operation, the first refresh operation will be performed on two adjacent addresses (i.e. the first address and the second address) in a group of SameBanks, and in this process The first address remains unchanged. When all Banks in the Bank Group have completed the first refresh operation on two adjacent addresses, that is, after all Banks in the Bank Group have completed the first refresh operation in the previous round, the first address accumulates 2 and becomes the third address. , the next round of first refresh operation can be performed according to the third address. In this way, the first refresh operation can be performed on the addresses in each bank in the order of the addresses, ensuring the continuity of the refresh addresses and avoiding missing addresses without performing the first refresh operation.

In the embodiment of the present disclosure, referring to Figure 35, the first data selector MUX1 is also used to obtain the fourth address or the fifth address from the address counter 301 when the refresh control circuit receives the second refresh instruction, in response to the address control signal Addr Ctrl , output the fourth address or fifth address.

Referring to Figures 35 and 37, when the refresh control circuit receives the second refresh command, the address counter 301 receives the third clock signal AB CBR CLK. Each valid pulse in the third clock signal AB CBR CLK will trigger the address counter 301 to accumulate 1 on the first address. The address output signal Addr Counter Output represents the first address stored by the address counter 301. Referring to Figure 37, the address output signal Addr Counter Output is accumulated under the trigger of the third clock signal AB CBR CLK. Among them, the third clock signal AB CBR CLK shown in Figure 37 includes four cycles, and every two valid pulses are one cycle. Therefore, in the first cycle, the first address n is triggered to change to the fourth address n. +1 and the fifth address n+2; in the second cycle, n+2 as the first address is triggered to change to the fourth address n+3 and the fifth address n+4, and so on.

At the same time, the address control signal Addr Ctrl remains low, so that the first data selector MUX1 only outputs the fourth address and the fifth address received by its first input terminal. That is to say, the first data selector MUX1 outputs The address Add_1 is consistent with the address output signal Addr Counter Output. In this way, the second refresh operation can be performed on the addresses in all banks in the order of the addresses, thereby avoiding missing addresses and not performing the second refresh operation.

It should be noted that the waveforms of the third clock signal AB CBR CLK shown in Figure 37 and Figure 5 are the same. That is to say, the third clock signal AB CBR CLK shown in Figure 37 can be obtained through the example of Figure 5.

It can be understood that when all Banks in the Bank Group perform the second refresh operation, the address counter 301 generates consecutive addresses (including the fourth address and the fifth address) according to the third clock signal AB CBR CLK, and these consecutive addresses are The address is output through the address selection circuit 304, so that each address in all Banks sequentially completes the second refresh operation (ie, All Bank Refresh). In this way, the second refresh operation can be performed on the addresses in all banks in the order of the addresses, ensuring the continuity of the refresh addresses and avoiding missing addresses without performing the second refresh operation. At the same time, using a set of address generators can flexibly perform two refresh operations, thus improving the compatibility of the circuit.

In some embodiments of the present disclosure, as shown in FIG. 35 , the additional address generation circuit 305 includes: an eleventh inverter D11 , a second data selector MUX2 and an address delay module 307 .

The input terminal of the eleventh inverter D11 is connected to the output terminal of the address selection circuit 304 (that is, connected to the output terminal of the first data selector MUX1). The eleventh inverter D11 is used to obtain the target bit in the first address or the second address from the address selection circuit 304 when the refresh control circuit receives the first refresh instruction, and convert the target bit in the first address or the second address to Output after bit inversion.

The first input terminal of the second data selector MUX2 is connected to the output terminal of the address selection circuit 304 (that is, connected to the output terminal of the first data selector MUX1), and the second input terminal of the second data selector MUX2 is connected to the eleventh inverting The output terminal of device D11. The second data selector MUX2 is used to obtain the first address from the address selection circuit 304 or The target bit in the second address and output the target bit in the first address or the second address. Alternatively, the second data selector MUX2 is used to obtain the data from the eleventh inverter D11 when the refresh control circuit receives the first refresh command and the control end of the second data selector MUX2 receives the extra refresh flag signal Extra Refresh Flag. Invert the target bit in the first address or the second address, and output the inverted target bit in the first address or the second address.

The input terminal of the address delay module 307 is connected to the output terminal of the address selection circuit 304 . The address delay module 307 is used to obtain other bits in the first address or the second address from the address selection circuit 304 and delay other bits in the first address or the second address when the refresh control circuit receives the first refresh instruction. Then output, where the other bits are address bits except the target bit.

In the embodiment of the present disclosure, referring to FIG. 35 , the address Add_1 received by the additional address generation circuit 305 from the address selection circuit 304 is divided into two parts for transmission, in which the target bit of the address Add_1 is transmitted to the second data selector MUX2 The first input terminal (i.e., the input terminal marked "0"), the target bit of the address Add_1 is inverted by the eleventh inverter D11 and then transmitted to the second input terminal (i.e., labeled "1" of the second data selector MUX2 ” input terminal), the other bits in the address Add_1 except the target bit are transmitted to the address delay module 307. That is to say, the second data selector MUX2 selects the target bit of address Add_1 for output according to the extra refresh flag signal Extra Refresh Flag, or selects the target bit of the inverted address Add_1 for output. At the same time, since the target bit of address Add_1 will be delayed in timing after passing through the second data selector MUX2 and the eleventh inverter D11, the other bits in address Add_1 except the target bit need to go through the address Delay module 307 to match timing.

In the embodiment of the present disclosure, with reference to Figure 35 and Figure 38, when the refresh control circuit receives the first refresh command and performs the first refresh operation, if there is a repeated command in the first refresh command, such as the first refresh command SB in Figure 38 If there is a repeated instruction in CMD<0>, the extra refresh flag signal Extra Refresh Flag is output to a high level to the control end of the second data selector MUX2; at this time, the second data selector MUX2 selects the inverted address Add_1 The target bit is output, so that the additional address generation circuit 305 outputs the additional address k or k+1 as the address to be refreshed. Correspondingly, when the refresh control circuit receives the first refresh command and performs the first refresh operation, if there is no repeated command in the first refresh command, as shown in Figure 38, the first refresh command SB CMD<0>~SB CMD<1> At the timing position corresponding to the regular pulse in , the extra refresh flag signal Extra Refresh Flag is output to a low level to the control end of the second data selector MUX2; at this time, the second data selector MUX2 selects the non-inverted address Add_1 The target bit is output, so that the additional address generation circuit 305 outputs the first address n or the second address n+1 as the address to be refreshed, that is, the additional address generation circuit 305 outputs the address Add_1 output by the address selection circuit 304 as the address to be refreshed. AddressAddress.

In the embodiment of the present disclosure, referring to FIG. 35 , when the refresh control circuit receives the second refresh instruction and performs the second refresh operation, the address Add_1 output by the address selection circuit 304 includes the fourth address or the fifth address. At this time, the extra refresh flag signal Extra Refresh Flag remains low. Therefore, the second data selector MUX2 selects the target bit of the address Add_1 that is not inverted for output. Therefore, the extra address generation circuit 305 outputs the fourth address or the fifth address. The address is used as the address to be refreshed, that is, the additional address generation circuit 305 outputs the address Add_1 output by the address selection circuit 304 as the address to be refreshed.

It can be understood that, under the trigger of the extra refresh flag signal Extra Refresh Flag, the address generator 103 selects the target bit in the address Add_1 or the inverted target bit for output through the second data selector MUX2, so that it can be When unnecessary repeated instructions appear in the first refresh instruction, additional addresses are output. In this way, the extra repeated instructions in the first refresh instruction are used to refresh the additional addresses that need to be refreshed, thereby avoiding the waste of instructions and improving the refresh efficiency.

It should be noted that in the present disclosure, the terms "comprising", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device that includes a series of elements not only includes those elements , but also includes other elements not expressly listed or inherent in such process, method, article or apparatus. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article or apparatus that includes that element.

The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. should be covered by the protection scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Industrial applicability

Embodiments of the present disclosure provide a refresh address generation circuit, including: a refresh control circuit, a repeated command processing circuit, and an address generator. The refresh control circuit is configured to receive multiple first refresh instructions in sequence and perform multiple first refresh operations accordingly. When the number of first refresh operations is less than m, it outputs a first clock signal, where m is an integer greater than or equal to 1. The repeated command processing circuit is coupled to the refresh control circuit and is used for receiving the first refresh command and outputting an additional refresh flag signal when a repeated command occurs in the first refresh command. The address generator is coupled to the refresh control circuit and the repeated command processing circuit, and pre-stores the first address, for outputting the address to be refreshed in response to the first clock signal when the first clock signal is received and no additional refresh flag signal is received. , or when receiving the additional refresh flag signal, output an additional address in response to the additional refresh flag signal, wherein the address to be refreshed includes the first address or the second address, the second address is adjacent to the first address, the additional address and the second address The difference of an address is greater than the preset threshold. In this way, the extra repeated instructions in the first refresh instruction are used to refresh the additional addresses that need to be refreshed, thereby achieving effective use of repeated instructions, avoiding instruction waste, and improving refresh efficiency.

Claims

A refresh address generation circuit, the refresh address generation circuit includes:

Refresh control circuit, configured to receive multiple first refresh instructions in sequence and perform multiple first refresh operations correspondingly, and output a first clock signal when the number of first refresh operations is less than m, where m is an integer greater than or equal to 1 ;

a repeated command processing circuit, coupled to the refresh control circuit, for receiving the first refresh command, and outputting an additional refresh flag signal when a repeated command occurs in the first refresh command;

An address generator, coupled to the refresh control circuit and the repeated command processing circuit, and pre-stored a first address for responding when the first clock signal is received and the additional refresh flag signal is not received. Output an address to be refreshed in response to the first clock signal, or when receiving the additional refresh flag signal, output an additional address in response to the additional refresh flag signal; wherein the address to be refreshed includes the first address Or a second address, the second address is adjacent to the first address; the difference between the additional address and the first address is greater than a preset threshold.
The refresh address generation circuit according to claim 1, wherein,

The refresh control circuit is also configured to output a second clock signal when the number of first refresh operations is equal to m;

The address generator is further configured to receive the second clock signal and change the first address to a third address in response to the second clock signal.
The refresh address generation circuit according to claim 2, wherein the refresh control circuit includes:

A refresh window signal generation circuit, configured to receive a plurality of first refresh instructions and a refresh window reset signal, and generate a refresh window signal according to a plurality of the first refresh instructions and the refresh window reset signal; wherein, the refresh window The pulse duration of the signal is the window time for the refresh control circuit to perform a refresh operation, and the refresh window reset signal is used to reset the refresh window signal generation circuit after a refresh operation is completed;

A clock pulse generation circuit, coupled to the refresh window signal generation circuit, for receiving a refresh window signal and the first refresh instruction, where the number of the first refresh instructions received by the clock pulse generation circuit is less than or equal to m And the first clock signal is generated before the m-th first refresh operation ends, or the second clock signal is generated after the m-th first refresh operation ends.
The refresh address generation circuit according to claim 3, wherein the clock pulse generation circuit includes:

A counting circuit configured to receive the first refresh instruction and a count reset signal, count the first refresh instruction, and output a count signal, and perform reset according to the count reset signal;

A counting reset signal generating circuit, coupled to the counting circuit and the refresh window signal generating circuit, for generating the counting reset signal after the mth first refresh operation is completed;

A first pulse generation sub-circuit, coupled to the count reset signal generation circuit, is used to generate the first clock signal according to the count signal when the first refresh instructions are less than m, or, when the first refresh instructions are less than m, When a refresh instruction is equal to m, the second clock signal is generated according to the count reset signal.
The refresh address generation circuit according to claim 3, wherein the refresh window signal generation circuit includes:

A plurality of refresh window sub-signal generating circuits, configured to receive a refresh window reset signal and receive a plurality of first refresh instructions in sequence, and output a plurality of first refresh instructions and the refresh window reset signal in sequence. Refresh window sub-signal;

A refresh window sub-signal processing circuit, coupled to a plurality of the refresh window sub-signal generating circuits, is used to receive a plurality of the refresh window sub-signals in sequence, perform logical operations on the refresh window sub-signals, and output the refresh window signal. .
The refresh address generation circuit according to claim 5, wherein the refresh control circuit is further configured to receive a second refresh instruction and perform a second refresh operation; wherein,

A plurality of the refresh window sub-signal generating circuits are further configured to simultaneously receive the second refresh instruction and the refresh window reset signal, and generate the same sub-signal according to the second refresh instruction and the refresh window reset signal in one-to-one correspondence. A plurality of said refresh window sub-signals;

The refresh window sub-signal processing circuit is also used to receive a plurality of the refresh window sub-signals, perform logical operations on the refresh window sub-signals, and output the refresh window signal.
The refresh address generation circuit according to claim 5, wherein the refresh control circuit further includes:

A second pulse generation sub-circuit, coupled to the refresh window signal generation circuit, is used to receive a refresh window signal and an address command signal when the refresh control circuit starts to perform the first refresh operation or the second refresh operation. Generate a first pulse of the third clock signal, and output a second pulse of the third clock signal according to the first pulse of the address command signal, thereby outputting the third clock signal;

An internal refresh window signal generation circuit receives the third clock signal and is used to generate the internal refresh window signal according to the third clock signal; wherein the first pulse of the internal refresh window signal is generated when the third clock signal The first pulse of the signal is generated after and ends before the second pulse of the third clock signal is generated; the second pulse of the internal refresh window signal is generated after the second pulse of the third clock signal and ends before the second pulse of the third clock signal is generated. The refresh window signal ends before the pulse ends;

an address command signal generating circuit, configured to generate a first pulse and a second pulse of the address command signal according to the falling edge of the internal refresh window signal; wherein the first pulse of the address command signal is used to generate the internal Refresh the second pulse of the window signal and the second pulse of the third clock signal;

A refresh window reset signal generating circuit receives the internal refresh window signal and is configured to generate a pulse of the refresh window reset signal according to the falling edge of the second pulse of the internal refresh window signal.
The refresh address generation circuit according to claim 7, wherein the refresh control circuit further includes:

A signal selection circuit, coupled to the counting circuit, the first pulse generating sub-circuit and the second pulse generating sub-circuit, for receiving the counting signal, the first clock signal and the second clock signal and the third clock signal, when the refresh control circuit performs the first refresh operation, the first clock signal or the second clock signal is output according to the count signal, or, when the refresh control circuit When the circuit performs the second refresh operation, it outputs the third clock signal according to the counting signal.
The refresh address generation circuit according to claim 7, wherein the refresh control circuit further includes:

Address flag signal generation circuit, coupled to the address command signal generation circuit and the refresh window signal generation circuit, is used to receive the address command signal and the refresh window signal, according to the first rise of the address command signal The rising edge of the address mark signal is generated based on the falling edge of the refresh window signal.
The refresh address generation circuit according to claim 4, wherein the repeated command processing circuit includes:

a repeated instruction determination circuit, coupled to the counting circuit, for receiving the first refresh instruction and the counting signal, not outputting when a repeated instruction does not appear in the first refresh instruction, and, when the first refresh instruction does not occur, it does not output When a repeated instruction occurs in a refresh instruction, the repeated instruction is output;

An additional refresh flag signal generation circuit, coupled to the repetition instruction determination circuit and the refresh window signal generation circuit, is used to receive the repetition instruction and the refresh window signal, and generates a signal according to the repetition instruction and the refresh window signal. The additional refresh flag signal; wherein, the rising edge of the additional refresh flag signal is generated according to the effective pulse of the repeated instruction, and the falling edge of the additional refresh flag signal is generated according to the falling edge of the refresh window signal. And generated.
The refresh address generation circuit according to claim 8, wherein the address generator includes:

An address counter, coupled to the signal selection circuit, used to prestore the first address, change the first address to a third address according to the second clock signal, or change the first address according to the third clock signal. The first address and outputs the fourth address and the fifth address; the first address, the fourth address and the fifth address are three consecutive addresses in sequence;

an address processing circuit, coupled to the address counter, the refresh window sub-signal generation circuit and the repeated command processing circuit, for receiving the address flag signal when the refresh control circuit performs the first refresh operation, And obtain the first address, if the additional refresh flag signal is not received, then output the first address or the second address according to the address flag signal, if the additional refresh flag signal is received, then Output the additional address within the window time of the additional refresh flag signal;

The address processing circuit is also configured to sequentially obtain the fourth address and the fifth address when the refresh control circuit performs the second refresh operation, and sequentially output according to a plurality of the refresh window sub-signals. the fourth address and the fifth address.
The refresh address generation circuit according to claim 11, wherein the address processing circuit includes:

A control signal generation circuit, coupled to the refresh window sub-signal generation circuit and the address flag signal generation circuit, is used to receive a plurality of the refresh window sub-signals and the address flag signals, and generates a control signal according to a plurality of the refresh window sub-signals. signal and the address flag signal to generate an address control signal;

An address selection circuit, coupled to the address counter and the control signal generation circuit, configured to output the first refresh instruction before the rising edge of the address control signal arrives when the refresh control circuit receives the first refresh instruction. an address, or, after the rising edge of the address control signal arrives, the first address is accumulated to obtain and output the second address; the address selection circuit is also used to perform the refresh operation When the control circuit receives the second refresh instruction, it responds to the address control signal and sequentially outputs the fourth address and the fifth address;

An additional address generation circuit, coupled to the address selection circuit, for receiving and outputting when the refresh control circuit performs the first refresh operation and the additional address generation circuit does not receive the additional refresh flag signal. The first address and the second address; or, when the refresh control circuit performs the first refresh operation and the additional address generation circuit receives the additional refresh flag signal, receiving the first address and the second address, invert the target bits in the first address and the second address according to the additional refresh flag signal, and obtain and output the additional address, wherein the target bit is the Any address bit higher than the preset bit in the first address and the second address; or, when the refresh control circuit performs the second refresh operation, receive and output the fourth address or the third address. Five addresses.
The refresh address generation circuit according to claim 4, wherein the counting circuit includes:

A plurality of first inverters, the input terminals of the plurality of first inverters receive a plurality of the first refresh instructions in sequence;

a second inverter, an input terminal of which receives the count reset signal;

A plurality of first latches, the set terminals of the plurality of first latches are connected to the output terminals of a plurality of first inverters in sequence, and the reset terminals of the plurality of first latches are all connected Connected to the output end of the second inverter, a plurality of first latches correspondingly output a plurality of counting signals.
The refresh address generation circuit according to claim 4, wherein the count reset signal generation circuit includes:

A first AND gate, the input end of the first AND gate receives a plurality of the counting signals;

A third inverter, an input end of which receives the refresh window signal;

a second AND gate, the input end of the second AND gate is respectively connected to the output end of the first AND gate and the output end of the third inverter;

A first delayer, the input terminal of the first delayer is connected to the output terminal of the second AND gate;

a fourth inverter, the input terminal of the fourth inverter is connected to the output terminal of the first delay device;

A third AND gate, the input end of the third AND gate is respectively connected to the output end of the second AND gate and the output end of the fourth inverter, and the third AND gate outputs the count reset signal.
The refresh address generation circuit according to claim 4, wherein the first pulse generation sub-circuit includes:

a second delayer, an input terminal of which receives the count reset signal;

a third delayer, the input terminal of the third delayer is connected to the output terminal of the second delayer;

A first OR gate, the input terminal of the first OR gate is respectively connected to the output terminal of the second delayer and the output terminal of the third delayer, and the first OR gate outputs the first clock signal or the second clock signal.
The refresh address generation circuit according to claim 6, wherein the refresh window sub-signal includes: a first refresh window sub-signal or a second refresh window sub-signal; each of the refresh window sub-signal generation circuit includes:

A first NOR gate. When the refresh control circuit performs the first refresh operation, the first input end of the first NOR gate receives the corresponding first refresh instruction, or when the refresh control circuit When the circuit performs the second refresh operation, the second input terminal of the first NOR gate receives the second refresh instruction;

a second latch, the set end of the second latch is connected to the output end of the first NOR gate, and the reset end of the second latch receives the refresh window reset signal; when the When the refresh control circuit performs the first refresh operation, the second latch outputs the corresponding first refresh window sub-signal, or when the refresh control circuit performs the second refresh operation, the second latch outputs the corresponding first refresh window sub-signal. The second latch outputs the corresponding second refresh window sub-signal.
The refresh address generation circuit according to claim 16, wherein the refresh window sub-signal processing circuit includes:

a second OR gate. When the refresh control circuit performs the first refresh operation, the input terminal of the second OR gate receives multiple first refresh window sub-signals respectively, or when the refresh control circuit When performing the second refresh operation, the input terminals of the second OR gate receive the same plurality of second refresh window sub-signals respectively; the second OR gate outputs the refresh window signal.
The refresh address generation circuit according to claim 7, wherein the second pulse generation sub-circuit includes:

a fourth delayer, an input end of which receives the refresh window signal;

a fifth inverter, the input terminal of the fifth inverter is connected to the output terminal of the fourth delay device;

A fourth AND gate, the first input end of the fourth AND gate receives the refresh window signal, and the second input end of the fourth AND gate is connected to the output end of the fifth inverter;

A sixth inverter, the input terminal of the sixth inverter receives the address flag signal;

a fifth AND gate, the first input terminal of the fifth AND gate is connected to the output terminal of the sixth inverter, and the second input terminal of the fifth AND gate receives the address command signal;

a second NOR gate, the input end of the second NOR gate is respectively connected to the output end of the fourth AND gate and the output end of the fifth AND gate;

A seventh inverter, the input terminal of the seventh inverter is connected to the output terminal of the second NOR gate, and the seventh inverter outputs the third clock signal.
The refresh address generation circuit according to claim 7, wherein the address command signal generation circuit includes:

An eighth inverter, the input end of the eighth inverter receives the internal refresh window signal;

A fifth delayer, the input terminal of the fifth delayer is connected to the input terminal of the eighth inverter, and receives the internal refresh window signal;

A sixth AND gate. The input terminals of the sixth AND gate are respectively connected to the output terminal of the eighth inverter and the output terminal of the fifth delayer. The sixth AND gate outputs the address command signal. .
The refresh address generation circuit according to claim 19, wherein the internal refresh window signal generation circuit includes:

A third latch, the set terminal of the third latch receives the third clock signal, the reset terminal of the third latch is connected to the output terminal of the eighth inverter, and the third latch receives the third clock signal. Three latches output the internal refresh window signal.
The refresh address generation circuit according to claim 7, wherein the refresh window reset signal generation circuit includes:

A sixth delayer, the input end of the sixth delayer receives the address flag signal;

A seventh AND gate, the first input end of the seventh AND gate is connected to the output end of the sixth delayer, and the second input end of the seventh AND gate receives the internal refresh window signal;

A seventh delayer, the input terminal of the seventh delayer is connected to the output terminal of the seventh AND gate, and the seventh delayer outputs the refresh window reset signal.
The refresh address generation circuit according to claim 8, wherein the signal selection circuit includes:

A third NOR gate, the input terminals of the third NOR gate respectively receive a plurality of the counting signals;

A third OR gate, a first input terminal of the third OR gate receives the first clock signal or the second clock signal, and a second input terminal of the third OR gate receives the third clock signal;

An eighth AND gate, the first input end of the eighth AND gate is connected to the output end of the third NOR gate, and the second input end of the eighth AND gate is connected to the output end of the third OR gate, The eighth AND gate outputs the first clock signal, the second clock signal or the third clock signal.
The refresh address generation circuit according to claim 9, wherein the address flag signal generation circuit includes:

A ninth inverter, the input terminal of the ninth inverter receives the address command signal;

a fourth latch, the set terminal of the fourth latch is connected to the output terminal of the ninth inverter, the reset terminal of the fourth latch receives the refresh window signal, and the fourth latch The latch outputs the address flag signal.
The refresh address generation circuit according to claim 10, wherein the repeated instruction determination circuit includes:

A plurality of eighth delayers, the input terminals of the plurality of eighth delayers receive a plurality of the counting signals in sequence;

A plurality of ninth AND gates, the first input terminals of the plurality of ninth AND gates are sequentially connected to the output terminals of a plurality of eighth delays, and the second input terminals of the plurality of ninth AND gates are sequentially connected to a plurality of first refresh instructions;

A fourth NOR gate, the input terminals of the fourth NOR gate are respectively connected to the output terminals of a plurality of the ninth AND gates, and the fourth NOR gate outputs the repeated instruction.
The refresh address generation circuit according to claim 10, wherein the additional refresh flag signal generation circuit includes:

A fifth latch, the set end of the fifth latch receives the repeated instruction, the reset end of the fifth latch receives the refresh window signal, and the fifth latch outputs the Additional refresh flag signal.
The refresh address generation circuit according to claim 12, wherein the control signal generation circuit includes:

A tenth AND gate, the input terminals of the tenth AND gate respectively receive a plurality of the refresh window sub-signals;

A tenth inverter, the input end of the tenth inverter receives the address flag signal;

A fifth NOR gate, the first input terminal of the fifth NOR gate is connected to the output terminal of the tenth AND gate, and the second input terminal of the fifth NOR gate is connected to the output terminal of the tenth inverter. At the output end, the fifth NOR gate outputs the address control signal.
The refresh address generation circuit according to claim 12, wherein the address selection circuit includes: an adder and a first data selector;

The input end of the adder is connected to the address counter; the adder is used to obtain the first address when the refresh control circuit receives the first refresh instruction, and perform accumulation based on the first address. , obtain the second address;

The first input end of the first data selector is connected to the address counter, the second input end of the first data selector is connected to the adder, and the control end of the first data selector receives the address Control signal, the output terminal of the first data selector serves as the output terminal of the address selection circuit;

The first data selector is used to obtain the first address from the address counter and the second address from the adder when the refresh control circuit receives the first refresh instruction, In response to the address control signal, selecting the first address or the second address for output;

The first data selector is also used to obtain the fourth address or the fifth address from the address counter when the refresh control circuit receives the second refresh instruction, in response to the address control signal to output the fourth address or the fifth address.
The refresh address generation circuit according to claim 27, wherein the additional address generation circuit includes: an eleventh inverter, a second data selector and an address delay module;

The input end of the eleventh inverter is connected to the output end of the address selection circuit; the eleventh inverter is used to select the first refresh instruction from the refresh control circuit when the refresh control circuit receives the first refresh instruction. The address selection circuit obtains the target bit in the first address or the second address, inverts the target bit in the first address or the second address, and outputs it;

The first input terminal of the second data selector is connected to the output terminal of the address selection circuit, and the second input terminal of the second data selector is connected to the output terminal of the eleventh inverter; Two data selectors, used to obtain the additional refresh flag signal from the address selection circuit when the refresh control circuit receives the first refresh instruction and the control end of the second data selector does not receive the additional refresh flag signal. The target bit in the first address or the second address, and output the target bit in the first address or the second address; or, receive the first refresh instruction in the refresh control circuit , and when the control end of the second data selector receives the additional refresh flag signal, the inverted first address or the target in the second address is obtained from the eleventh inverter. bit, and output the inverted target bit in the first address or the second address;

The input end of the address delay module is connected to the output end of the address selection circuit; the address delay module is used to obtain the data from the address selection circuit when the refresh control circuit receives the first refresh instruction. Other bits in the first address or the second address are output after being delayed; the other bits are address bits other than the target bit.