JPH06111565A - Dynamic ram - Google Patents

Abstract

PURPOSE:To shorten the period of time for reading out the data of all memory cells so that the data of all the memory cells ar continuously read out by a serial mode. CONSTITUTION:At respective blocks 11A, 11B, 11C and 11D, before a block selection condition is made, the data of all the memory cells connected to word lines to be selected are held at sense amplifiers 14A0 to 14An, 14B0 to 14Bn, 14C0 to 14Cn and 14D0 to 14Dn.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dynamic RAM (dynamic RAM) having a serial mode as an operation mode.
random access memory. Hereinafter, referred to as DRAM).

[0002]

BACKGROUND ART FIG. 16 is a diagram showing an example main part of a conventional DRAM having a serial mode, 1 memory cell array _{section, 2 00, 2 01 ··· 2} mn memory cells, W
L ₀ , WL ₁ ... WL _m are word lines, BL ₀ , / BL _0.
... / BL _n is a bit line, 3 ₀ , 3 _1, ... 3 _n are sense amplifiers.

Reference numeral 4 denotes a row address buffer which outputs an internal row address signal obtained by waveform-shaping an externally supplied row address signal to form a complementary signal. Reference numeral 5 denotes an internal row address signal output from the row address buffer 4. Is a row decoder that decodes a word line and selects a word line.

Further, 6 is a column address buffer for outputting an internal column address signal obtained by waveform-shaping a column address signal supplied from the outside to form a complementary signal, and 7 is an internal column address signal output from the column address buffer 6. Is a column decoder that decodes the signal and outputs a column selection signal.

[0005] 8 column (sense amplifier 3 ₀ according to the column selection signal output from the column decoder 7,
Column selection gates 3 ₁ ... 3 _n ) are selected, and 9 is an output buffer for outputting the data read via the column selection gate 8 to the outside.

FIG. 17 is a waveform diagram showing the operation in the serial mode provided in this DRAM. When this serial mode is executed, first, a row address strobe signal (hereinafter referred to as / RAS signal). For example, a row address R ₀ for selecting the word line WL ₀ is fetched in synchronization with the falling edge of.

As a result, the word line WL ₀ is activated,
The word lines WL ₀ to the connected memory cell 2 _00,
2 ₀₁ · · 2 _0n information, respectively, the bit line pair BL _0,
/ BL ₀ , BL ₁ , / BL ₁ ... BL _n , / BL _n are read and sense amplifiers 3 ₀ , 3 ₁ ... 3 _n amplify and hold them.

[0008] Next, a column address strobe signal (hereinafter, referred to as / CAS signal) in synchronization with the falling of, for example, the column address C ₀ should be selected sense amplifier 3 ₀ is fetched, the column select gate 8 Through,
The sense amplifier 3 ₀ is selected, and the data D ₀ is output from the sense amplifier 3 ₀ to the outside via the output buffer 9.

Next, while keeping the / RAS signal at the L level,
When the CAS signal is alternately changed from H level → L level → H level, the column address is sequentially incremented by a predetermined internal circuit (not shown) in synchronization with the fall of the / CAS signal, and the sense amplifier 3 ₁ 3 ₂ ... 3 _n
There are sequentially selected, the sense amplifier 3 _1, 3 ₂ ... 3 data D ₁ stored in the _n, D _2, ... D _n is output sequentially.

[0010] In this way, the memory cells 2 connected to the word line _{WL 0 00, 2 01 ·· 2} 0n data D _0,
When D ₁ ... D _n are read, the serial mode ends and the / RAS signal and the / CAS signal are sequentially raised.

[0011]

Here INVENTION Problem to be Solved] In the conventional DRAM shown in FIG. 16, all the memory cells 2 _00, 2 ₀₁ -
_{.. When} reading data of 2 _mn using the serial mode, the serial mode must be executed for each of the word lines WL ₀ , WL ₁ ... WL _m Each time the serial mode ends for a line,
/ RAS signal must be raised.

[0012] That is, for example, after reading the word line WL ₀ the connected memory cell 2 _00, 2 ₀₁ ··· 2 _0n data to an external serial mode, are connected to the word line WL ₁ If to be read the memory cell 2 _10, 2 ₁₁ ··· 2 _1n of data in serial mode, after reading the data of the memory cell 2 _00, 2 ₀₁ ··· 2 _0n outside, again wordline the WL ₁ is activated, the memory cells connected to the word line _{WL 1 2 10, 2 11 ···} 2
The sense amplifier 3 ₀ the data of the _1n, 3 ₁ must be held in ··· 3 _n.

As described above, the conventional DRAM shown in FIG.
In the, all the memory cells in the chip 2 _00, 2 ₀₁ ...
Even when to be read to 2 _mn data can not be read consecutively the memory cells 2 _00, the 2 ₀₁ · · · 2 _mn data in serial mode, becomes longer read time There was a problem.

For example, even if the serial mode interval is set to 40 [nS], for example, until the data of the memory cell connected to the next selected word line is output, , 110 [nS] is required.

In view of the above point, the present invention can shorten the read time when reading the data of all the memory cells so that the data of all the memory cells can be continuously read in the serial mode. It is an object of the present invention to provide a DRAM that can be used.

[0016]

A DRAM according to the present invention
Is a memory cell array section in which memory cells are arranged,
After the falling edge of the / RAS signal, the row address, block address, and column address are externally fetched in synchronization with the first falling edge of the / CAS signal, and the row address, block address, and column address are used as the start address to set the row address. Is the upper bit, the block address is the middle bit, the column address is the lower bit,
In addition, the row address is repeatedly risen and fallen so that it is incremented when the block selected state is changed to the block non-selected state, and the row address is cycled from the leading address in synchronization with the fall of the CAS signal. Address generating means for sequentially outputting the addresses to be stored, and makes the sense amplifier hold the data of all the memory cells connected to the word line designated by the row address regardless of the block selected state and the block non-selected state. A plurality of blocks are provided so that data is output to the outside only when the block selection state is set.

[0017]

According to the present invention, in each block, an address fetched from the outside is used as a start address, and a row address is a loop address so that it is incremented when the block selected state is changed to the block non-selected state. Is configured to generate an address for sequentially outputting and to hold the data of all the memory cells connected to the word line specified by the row address in the sense amplifier regardless of the block selection state and the block non-selection state. Has been done.

In other words, in each block, the sense amplifier holds the data of all the memory cells connected to the word line to be selected before the block is selected. Therefore, the data of all memory cells in all blocks can be read in the serial mode.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first to third embodiments of the present invention will be described below with reference to FIGS.

First Embodiment FIG. 1 to FIG. 11 FIG. 1 and FIG. 2 are block diagrams showing the essential parts of the first embodiment of the present invention by dividing them, and 10 is a chip body, 11A, 11
B, 11C and 11D are blocks, 12A, 12B and 12
C and 12D are memory cell array portions, 13A, 13B and 1
3C and 13D are memory cells.

Further, WLA ₀ , WLA ₁ ... WLA _m ,
WLB ₀ , WLB ₁ ... WLB _m , WLC ₀ , WLC ₁
..... WLC _m , WLD ₀ , WLD ₁ ... WLD _m are word lines.

Further, BLA ₀ , / BLA ₀ ... / BLA
_n , BLB ₀ , / BLB ₀ ... / BLB _n , BLC ₀ , /
BLC ₀ ... / BLC _n , BLD ₀ , / BLD ₀ ... /
BLD _n is a bit line.

Further, 14A ₀ , 14A ₁ ... 14A _n ,
14B ₀ , 14B ₁ ... 14B _n , 14C ₀ , 14C _{1
·· 14C n, 14D 0, 14D} 1 ··· 14D n is a sense amplifier.

Further, 15A, 15B, 15C, 15D
Is a row address counter that is set with an externally supplied row address or an address next to the externally supplied row address as an initial value in the serial mode.

Here, the row address counter 15A,
When the block having a higher block address than the block to which it belongs is selected as the first block to be selected first, 15B and 15C are set with the next address of the row address supplied from the outside as the initial value. ,
In other cases, the row address supplied from the outside is set as the initial value.

Further, the row address counter 15D is
Whichever block is selected as the first block to be selected first, a row address supplied from the outside is set as an initial value.

That is, when the row address supplied from the outside is R _X and the block 11A is selected first, the row address counters 15A and 15B,
15C and 15D are set with the row address R _X as an initial value.

If the row address supplied from the outside is R _X and the block 11B is selected first, the row address counter 15A displays the row address R _{X + 1} (where R _X = final). In the case of the row address R _m , the head address R ₀ ) is set as the initial value, and the row address counters 15B, 15C, 15D are set with the row address R _X as the initial value.

If the row address supplied from the outside is R _X and the block 11C is first selected, the row address counters 15A and 15B are selected.
Is set to the row address R _{X + 1} (however, in the case of the final row address R _m , the start address R ₀ ) as the initial value, and the row address counters 15C and 15D set the row address R _X to the initial value. To be done.

When the row address supplied from the outside is R _X and the block 11D is selected first, the row address counters 15A, 15B,
15C is set with the row address R _{X + 1} (however, in the case of the final row address R _m , the start address R ₀ ) as the initial value, and the row address counter 15D is set with the row address R _X as the initial value. It

16A, 16B, 16C and 16D are row address counters 15A, 15B and 15D, respectively.
A row decoder that decodes the row address output from C and 15D.

Further, 17A, 17B, 17C and 17D are block address counters which are set using an externally supplied block address as an initial value, and 18A and 18D.
B, 18C, and 18D are block decoders that decode the block addresses output from the block address counters 17A, 17B, 17C, and 17D, respectively.

Further, 19A, 19B, 19C and 19D are column address counters 20A, 20B, which are set with a column address supplied from the outside as an initial value.
20C and 20D are column address counter 1 respectively
9A, 19B, 19C, 19D is a column decoder for decoding the column address output.

Further, 21A, 21B, 21C, 21D
Are column decoders 20A, 20B and 20 respectively.
A column selection gate for selecting a column based on a column selection signal output from C and 20D.

Further, 22 is a column selection gate 21A, 2
The output buffer is commonly provided to 1B, 21C, and 21D and outputs the data output from the column selection gate of the selected block to the outside.

Here, the column address counter 19A
Is set as the initial value of the column address fetched in synchronization with the first fall of the / CAS signal after the fall of the / RAS signal, and then counts up in synchronization with the fall of the / CAS signal, When counting up to the final column address C _n , the next / CAS
An overflow signal is output to the block address counter 17A in synchronization with the falling edge of the signal and at the same time, the column address C ₀ is reset to the head column address C ₀ , and then / C again.
It is configured to continue counting up in synchronization with the falling edge of the AS signal.

The initial value and count value of the column address counter 19A are output to the column decoder 20A at any time. Other column address counter 19
The same applies to B, 19C, and 19D.

In the first embodiment, the block address is synchronized with the falling edge of the / RAS signal,
Alternatively, it is captured in synchronization with the first falling edge of the / CAS signal after the falling edge of the / RAS signal.

Therefore, the block address counter 17
A is synchronized with the falling edge of the / RAS signal, or
After the fall of the RAS signal, the block address fetched in synchronization with the first fall of the / CAS signal is set as an initial value, and thereafter, in synchronization with the overflow signal output from the column address counter 19A,
After counting up and counting up to the final block address B ₃ , the column address counter 1
In synchronization with the next overflow signal output from 9A,
The head block address B ₀ is reset, and thereafter, counting up is continued again in synchronization with the overflow signal output from the column address counter 19A.

The block address counter 17A
The initial value and the count value of are output to the block decoder 18A at any time. Other block address counter 1
The same applies to 7B, 17C, and 17D.

In the case of the first embodiment, the block address B ₀ selects the block 11A, the block address B ₁ selects the block 11B, the block address B ₂ selects the block 11C, and the block address B ₃ selects.
The block 11D is selected by.

Therefore, the block decoder 18A receives the block address B from the block address counter 17A.
_{If a value} other than ₀ is output, the column selection gate 2
1A is configured to be inactive.

Further, the block decoder 18B receives the block address B ₁ from the block address counter 17B.
If other than is output, the column selection gate 21
It is configured to make B inactive.

Further, the block decoder 18C receives the block address B ₂ from the block address counter 17C.
If other than is output, the column selection gate 21
It is configured to make C inactive.

The block decoder 18D receives the block address B ₃ from the block address counter 17D.
If other than is output, the column selection gate 21
It is configured to make D inactive.

The block decoders 18A, 18B,
18C and 18D are blocks 11A, 11B and 1 respectively.
When 1C and 11D are changed from the selected state to the non-selected state,
The selection state end signal is sent to the row address counter 15A, 1
It is configured to output to 5B, 15C and 15D.

Further, the row address counter 15A is
A row address or row address + 1 which is fetched in synchronization with the falling edge of the / RAS signal is set as an initial value, and then, when the block 11A shifts from the selected state to the non-selected state, the selection output from the block decoder 18A When counting up in synchronization with the state end signal and counting up to the final row address R _m , the first row address R ₀ is synchronized with the next selected state end signal output from the block decoder 18A. After being reset, it is configured to count up again in synchronization with the selection state end signal output from the block decoder 18A.

The initial value and count value of the row address counter 15A are output to the row decoder 16A at any time. Other row address counters 15B, 15
The same applies to C and 15D.

That is, in the block 11A, the row address set as the initial value in the row address counter 15A is the upper bit, and the block address set in the block address counter 17A as the initial value is the middle bit and the column address. The column address set as the initial value in the counter 19A is used as the lower bit, and the row address is repeatedly risen and fallen so as to be incremented when the block 11A is changed from the selected state to the non-selected state. In synchronism with the falling edge of the / CAS signal, a cycle of addresses is sequentially generated from the initially set address. The same applies to the other blocks 11B, 11C, and 11D.

Therefore, for example, the row address = the address to be initialized, that is, the head address.
If R _X , block address = B ₁ , and column address = C _Y are taken in, blocks 11A, 11B, 11
In C and 11D, the addresses as shown in FIGS. 3, 4, 5, and 6 are generated in the order shown by the arrows.

FIG. 7 is a waveform diagram showing the operation of the serial mode in the first embodiment, and similarly to the above, the head address is row address = R _X , block address = B ₁ , column address. = are shown in the case where C _Y was captured. Note that RAC means a row address counter, and CAC means a column address counter.

Here, in the period T1 shown in FIG.
The block 11B is selected. In this case, in the block 11B, the data of the memory cell connected to the word line designated by the row address R _X is read to the bit line pair, and the sense amplifiers 14B ₀ and 14B are read. ₁ ... 1
4B _n is amplified and held, but only the data from the memory cell corresponding to the address specified by the column addresses C _{Y to} C _n is column address C _Y → C _{Y + 1} →.
·· → is read out to the outside in the order of C _n.

In this case, in the block 11A, the data of the memory cell connected to the word line designated by the row address R _{X + 1} is read out to the bit line pair, which is amplified by the sense amplifiers 14A _{0 to} 14A _n . And is retained,
Since the column selection gate 21A is inactivated, the data held in the sense amplifiers 14A _{0 to} 14A _n will not be read out to the outside.

In the blocks 11C and 11D, the data of the memory cell connected to the word line designated by the row address R _X is read out to the bit line pair, which is sense amplifiers 14C _{0 to} 14C _n and 14D _0. The column select gates 21C and 21D are amplified and held at ~ 14D _n.
Because it is a non-active, the sense amplifier 14C ₀ ~14
The data held in C _n and 14D _{0 to} 14D _n are not read out to the outside.

FIG. 8 is a diagram conceptually showing this operation. 23A, 23B, 23C and 23D are memory maps of blocks 11A, 11B, 11C and 11D, respectively, and a solid line X is a memory cell from which data is read out. The broken line Y indicates the address of the memory cell which is held in the sense amplifier but whose data is not read to the outside. The same applies to FIGS. 9 to 11.

In the period T2 shown in FIG. 7, the block 11C is selected. In this case, as shown in FIG. 9, the block 11C is connected to the word line designated by the row address R _X. The data of the memory cell being read is previously read to the bit line pair, and the sense amplifier 14C ₀
It is amplified by ～14C _n, because it is held, in succession block 11B, data column address held sense amplifier 14C ₀ ~14C _n is _{C 0 → C 1 → ··· →} C n
Are read out in the order of.

In this case, in blocks 11A and 11B,
As shown also in FIG. 9, the data of the memory cells connected to the word line designated by the row address R _{X + 1} is read to the bit line pair, and the sense amplifiers 14A _{0 to} 14A _n , 1
Is amplified by 4B _{0 ~14B n,} are held, column selection gates 21A, 21B so is deactivated, the sense amplifiers 14A ₀ to 14A _n, data held in 14B ₀ ~14B _n is outside It is never read.

Further, in the block 11D, as shown in FIG. 9, the data of the memory cell connected to the word line designated by the row address R _X is read out to the bit line pair, and the sense amplifiers 14D ₀ to 14D ₀ ~. is amplified by 14D _n, it is held, since the column select gate 21D is inactive, no data held in the sense amplifier 14D ₀ ~14D _n is read out to the outside.

In the period T3 shown in FIG. 7, the block 11D is selected. In this case, as shown in FIG. 10, the block 11D is connected to the word line designated by the row address R _X. Since the data of the memory cell being read is previously read to the bit line pair, amplified by the sense amplifiers 14D _{0 to} 14D _n , and held, the sense amplifiers 14D _{0 to} 14D 14 are successively connected to the block 11C.
The data held in D _n is the column address C ₀ → C ₁
→ ··· → is read out to the outside in the order of C _n.

In this case, blocks 11A, 11B and 11
In C, as shown in FIG. 10, the data of the memory cell connected to the word line designated by the row address R _{X + 1} is read out to the bit line pair, and the sense amplifiers 14A ₀ to 14A ₀ .
14A _n, 14B ₀ ~14B _n, is amplified by 14C ₀ ~14C _n, are held, column selection gates 21A, 21
Since B and 21C are inactive, the sense amplifier 14A
_The data held in _{0 to} 14A _n , 14B _{0 to} 14B _n , and 14C _{0 to} 14C _n are not read out to the outside.

In the period T4 shown in FIG. 7, the block 11A is selected. In this case, as shown in FIG. 11, the block 11A has the row address R _{X + 1.}
The data of the memory cell connected to the word line designated by is read out in advance to the bit line pair, and the sense amplifier 14
A ₀ is amplified by to 14A _n, because it is held, in succession block 11D, the sense amplifier 14A ₀ to 14A data held in the _n column address C ₀ → C ₁ → ··
· → is read out to the outside in the order of C _n.

In this case, blocks 11B, 11C and 11
In D, as shown in FIG. 11, the data of the memory cell connected to the word line designated by the row address R _{X + 1} is read to the bit line pair, and the sense amplifiers 14B ₀ to
14B _n, 14C ₀ ~14C _n, is amplified by 14D ₀ ~14D _n, are held, the column selection gate 21B, 21
Since C and 21D are inactive, the sense amplifier 1
4B _{0 to} 14B _n , 14C _{0 to} 14C _n , 14D _{0 to} 14D _n
The data held in is never read.

FIG. 12 is a diagram showing the overall reading method. The solid line with an arrow shows the state in which cells are selected according to the column address, and the broken line shows the next block. Shows a jump.

Here, in this first embodiment, each block 1
In 1A, 11B, 11C, and 11D, the address fetched from the outside is used as the start address, and the row address is sequentially output so that it is incremented when the block selected state is changed to the block unselected state. The address of the memory cells connected to the word line designated by the row address regardless of the block selected state or the block non-selected state, the sense amplifiers 14A _{0 to} 14A _n ,
14B _{0 to} 14B _n , 14C _{0 to} 14C _n , 14D _{0 to} 14
It is configured to be held at D _n .

In other words, each block 11A, 11B,
In 11C and 11D, the data of all the memory cells connected to the word line to be selected is previously sensed by the sense amplifiers 14A _{0 to} 14A _n , 1 before being set to the block selection state.
4B _{0 to} 14B _n , 14C _{0 to} 14C _n , 14D _{0 to} 14D _n
I am trying to hold it.

Therefore, according to the first embodiment, the data of all the memory cells of all the blocks 11A, 11B, 11C and 11D can be read in the serial mode, and the data of all the memory cells can be read continuously. The read time can be shortened.

In the first embodiment, when the blocks 11A, 11B, 11C and 11D are in the non-selected state, the column selection gates 21A, 21B, 21C and 21 are selected.
Although D is deactivated, the column decoders 20A, 20B, 20C, and 20D may be deactivated instead.

Second Embodiment FIG. 13 FIG. 13 is a block diagram showing the essential parts of a second embodiment of the present invention. In this second embodiment, the first embodiment shown in FIGS. Are blocks 11A, 11B, 11C, 11D
Column address counters 19A, 1 for each
9B, 19C and 19D have been deleted.

Then, one column address counter 19 which operates in the same manner as the column address counters 19A, 19B, 19C and 19D is provided in the blocks 11A,
11B, 11C, 11D to be shared, that is, column decoders 20A, 20B, 20C, 20D and block address counters 17A, 17B, 17
It is provided so as to be shared by C and 17D. Others are the same as those in the first embodiment.

Also in the second embodiment, as in the first embodiment, the data of all the memory cells of all blocks 11A, 11B, 11C and 11D can be read in the serial mode, and the data of all the memory cells can be read. It is possible to shorten the read time when reading continuously.

Third Embodiment FIG. 14, FIG. 15 FIG. 14 is a sectional view showing a third embodiment of the present invention. In the figure, 24A, 24B, 24C and 24D are chips, 25 is a molding resin, 26 is a bonding wire, and 27 is a lead.

In this third embodiment, one block is regarded as one chip, and blocks 11A, 11B and 1 in the first embodiment are used.
1C and 11D are connected to chips 24A, 24B and 2 respectively.
4C, 24D, and each chip 24A, 24D
An output buffer is provided in each of B, 24C and 24D.

That is, for example, the chip 24A has a circuit as shown in FIG. 28A is a memory cell array section (corresponding to the memory cell array section 12A in FIG. 1), 29A is a memory cell (memory cell 1 in FIG. 1).
3A), WLA ₀ , WLA ₁ ... WLA _m are word lines, and BLA ₀ , / BLA ₀ ... / BLA _n are bit lines.

30A _{0 to} 30A _n are sense amplifiers (corresponding to the sense amplifiers 14A _{0 to} 14A _n in FIG. 1).
Is.

In the serial mode, 31A is a row address counter (row address counter 15A in FIG. 1 which is set with an externally supplied row address or an address next to the externally supplied row address as an initial value. 32A is a row decoder for decoding the row address output from the row address counter 31A (corresponding to the row decoder 16A in FIG. 1).
Is.

Further, 33A is a block address counter (corresponding to the block address counter 17A in FIG. 1) which is set with a block address supplied from the outside as an initial value in the serial mode, and 34A is a block address counter 33A. It is a block decoder (corresponding to the block decoder 18A in FIG. 1) that decodes the block address output from the.

Further, 35A is a column address counter (corresponding to the column address counter 19A in FIG. 1) set with a column address supplied from the outside as an initial value in the serial mode, and 36A is a column address counter 35A. It is a column decoder (corresponding to the column decoder 20A in FIG. 1) that decodes the column address output from.

37A is a column selection gate (column selection gate 2 in FIG. 1) for selecting a column based on a column selection signal output from the column decoder 36A.
1A) and 38A are output buffers for outputting the data output from the column selection gate 37A to the outside.

The chip 24B has the same memory as that shown in FIG.
Memory cell array corresponding to the memory cell array section 12B
Section, memory cell corresponding to memory cell 13B, word line
WLB ₀, WLB₁... WLB_mCorresponding to the word line,
Bit line BLB₀, / BLB₀... / BLB_nCorresponds to
Bit line is provided.

The sense amplifiers corresponding to the sense amplifiers 14B _{0 to} 14B _n , the row address counter corresponding to the row address counter 15B, and the row decoder 16B.
Is provided for the row decoder.

Also, the block address counter 17B
Block address counter, block decoder 18B corresponding block decoder, column address counter 19A corresponding column address counter, column decoder 20B corresponding column decoder,
A column selection gate corresponding to the column selection gate 21B,
An output buffer is provided.

The chip 24C includes a memory cell array portion corresponding to the memory cell array portion 12C shown in FIG.
Memory cell corresponding to memory cell 13C, word line WL
Word lines corresponding to C ₀ , WLC ₁ ... WLC _m , and bit lines corresponding to bit lines BLC ₀ , / BLC ₀ ... / BLC _n are provided.

The sense amplifiers corresponding to the sense amplifiers 14C _{0 to} 14C _n , the row address counter corresponding to the row address counter 15C, and the row decoder 16C.
Is provided for the row decoder.

Also, the block address counter 17C
Corresponding to the block address counter, the block decoder corresponding to the block decoder 18C, the column address counter corresponding to the column address counter 19C, the column decoder corresponding to the column decoder 20C,
A column selection gate corresponding to the column selection gate 21C,
An output buffer is provided.

The chip 24D has a memory cell array portion corresponding to the memory cell array portion 12D shown in FIG.
Memory cell corresponding to memory cell 13D, word line WL
Word lines corresponding to D ₀ , WLD ₁ ... WLD _m , and bit lines corresponding to bit lines BLD ₀ , / BLD ₀ ... / BLD _n are provided.

The sense amplifiers corresponding to the sense amplifiers 14D _{0 to} 14D _n , the row address counter corresponding to the row address counter 15D, and the row decoder 16D.
Is provided for the row decoder.

Also, the block address counter 17D
Corresponding to the block address counter, the block decoder corresponding to the block decoder 18D, the column address counter corresponding to the column address counter 19D, the column decoder corresponding to the column decoder 20D,
A column selection gate corresponding to the column selection gate 21D,
An output buffer is provided.

Therefore, also in this third embodiment,
The data of all the memory cells of all the chips 24A, 24B, 24C, 24D can be read in the serial mode, and the read time when reading the data of all the memory cells continuously can be shortened.

[0089]

As described above, according to the present invention, in each block, the address fetched from the outside is used as the start address, and the row address is incremented when the block selected state is changed to the block non-selected state. As described above, an address that sequentially outputs a cycle of addresses is generated, and data of all memory cells connected to the word line specified by the row address is irrespective of the block selected state and the block non-selected state. The sense amplifier holds it, and in each block,
By making the sense amplifier hold the data of all memory cells connected to the word line that should be selected before entering the block selected state, the data of all memory cells of all blocks are read in serial mode. Therefore, it is possible to shorten the read time when reading the data of all the memory cells.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of a main part of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of a main part of the first embodiment of the present invention.

FIG. 3 is a diagram showing addresses generated in a block in a serial mode according to the first embodiment of the present invention.

FIG. 4 is a diagram showing addresses generated in a block in a serial mode according to the first embodiment of the present invention.

FIG. 5 is a diagram showing addresses generated in a block in the serial mode according to the first embodiment of the present invention.

FIG. 6 is a diagram showing addresses generated in a block in the serial mode according to the first embodiment of the present invention.

FIG. 7 is a waveform chart showing the operation in the serial mode in the first embodiment of the present invention.

FIG. 8 is a conceptual diagram showing an operation in a serial mode in the first embodiment of the present invention.

FIG. 9 is a conceptual diagram showing an operation in a serial mode in the first embodiment of the present invention.

FIG. 10 is a conceptual diagram showing an operation in a serial mode in the first embodiment of the present invention.

FIG. 11 is a conceptual diagram showing an operation in a serial mode in the first embodiment of the present invention.

FIG. 12 is a conceptual diagram showing the overall operation of the serial mode in the first embodiment of the present invention.

FIG. 13 is a circuit diagram showing a part of a main portion of a second embodiment of the present invention.

FIG. 14 is a sectional view showing a third embodiment of the present invention.

FIG. 15 is a block diagram showing a main part of a circuit included in a chip which constitutes a third embodiment of the present invention.

FIG. 16 is a circuit diagram showing a main part of an example of a conventional DRAM having a serial mode.

17 is a waveform chart showing an operation in a serial mode included in the DRAM shown in FIG.

[Explanation of symbols]

 11A to 11D block 12A to 12D memory cell array unit 13A to 13D memory cell

Claims (5)

[Claims] 1. A memory cell array portion in which memory cells are arranged, and a row address, a block address, and a row address are externally supplied in synchronization with a first fall of a column address strobe signal after a fall of a row address strobe signal. The column address is fetched, these row address, block address, and column address are used as the start address, the row address is used as the upper bit, the block address is used as the middle bit, and the column address is used as the lower bit. Address generation means for sequentially outputting a cycle of addresses starting from the start address in synchronization with the falling edge of a column address strobe signal that repeatedly rises and falls so as to be incremented when the block non-selected state is entered. When It has, regardless of the block selection state or the block non-selection state, the sense amplifier holds the data of all the memory cells connected to the word line specified by the row address, and only when the block selection state is set, A dynamic RAM comprising a plurality of blocks for outputting data to the outside. 2. The dynamic RAM according to claim 1, wherein each of the plurality of blocks is formed by one block as one chip. 3. The address generating means is a row address
After the falling edge of the strobe signal, the column address that is fetched in synchronization with the first falling edge of the column address strobe signal is set as the initial value, and then counts up in synchronization with the falling edge of the column address strobe signal. , When it counts up to the last column address, it outputs an overflow signal in synchronization with the falling edge of the next column address strobe signal, and is reset to the first column address.
Again, the column address that continues counting up in synchronization with the falling edge of the column address strobe signal
Initial value of the block column address fetched in synchronization with the counter and the falling edge of the row address strobe signal, or after the falling edge of the row address strobe signal and in synchronization with the first falling edge of the column address strobe signal. , And then counts up in synchronization with the overflow signal output from the column address counter, and when counting up to the final block address, the next overflow signal output from the column address counter is set. It is reset to the first block address in synchronization, and thereafter, again,
A block address counter that continues to count up in synchronization with the overflow signal output from the column address counter and a row address that is fetched in synchronization with the falling edge of the row address strobe signal are set as initial values. , Then, when the block shifts from the selected state to the non-selected state, it counts up in synchronization with the selected state end signal output from the block decoder which decodes the block address output from the block address counter, When counting up to the final row address, the row address is reset to the first row address in synchronization with the next selection state end signal output from the block decoder, and thereafter, the selection state end signal output from the block decoder again. Count up in sync with According to claim 1 or 2, wherein the dynamic RAM, characterized in that it is constituted by a row address counter that. 4. The dynamic RAM according to claim 1, wherein the plurality of blocks are configured to inactivate a column selection gate for selecting a column when the column is not selected. . 5. The plurality of blocks are configured to deactivate a column decoder which decodes a column address when not selected.
Alternatively, the dynamic RAM described in 3.