JP2640014B2 - Dot matrix display device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a dot matrix display device, and more particularly to a dot matrix display device using a dot matrix display panel such as a liquid crystal display.

(Prior art)

An example of this type of image display device is disclosed in Japanese Patent Application Laid-Open No. 58-54391 [G09G 3/36] published on March 31, 1983, and is shown in FIG.

A conventional dot matrix display device 1 shown in FIG. 3 includes a liquid crystal matrix display panel (hereinafter, simply referred to as a “display panel”) 2 to which a row drive signal is supplied from a row drive circuit 3 and an odd number is provided. A column drive signal is applied from the column drive circuit 4 and the even-numbered column drive circuit 5. Each of the odd-numbered column driving circuit 4 and the even-numbered column driving circuit 5 includes a shift register and a sample-and-hold circuit, as is well known. In response to the clock pulses CLKa and CLKb having a phase difference of 180 ° and the shift register start pulse SSP as shown in FIG.
RA1, SRA2, SRA3, ... and even-sequence sample pulses SRB1, SRB
, SRB3,... Are output, the image signal DATA is sampled and held in response to the sample pulse, and output to the display panel 2.

Note that Japanese Patent Application Laid-Open No. 58-20 published on December 2, 1983
No. 7071 [G06F9 / 00] discloses a similar liquid crystal display device.

[Problems to be solved by the invention]

In the prior art shown in FIG. 3 and the prior art disclosed in Japanese Patent Application Laid-Open No. 58-207071, when the number of dots in the column direction is relatively small, an odd column driving circuit 4 is used to generate a sample pulse.
The clocks CLKa and CLKb supplied to the even-numbered column driving circuit 5 have a low frequency, so that a sample pulse width sufficient to sample and hold data is obtained. However, for example, in the case of a high-definition display panel that can support high definition, etc., the number of dots increases,
Therefore, the clock frequency must be increased, and the width of the sample pulse becomes very small. As a result, the sample and hold of the image signal cannot be performed accurately. Therefore, the driving time of each column is shortened, and the quality of the displayed image is deteriorated.

Therefore, a main object of the present invention is to provide a dot matrix display device capable of securing a sufficient driving time even in a high definition display panel.

[Means for solving the problem]

In brief, the present invention includes an odd column driving unit that supplies a driving signal to each odd column of a dot matrix display panel, and an even column driving unit that supplies a driving signal to each even column of a dot matrix display panel. In the dot matrix display device, the odd-numbered column driving means includes a plurality of odd-numbered column driving circuits (16a, 16b, 16c), and the plurality of odd-numbered column driving circuits include first clock pulses (CLK1, CLK
2, CLK3), and the first sampling pulses (SRA1, SRA1) having different phases based on the first clock pulse.
2, SRA3,...), And samples the image signal to supply a drive signal to each odd-numbered column. The even-numbered driving means includes a plurality of even-numbered column driving circuits (18a, 18b, 18c) and a plurality of even-numbered column driving circuits. The circuit individually receives the second clock pulses (CLK4, CLK5, CLK6) out of phase with each other, and generates an image according to second sampling pulses (SRB1, SRB2, SRB3,...) Having different phases based on the second clock pulse. A dot matrix display device characterized in that a signal is sampled and a drive signal is supplied to each even column.

[Action]

The row driving circuit includes, for example, a shift register, and an output of the shift register is provided as a row driving signal of the display panel. The odd column driving circuit and the even column driving circuit are each divided into two or more, and each odd column driving circuit and each even column driving circuit include a shift register and a K sample hold circuit. Then, a sample pulse is generated based on clock pulses having different phases from each other in each of the odd-numbered column driving circuit and each of the even-numbered column driving circuits. Each odd column driving circuit alternately samples and holds the image signal, and outputs a driving signal to each odd column alternately. Similarly, each even column driving circuit alternately samples and holds an image signal and outputs each even column alternately.

〔The invention's effect〕

According to the present invention, since the odd-numbered column driving circuit and the even-numbered column driving circuit are each divided into a plurality, it is possible to secure a sufficient sample pulse width even in a high definition display panel having a very large number of dots in the column direction. Therefore, even a driving circuit having a low operation speed can sufficiently cope with the driving circuit, and a quality image can be displayed.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

〔Example〕

Referring to FIG. 1, a dot matrix display device 10 of this embodiment includes a display panel 12, which has a higher number of dots in the column direction than the conventional display panel shown in FIG. It is configured as a fine dot matrix display panel. Then, a row drive signal is supplied to the display panel 12 from a row drive circuit 14 including a shift register. Note that the row drive circuit 14 is supplied with a vertical start pulse VSP and a horizontal start pulse HSP.

In this embodiment, the first, second and third odd column driving circuits
16a, 16b and 16c are responsible for odd rows of the display panel 12,
The first, second, and third even-numbered column driving circuits 18a, 18b, and 18c are responsible for the even-numbered columns of the display panel 12. The image signal DATA, shift register pulse SSP and horizontal start pulse HSP are
1, the second and third odd column drive circuits 16a, 16b and 16c and the first, second and third even column drive circuits 18a, 18b and 1
Commonly given to 8c. Then, as shown in FIG. 2, clock pulses CLK1 and CLK2 having a phase difference of 120 ° from each other.
And CLK3 are the first odd column drive circuit 16a and the second odd column drive circuit 16a, respectively.
Clock pulses CLK4, CLK5, and CLK6 which are provided to the odd-numbered column driving circuit 16b and the third odd-numbered column driving circuit 16c and also have a phase difference of 120 ° from each other are respectively supplied to the first even-numbered column driving circuit 18a and the second even-numbered column Drive circuit 18b and third even column drive circuit 18c.

Each of the column drive circuits 16a to 16c and 18a to 18c respectively
Although not shown, a shift register and a sample-and-hold circuit are included, and the shift register includes clock pulses CLK1 to CLK6.
As shown in FIG. 2, the sample pulses SRA1, SRA2, SR
A3, ... and the sample pulses SRB1, SRB2, SRB3,
... is output. The sample and hold circuit outputs the video signal DATA
Is sampled in response to the sample pulse, and during one horizontal scanning period, as can be clearly understood from FIG. 4, each sampling pulse has a pulse width of six columns of the display panel and a phase between SRA and SRB. For one row, and each SRA or SRB differs by two rows.

First, second and third odd column drive circuits 16a, 16b and 16c
Supplies the drive signals of the odd columns alternately from the upper part of the display panel 12, and the first, second and third even-row drive circuits 18a, 18b and 18c supply the drive signals of the even columns from the lower part of the display panel 12. Supply alternately. For example, the first odd-numbered column driving circuit 16a
Supplies the first, seventh, thirteenth, nineteenth,..., Column drive signals, and the second odd-numbered column drive circuit 16b converts the third, ninth, fifteenth, twenty-first,. And the third odd column drive circuit 16c
The fifth, eleventh, seventeenth, twenty-third,..., Th column drive signals are supplied. Similarly, the first even-numbered column drive circuit 18a includes the second, eighth, fourteenth,
. 0,..., And the second even-numbered column driving circuit 18
b supplies the fourth, tenth, sixteenth, twenty-second, ... th column drive signals,
Then, the third even-numbered column driving circuit 18c outputs the sixth, twelfth, eighteenth, twenty-fourth,.
And supply a third column drive signal.

As described above, the first, second and third odd column drive circuits 16
Clock pulses CLK1, CLK2 given to a, 16b and 16c
And CLK3 are pulses that are 120 ° out of phase,
The clock pulses CLK4, CLK5 and CLK6 applied to the first and third even-numbered column drive circuits 18a, 18b and 18c are pulses whose phases are shifted by 120 °. And the clock pulse
CLK1 and CLK4 are out of phase by 60 °. Therefore, even if the number of dots in the horizontal direction becomes very large,
A sample pulse width corresponding to one dot can be sufficiently widened, and therefore a sufficient drive signal can be given to a high-definition display panel even when a movable circuit having a low operation speed is used.

Although the liquid crystal dot matrix display panel is used as the display panel in the above embodiment, it goes without saying that the present invention can be applied to any dot matrix display panel such as a plasma display panel.

Further, the number of the odd-numbered column drive circuits and the number of the even-numbered column drive circuits are not limited to three in the embodiment, and may be two or more.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIG. 2 is a timing chart showing the operation of the embodiment shown in FIG. FIG. 3 is a block diagram showing the prior art. FIG. 4 is a timing chart showing the operation of the prior art in FIG. In the figure, 10 is a dot matrix display device, 12 is a display panel, 14 is a row drive circuit, 16a, 16b and 16c are first and second
And a third odd column drive circuit, 18a, 18b and 18c denote first, second and third even column drive circuits.

Claims (1)

(57) [Claims] 1. A dot matrix display panel in which display dots are arranged in a matrix, row drive means for supplying a drive signal to each row of the dot matrix display panel, and a drive signal to each odd-numbered column of the dot matrix display panel. A dot matrix display device comprising: an odd column driving unit that supplies a driving signal to each even column of the dot matrix display panel; and an odd column driving unit that includes a plurality of odd column driving circuits (16a, 16b,
16c), wherein the plurality of odd-numbered column driving circuits individually receive first clock pulses (CLK1, CLK2, CLK3) out of phase with each other, and perform first sampling of different phases based on the first clock pulses. Pulse (SRA1, SRA2, SRA3,
..), And supplies a drive signal to each of the odd-numbered columns. The even-numbered column driving means includes a plurality of even-numbered column driving circuits (18a, 18b,
18c), wherein the plurality of even-numbered column driving circuits individually receive second clock pulses (CLK4, CLK5, CLK6) out of phase with each other, and perform second sampling of different phases based on the second clock pulses. Pulse (SRB1, SRB2, SRB3,
..), And supplies the drive signal to each of the even columns, respectively. The odd column drive unit and the even column drive unit sample the image signals in the order of the columns. A drive signal is supplied to each of the odd columns and each of the even columns.