JP2637849B2 - Microcomputer - Google Patents

Microcomputer

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Publication number
JP2637849B2
JP2637849B2 JP2414414A JP41441490A JP2637849B2 JP 2637849 B2 JP2637849 B2 JP 2637849B2 JP 2414414 A JP2414414 A JP 2414414A JP 41441490 A JP41441490 A JP 41441490A JP 2637849 B2 JP2637849 B2 JP 2637849B2
Authority
JP
Japan
Prior art keywords
circuit
processing circuit
signal processing
power supply
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2414414A
Other languages
Japanese (ja)
Other versions
JPH04225419A (en
Inventor
義則 井上
和也 真子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Original Assignee
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
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Filing date
Publication date
Application filed by NIPPON DENKI AISHII MAIKON SHISUTEMU KK filed Critical NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Priority to JP2414414A priority Critical patent/JP2637849B2/en
Publication of JPH04225419A publication Critical patent/JPH04225419A/en
Application granted granted Critical
Publication of JP2637849B2 publication Critical patent/JP2637849B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、アナログ信号を扱う回
路を内蔵したマイクロコンピュータに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a circuit for handling analog signals.

【0002】[0002]

【従来の技術】従来のマイクロコンピュータでアナログ
信号を扱う回路 (以下、アナログ回路という。)たとえ
ばADコンバータやDAコンバータを内蔵したもので
は、演算回路やタイミング発生回路等の中央処理回路
(以下、CPUという。)とアナログ回路とは同一の電
源で動作していた。CPUではディジタル信号で処理を
行うために信号は高電位(以下、VDD電位という。)と
低電位(以下、GND電位という。)の2値をもち、2
値の電位差は電源電圧となる。いま、CPUの一例とし
てインバータ(図3参照)の動作と電源電圧とについて
説明する。入力10にVDD電位が印加されると、PchMO
Sトランジスタ12 (以下、PchMOSという。) はオフ
し、NchMOSトランジスタ13( 以下、NchMOSとい
う。)はオンして出力にGND電位が出力される。この
ときにNchMOS13がオンするためには、ゲートの電圧
とソースの電圧の差すなわち入力の電位(VDD電位)と
GND電位の差がNchMOS13のしきい値電圧より高く
なくてはならない。一方、入力にGND電位が印加され
るとNchMOS13はオフし、PchMOS12はオンして出
力にVDD電位が出力される。こときにPchMOS12がオ
ンするためには、ゲートの電圧とソースの電圧の差すな
わち入力の電位(GND電位)とVDD電位の差がPchM
OS12のしきい値電圧より高くなくてはならない。この
ように、CPUが動作するためにはVDD電位とGND電
位の差すなわち電源電圧がNchMOS13およびPchMO
S12のしきい値電圧より高ければよいことがわかる。
2. Description of the Related Art A circuit for handling analog signals in a conventional microcomputer (hereinafter referred to as an analog circuit), for example, one having a built-in AD converter or DA converter, has a central processing circuit (hereinafter referred to as a CPU) such as an arithmetic circuit and a timing generation circuit. ) And the analog circuit were operated by the same power supply. In the CPU, since processing is performed using digital signals, a signal has two values, a high potential (hereinafter, referred to as a VDD potential) and a low potential (hereinafter, referred to as a GND potential).
The potential difference between the values is the power supply voltage. Now, the operation of the inverter (see FIG. 3) and the power supply voltage will be described as an example of the CPU. When V DD potential is applied to input 10, PchMO
The S transistor 12 (hereinafter, referred to as PchMOS) is turned off, the NchMOS transistor 13 (hereinafter, referred to as NchMOS) is turned on, and the GND potential is output to the output. At this time, in order for the NchMOS 13 to be turned on, the difference between the gate voltage and the source voltage, that is, the difference between the input potential ( VDD potential) and the GND potential must be higher than the threshold voltage of the NchMOS13. On the other hand, when the GND potential is applied to the input, the Nch MOS 13 is turned off, the Pch MOS 12 is turned on, and the VDD potential is output at the output. At this time, in order for the Pch MOS 12 to be turned on, the difference between the gate voltage and the source voltage, that is, the difference between the input potential (GND potential) and the VDD potential is PchM.
It must be higher than the threshold voltage of OS12. As described above, in order for the CPU to operate, the difference between the VDD potential and the GND potential, that is, the power supply voltage is equal to the NchMOS 13 and the PchMO.
It is understood that it is only necessary to be higher than the threshold voltage of S12.

【0003】次に、アナログ回路の動作電源電圧につい
て説明する。アナログ回路の一例として図4に示すAD
コンバータについて説明する。比較信号16がロウレベル
のときにスイッチ素子19はオンしてB点とC点を短絡す
ると、NchMOS21とPchMOS20とはともにオン状態
となり、B点およびC点の電圧はNchMOS21とPchM
OS20のオン状態の抵抗値で分圧された電圧になる。そ
の後に比較信号16がハイレベルになり、スイッチ素子19
がオフし、次に制御信号14がロウからハイに変わるとス
イッチ素子17がオンからオフにスイッチ素子18はオフか
らオンになり、A点はVinの電圧がVvefに切りかわ
り、B点の電位はコンデンサ22を通じてA点の電位変化
にともない変動する。この変動をNchMOS21とPchM
OS20とで増幅してC点へ出力する。このような動作の
ためには、比較信号16がロウのときにB点の電位がNch
MOS21とPchMOS20のオン抵抗の分圧電圧でなけれ
ばならない。そのためにはNchMOS21とPchMOS20
とがともにオンすることが必要であり、VDDとB点の電
位差がPchMOS20のしきい値電圧以上であり、B点と
GNDの電位差がNchMOS21のしきい値電圧以上でな
ければならない。すなわち、電源電圧はPchMOS20と
NchMOS21のしきい値電圧の和以上の電圧が必要であ
る。
Next, the operation power supply voltage of the analog circuit will be described. As an example of the analog circuit, the AD shown in FIG.
The converter will be described. When the comparison signal 16 is at the low level, the switch element 19 is turned on to short-circuit the points B and C, so that both the NchMOS 21 and the PchMOS 20 are turned on, and the voltages at the points B and C are NchMOS21 and PchM
The voltage is divided by the on-state resistance of OS20. After that, the comparison signal 16 becomes high level, and the switching element 19
There was off, the switch element 18 off and then the control signal 14 is changed from low to high the switch element 17 from ON is turned on from off, instead off voltage of the point A V in is the V VEF, B point Changes with the potential change of the point A through the capacitor 22. This fluctuation is compared with NchMOS21 and PchM
The signal is amplified by the OS 20 and output to the point C. For such an operation, when the comparison signal 16 is low, the potential at the point B is Nch
It must be a divided voltage of the on-resistance of the MOS21 and the PchMOS20. For that purpose, NchMOS21 and PchMOS20
Must be turned on, the potential difference between VDD and the point B must be equal to or greater than the threshold voltage of the PchMOS 20, and the potential difference between the point B and GND must be equal to or greater than the threshold voltage of the NchMOS 21. That is, the power supply voltage needs to be equal to or higher than the sum of the threshold voltages of the PchMOS 20 and the NchMOS 21.

【0004】以上述べたようにアナログ回路の方がCP
Uより動作のために高い電源電圧が必要である。
As described above, the analog circuit has a lower CP.
A higher power supply voltage is required for operation than U.

【0005】[0005]

【発明が解決しようとする課題】従来のマイクロコンピ
ュータでは、アナログ回路の最小動作電圧がCPUより
も高いので、電池を電源として用いて電池寿命に近づい
たときなど電源電圧が下がった場合に、アナログ回路が
異常動作をし、CPUは正常動作をする場合が生じる。
アナログ回路が異常動作をすると、アナログ回路の出力
信号は誤ったデータとなり、平均値の演算などではこの
誤ったデータの出力信号の複数のデータを記憶して演算
処理するので、演算結果に誤りを含む欠点があった。
In a conventional microcomputer, the minimum operating voltage of an analog circuit is higher than that of a CPU. The circuit operates abnormally, and the CPU operates normally.
If the analog circuit operates abnormally, the output signal of the analog circuit becomes erroneous data. In the calculation of the average value, etc., a plurality of data of the output signal of the erroneous data are stored and processed. There were drawbacks including:

【0006】本発明は、このような欠点を除去するもの
で、アナログ信号処理回路での誤データによる装置の誤
処理を回避することができるマイクロコンピュータを提
供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a microcomputer which eliminates such disadvantages and which can avoid erroneous processing of a device due to erroneous data in an analog signal processing circuit.

【0007】[0007]

【課題を解決するための手段】本発明は、電圧変動が起
こる装置電源に接続され、この装置電源に接続された装
置内のディジタル信号処理回路の最小動作電圧より高い
最小動作電圧をもち、このディジタル信号処理回路に自
回路の処理結果を与えるアナログ信号処理回路を備えた
マイクロコンピュータにおいて、上記装置電源の電圧を
検出しこの検出電圧が上記アナログ信号処理回路の最小
動作電圧を下回るときに上記ディジタル信号処理回路に
よる上記アナログ信号処理回路の処理結果の取り込みを
禁止する禁止信号を与える電源電圧検出回路を備え、上
記ディジタル信号処理回路は、この禁止信号に応じて上
記アナログ信号処理回路の処理結果の取り込みを一時中
止する手段を含むことを特徴とする。
SUMMARY OF THE INVENTION The present invention has a minimum operating voltage that is higher than the minimum operating voltage of a digital signal processing circuit in a device connected to the device power supply where voltage fluctuations occur. In a microcomputer provided with an analog signal processing circuit for giving a processing result of its own circuit to a digital signal processing circuit, a voltage of the device power supply is detected, and when the detected voltage falls below a minimum operating voltage of the analog signal processing circuit, the digital signal is output. A power supply voltage detection circuit for providing a prohibition signal for prohibiting the signal processing circuit from capturing the processing result of the analog signal processing circuit; the digital signal processing circuit responding to the prohibition signal to generate a processing result of the analog signal processing circuit; It is characterized in that it includes means for temporarily stopping the capturing.

【0008】ここで、上記ディジタル信号処理回路が含
むアナログ信号処理回路の処理結果の平均演算手段は、
取り込みを一時中止したアナログ信号処理回路の処理結
果を除いた平均演算を実行する手段であることが望まし
い。
The means for calculating the average of the processing results of the analog signal processing circuit included in the digital signal processing circuit includes:
It is desirable that the means be a means for executing an averaging operation excluding the processing result of the analog signal processing circuit whose capture has been suspended.

【0009】[0009]

【作用】装置電源電圧がディジタル信号処理回路の最小
動作電圧とアナログ信号処理回路の最小動作電圧との中
間値に低下すると、ディジタル信号処理回路は正常に処
理を行うが、アナログ信号処理回路の処理結果に誤りが
起こる。この誤処理結果の取り込みをディジタル信号処
理回路は一時中止して誤処理を回避する。
When the device power supply voltage drops to an intermediate value between the minimum operating voltage of the digital signal processing circuit and the minimum operating voltage of the analog signal processing circuit, the digital signal processing circuit performs normal processing. The result is incorrect. The digital signal processing circuit temporarily stops taking in the erroneous processing result to avoid the erroneous processing.

【0010】[0010]

【実施例】以下、本発明の一実施例について図面を参照
して説明する。
An embodiment of the present invention will be described below with reference to the drawings.

【0011】図1はこの実施例のブロック図である。電
源電圧検出回路1は、VDDとGNDの電位差がある電圧
以下を検出すると電源電圧検出信号5をハイレベルから
ロウレベルにする。なお、検出する電圧はアナログ回路
2の最小動作電源電圧に設定されている。アナログ回路
2は、アナログ入力信号4をディジタル信号6に変換す
るアナログ・ディジタル変換回路である。中央処理回路
3は、ディジタル信号6を取り込み、プログラムによっ
てセットの制御を行う。
FIG. 1 is a block diagram of this embodiment. The power supply voltage detection circuit 1 changes the power supply voltage detection signal 5 from a high level to a low level when detecting a voltage lower than a certain voltage difference between VDD and GND. The voltage to be detected is set to the minimum operating power supply voltage of the analog circuit 2. The analog circuit 2 is an analog / digital conversion circuit that converts the analog input signal 4 into a digital signal 6. The central processing circuit 3 takes in the digital signal 6 and controls the set by a program.

【0012】すなわち、この実施例は、第1図に示すよ
うに、電圧変動が起こる装置電源に接続され、この装置
電源に接続された装置内のディジタル信号処理回路であ
るCPU3の最小動作電圧より高い最小動作電圧をも
ち、このディジタル信号処理回路に自回路の処理結果を
与えるアナログ回路2を備え、さらに、本発明の特徴と
する手段として、上記装置電源の電圧を検出しこの検出
電圧がアナログ回路2の最小動作電圧を下回るときに上
記CPU3によるアナログ回路2の処理結果の取り込み
を禁止する禁止信号を与える電源電圧検出回路1を備
え、上記ディジタル信号処理回路は、この禁止信号に応
じてアナログ回路2の処理結果の取り込みを一時中止す
る手段を含む。また、上記ディジタル信号処理回路が含
むアナログ回路2の処理結果の平均演算手段は、取り込
みを一時中止したアナログ回路2の処理結果を除いた平
均演算を実行する手段である。
That is, as shown in FIG. 1, this embodiment is connected to an apparatus power supply in which voltage fluctuations occur, and is controlled by a minimum operating voltage of a CPU 3 which is a digital signal processing circuit in the apparatus connected to the apparatus power supply. An analog circuit 2 having a high minimum operating voltage and providing the digital signal processing circuit with the processing result of its own circuit is provided. Further, as a feature of the present invention, the voltage of the device power supply is detected and A power supply voltage detection circuit for providing a prohibition signal for prohibiting the CPU from capturing the processing result of the analog circuit when the voltage falls below the minimum operating voltage of the circuit; Means for temporarily stopping the acquisition of the processing result of the circuit 2 is included. The averaging means for the processing results of the analog circuit 2 included in the digital signal processing circuit is means for executing the averaging operation excluding the processing results of the analog circuit 2 whose capture has been suspended.

【0013】次に、この実施例の動作について説明す
る。高電位端子と低電位端子との間に電源電圧検出回路
1に設定された検出電圧以上の電圧が印加されている場
合に、電源電圧検出信号5にハイレベルが出力される。
電源電圧検出信号5にハイレベルが出力されると、CP
U3はディジタル信号6のデータを用いて処理を行う。
電源として電池を用いて寿命が近づいたときなど電源電
圧が低下し、高電位端子と低電位端子の電位差が電源電
圧検出回路1の検出電圧以下すなわちアナログ回路2の
最小動作電源電圧以下になると、アナログ回路2はディ
ジタル信号6に誤りをもったデータを出力し、電源電圧
検出回路1は電源電圧検出信号5にロウレベルを出力す
る。
Next, the operation of this embodiment will be described. When a voltage equal to or higher than the detection voltage set in the power supply voltage detection circuit 1 is applied between the high potential terminal and the low potential terminal, a high level is output as the power supply voltage detection signal 5.
When a high level is output to the power supply voltage detection signal 5, CP
U3 performs processing using the data of the digital signal 6.
When the power supply voltage decreases, for example, when the life of the battery is shortened using a battery as a power supply, and the potential difference between the high potential terminal and the low potential terminal becomes equal to or less than the detection voltage of the power supply voltage detection circuit 1, that is, equal to or less than the minimum operation power supply voltage of the analog circuit 2, The analog circuit 2 outputs data having an error in the digital signal 6, and the power supply voltage detection circuit 1 outputs a low level to the power supply voltage detection signal 5.

【0014】一例として、温度センサの出力をアナログ
回路2であるADコンバータでディジタル信号に変え、
CPU3は一定時間ごとにADコンバータ出力である温
度データを取込んで記憶し、記憶したデータをもとに平
均値を演算し、温度制御を行う装置を構成している。C
PU3はアナログ回路2のデータを用いて演算処理を行
うだけでなく、キーから設定用データを読込んだり、表
示回路へデータを送る処理など行っている。この構成
で、電源電圧検出信号5がロウレベルになると、CPU
3は電源電圧検出信号5を割込み信号として受け付けて
割込み処理を行う。割込み処理では、キーを読込む処理
や表示回路へデータを送る処理などを行い、ADコンバ
ータの出力データは取り込まないで処理を行う。このこ
とにより誤りをもったデータを記憶しないので、電源電
圧を上げてアナログ回路の出力データが正常になると、
記憶された誤りをもたないデータを使って平均値の演算
など直ちに行うことができる。
As an example, the output of the temperature sensor is converted into a digital signal by an AD converter which is an analog circuit 2,
The CPU 3 constitutes a device which takes in and stores temperature data which is the output of the AD converter at regular time intervals, calculates an average value based on the stored data, and performs temperature control. C
The PU 3 not only performs arithmetic processing using the data of the analog circuit 2, but also performs processing such as reading setting data from a key and transmitting data to the display circuit. With this configuration, when the power supply voltage detection signal 5 goes low, the CPU
3 receives the power supply voltage detection signal 5 as an interrupt signal and performs an interrupt process. In the interrupt process, a process of reading a key, a process of sending data to a display circuit, and the like are performed, and a process is performed without capturing output data of an AD converter. As a result, data with errors is not stored, so when the power supply voltage is increased and the output data of the analog circuit becomes normal,
The calculation of the average value can be performed immediately using the stored data having no error.

【0015】[0015]

【発明の効果】本発明は、以上説明したように、アナロ
グ回路の最小動作電源電圧を電源電圧検出回路によって
検出し、中央処理回路は電源電圧検出回路で検出した信
号によって誤りを持ったアナログ回路の出力信号をとり
込まず処理を行うので、誤ったデータを記憶せずに処理
を行え、平均値の演算などのために記憶したデータを用
いた処理に誤差が入らない効果がある。
As described above, according to the present invention, the minimum operating power supply voltage of the analog circuit is detected by the power supply voltage detection circuit, and the central processing circuit detects the analog circuit having an error by the signal detected by the power supply voltage detection circuit. Since the processing is performed without taking in the output signal, the processing can be performed without storing erroneous data, and there is an effect that an error does not occur in the processing using the data stored for calculating the average value.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明実施例の構成を示すブロック図。FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

【図2】 従来例の構成を示すブロック図。FIG. 2 is a block diagram showing a configuration of a conventional example.

【図3】 中央処理回路の内部例としてのインバータの
回路図。
FIG. 3 is a circuit diagram of an inverter as an internal example of a central processing circuit.

【図4】 アナログ回路の内部例としてのADコンバー
タの回路図。
FIG. 4 is a circuit diagram of an AD converter as an internal example of an analog circuit.

【符号の説明】[Explanation of symbols]

1 電源電圧検出回路 2 アナログ回路 3 中央処理回路 4 アナログ入力信号 5 電源電圧検出信号 6 ディジタル信号 10 入力 11 出力 12、20 PchMOSトランジスタ 13、21 NchMOSトランジスタ 14 制御信号 15 基準電圧信号 16 比較信号 17、18、19 スイッチ素子 1 Power supply voltage detection circuit 2 Analog circuit 3 Central processing circuit 4 Analog input signal 5 Power supply voltage detection signal 6 Digital signal 10 Input 11 Output 12, 20 PchMOS transistor 13, 21 NchMOS transistor 14 Control signal 15 Reference voltage signal 16 Comparison signal 17, 18, 19 switch element

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 電圧変動が起こる装置電源に接続され、
この装置電源に接続された装置内のディジタル信号処理
回路の最小動作電圧より高い最小動作電圧をもち、この
ディジタル信号処理回路に自回路の処理結果を与えるア
ナログ信号処理回路を備えたマイクロコンピュータにお
いて、上記装置電源の電圧を検出しこの検出電圧が上記
アナログ信号処理回路の最小動作電圧を下回るときに上
記ディジタル信号処理回路による上記アナログ信号処理
回路の処理結果の取り込みを禁止する禁止信号を与える
電源電圧検出回路を備え、上記ディジタル信号処理回路
は、この禁止信号に応じて上記アナログ信号処理回路の
処理結果の取り込みを一時中止する手段を含むことを特
徴とするマイクロコンピュータ。
1. An apparatus connected to a device power supply in which voltage fluctuation occurs.
A microcomputer provided with an analog signal processing circuit having a minimum operating voltage higher than a minimum operating voltage of a digital signal processing circuit in a device connected to the device power supply, and providing the digital signal processing circuit with a processing result of its own circuit. A power supply voltage for detecting a voltage of the power supply of the device and supplying a prohibition signal for prohibiting the digital signal processing circuit from taking in the processing result of the analog signal processing circuit when the detected voltage is lower than the minimum operating voltage of the analog signal processing circuit. A microcomputer comprising a detection circuit, wherein the digital signal processing circuit includes means for temporarily stopping taking in of the processing result of the analog signal processing circuit in response to the prohibition signal.
【請求項2】 上記ディジタル信号処理回路が含むアナ
ログ信号処理回路の処理結果の平均演算手段は、取り込
みを一時中止したアナログ信号処理回路の処理結果を除
いた平均演算を実行する手段である請求項1記載のマイ
クロコンピュータ。
2. The averaging means of the processing result of the analog signal processing circuit included in the digital signal processing circuit is means for executing an averaging operation excluding the processing result of the analog signal processing circuit whose capture has been suspended. The microcomputer according to 1.
JP2414414A 1990-12-26 1990-12-26 Microcomputer Expired - Fee Related JP2637849B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2414414A JP2637849B2 (en) 1990-12-26 1990-12-26 Microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2414414A JP2637849B2 (en) 1990-12-26 1990-12-26 Microcomputer

Publications (2)

Publication Number Publication Date
JPH04225419A JPH04225419A (en) 1992-08-14
JP2637849B2 true JP2637849B2 (en) 1997-08-06

Family

ID=18522898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2414414A Expired - Fee Related JP2637849B2 (en) 1990-12-26 1990-12-26 Microcomputer

Country Status (1)

Country Link
JP (1) JP2637849B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6018576A (en) * 1983-07-11 1985-01-30 Toyota Central Res & Dev Lab Inc Removal of peroxide from degraded oil

Also Published As

Publication number Publication date
JPH04225419A (en) 1992-08-14

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