JP2635065B2 - Semiconductor memory circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective when applied to a semiconductor memory circuit and a semiconductor memory circuit having a built-in content addressable memory circuit. The present invention relates to a technology that is effective when used in a microcomputer incorporated as a memory.

[Prior Art] FIG. 2 shows a schematic configuration of a semiconductor memory circuit studied by the present inventors.

The semiconductor memory circuit shown in FIG. 1 is formed as a cache memory in a semiconductor integrated circuit device IC in which a microcomputer is integrated, for example, and includes a pattern memory search circuit 1, a decoder 2, and a data storage memory circuit 3. , A sense and input / output driver circuit 4, a selection signal detection circuit 5, and the like.

The pattern storage and retrieval circuit 1 is a so-called CAM matrix that stores a plurality (n) of address patterns AP1 to APn and stores the same address pattern as an input address pattern Ai externally applied via a bus 6. A search is made from the plurality of address patterns AP1 to APn. Then, if there is a searched address pattern, it outputs selection signals 11-1 to 11-n corresponding to the storage position of the searched address pattern.

The decoder 2 is operated when the address patterns AP1 to APn are written in the pattern storage and retrieval circuit 1. The decoder 2 decodes the write address Aw supplied from the outside via the bus 7 to obtain the pattern. Selection signals 10-1 to 10 for designating a storage position of the storage and retrieval circuit 1
-N is generated. In this case, the address pattern written in the pattern storage and retrieval circuit 1 is externally provided via the bus 6.

The data storage storage circuit 3 stores data Dio input / output to / from the outside, and stores the storage position of the external input / output data Dio by selecting signals 11-1 to 11-n from the pattern storage / retrieval circuit 1. Specified by Writing or reading of data to or from the designated storage location is performed via sense and input / output driver 4 and bus 8.

The selection signal detection circuit 5 is constituted by an OR gate for detecting the total logical sum of the selection signals 11-1 to 11-n from the pattern storage / retrieval circuit 1. It is detected whether or not a selection signal effective for designating a storage location has been output. This detection signal Co is output to the outside via the line 9.

As described above, an associative storage circuit addressed by a specific address pattern is configured.

As a document describing a technique related to this type of storage circuit, there is, for example, JP-A-60-136097.

[Problems to be Solved by the Invention] However, it has been clarified by the present inventors that the above-described technology has the following problems.

That is, in the above-described semiconductor memory circuit, even if there is a partial defect in the pattern memory search circuit 1, for example, it cannot be directly verified from the outside. In order to determine whether or not there is a defective portion in the pattern storage and retrieval circuit 1, a test address pattern is externally input to the pattern storage and detection circuit 1 while the externally output selection signal detection circuit 5 The only indirect test is to monitor the state of the detection signal Co. However, in such an indirect inspection, the inspection is troublesome and time-consuming, and the cause or location of the failure cannot be accurately specified. That is, there is a problem that the above-described semiconductor memory circuit is inferior in test suitability.

An object of the present invention is to provide a technique for improving the test suitability of a semiconductor memory circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, there is provided a diagnostic circuit for outputting the state of the pattern storage / retrieval circuit that supplies the storage position selection signal to the data storage storage circuit to the outside.

[Operation] According to the above-described means, the state of the pattern storage and retrieval circuit can be directly verified from the outside, so that a defective portion can be easily and accurately specified. This achieves the purpose of improving the suitability for inspection.

EXAMPLES Hereinafter, preferred examples of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows a schematic configuration of a semiconductor memory circuit according to one embodiment of the present inventor.

The semiconductor memory circuit shown in FIG. 1 is formed as a cache memory in a semiconductor integrated circuit device IC in which a microcomputer is integrally formed, for example.
As its basic components, it has a pattern storage and retrieval circuit 1, a decoder 2, a data storage storage circuit 3, a sense and input / output driver circuit 4, a selection signal detection circuit 5, and the like.

The pattern storage and retrieval circuit 1 is a so-called CAM matrix that stores a plurality (n) of address patterns AP1 to APn and stores the same address pattern as an input address pattern Ai externally applied via a bus 6. A search is made from the plurality of address patterns AP1 to APn. Then, if there is a searched address pattern, it outputs selection signals 11-1 to 11-n corresponding to the storage position of the searched address pattern.

The decoder 2 is operated when the address patterns AP1 to APn are written in the pattern storage and retrieval circuit 1. The decoder 2 decodes the write address Aw supplied from the outside via the bus 7 to obtain the pattern. Selection signals 10-1 to 10 for designating a storage position of the storage and retrieval circuit 1
-N is generated. In this case, the address pattern written in the pattern storage and retrieval circuit 1 is externally provided via the bus 6.

The data storage storage circuit 3 stores data Dio input / output to / from the outside, and the storage position of the external input / output data Dio is determined by the selection signals 11-1 to 11-n from the pattern storage / retrieval circuit 1. It is specified. Writing or reading of data to the designated storage location is performed via sense and input / output driver 4 and bus 8.

The selection signal detection circuit 5 is constituted by an OR gate for detecting the total logical sum of the selection signals 11-1 to 11-n from the pattern storage / retrieval circuit 1. It is detected whether or not a selection signal effective for designating a storage location is output. This detection signal Co is output to the outside via the line 9.

As described above, the basic part of the associative storage circuit addressed by the specific address pattern is configured.

Further, in the semiconductor memory circuit shown in FIG. 1, in addition to the above-described configuration, a selection signal output from the pattern storage and retrieval circuit 1 is used as a diagnostic circuit for outputting the state in the pattern storage and retrieval circuit 1 to the outside. A selection signal output circuit 20 for outputting the contents of 11-1 to 11-n to the outside is provided. The selection signal output circuit 20 outputs the selection signals 11-1 to 11-1.
It is constituted by a selector 12 for switching and outputting the individual states of 11-n one by one in time order. The selector 12 is also called a multiplexer, and a switching position is selected by a write address Aw. As a result, it is possible to directly and externally verify whether the state in the pattern storage and retrieval circuit 1 is normal for each storage location, and to easily and accurately specify a defective portion.

 FIG. 3 shows another embodiment of the present invention.

The difference from the above embodiment will be described. In the storage circuit shown in the figure, the storage contents (AP1 to APn) of the pattern storage and retrieval circuit 1 are used as a diagnostic circuit for outputting the state of the pattern storage and retrieval circuit 1 to the outside. A storage / readout circuit 21 for outputting to the outside is provided. The storage / readout circuit 21 is constituted by a sense circuit 14 and an output driver 15, reads out an address pattern stored in a storage location selected by a write address Aw, and reads the readout address pattern via a bus 16. Output to the outside. As a result, the state inside the pattern storage and retrieval circuit 1 can be directly verified bit by bit from the outside, and the defective portion can be specified in more detail.

FIG. 4 partially shows a specific configuration example in the pattern storage and retrieval circuit 1.

As shown in FIG. 1, a large number of storage cells M are arranged in a matrix in the pattern storage and retrieval circuit 1, and a word line WL1 for selecting the storage cells M in units of rows is provided. Data lines (bit lines) DL1 and DL2 for writing or reading storage data to or from the storage cells M on the selected row are arranged in columns. Further, a match detection line WL2 is provided in each row. The match detection line WL2 is configured such that the address pattern stored in the memory cell column on the row selected by the word line WL1 has an external input address pattern Ai (Aom, Ao (m-
1) and 一致) are detected by wired logic to see if they match. Word line WL1 is connected to a selection signal 10-1,... Obtained by decoding a write address.
The data lines DL1 and DL2 are connected to the address pattern Ai (Aom, Aom
o (m-1), ‥‥) are connected to the bus 6 to which the signal is input and the sense circuit 14 for reading the storage data of the storage cells M on the selected row in bit units. The detection output of the match detection line WL2 is based on the selection signals 11-n,
It becomes ‥‥.

As described above, a pattern storage and retrieval circuit capable of reading out the stored address pattern in bit units and outputting the same to the outside is configured.

 FIG. 5 shows still another embodiment of the present invention.

The storage circuit shown in the figure is the storage read circuit shown in FIG.
The selector 21 is added to the selector 21. The selector 16
The address pattern stored in the storage location selected by the write address Aw is selected and read one bit at a time in order and output from the line 17 to the outside. Thus, the number of external terminals for diagnosis can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, some or all of the storage circuits in the pattern storage and retrieval circuit 1 may be constituted by read-only storage circuits.

[Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the state of the pattern storage and retrieval circuit can be directly verified from the outside, the effect that the defective portion can be easily and accurately specified can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor memory circuit according to one embodiment of the present invention, FIG. 2 is a schematic configuration diagram of a semiconductor memory circuit studied prior to the present invention, and FIG. 3 is a second embodiment of the present invention. FIG. 4 is a circuit diagram partially showing a configuration example in a pattern storage and retrieval circuit, and FIG. 5 is a schematic configuration diagram of a semiconductor storage circuit according to a third embodiment of the present invention. It is. 1 ... Pattern storage and retrieval circuit (CAM matrix), 2
... A decoder, 3... A data storage memory circuit, 4... Sense and input / output driver circuits, 10-1 to 10 -n...
1 to 11-n: a storage position selection signal for the data storage circuit 3, 12: selector, AP1 to APn: storage address pattern, Ai: input address pattern, 20: selection signal output as a diagnostic circuit Circuit, 21: Memory readout circuit as a diagnostic circuit, IC: Semiconductor integrated circuit device.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-272668 (JP, A) JP-A-62-38949 (JP, A) JP-A-60-103599 (JP, A) JP-A-60-1985 171735 (JP, A)

Claims (1)

(57) [Claims] A plurality of address patterns are stored by a plurality of write addresses, and an address pattern identical to an externally applied input address pattern is searched from the plurality of address patterns, and a storage position of the searched address pattern is stored. A pattern storage / retrieval circuit for outputting a selection signal corresponding to the data, and a storage circuit for storing data in which external input / output data is stored and a storage position of the external input / output data is designated by a selection signal from the pattern storage / retrieval circuit And a selection signal output line provided for each address pattern storage position of the pattern storage and search circuit, and a selection signal output line, and the storage position of the data storage storage circuit is designated by the pattern storage and search circuit. Selection signal detection circuit that detects whether a valid selection signal has been output When the semiconductor memory circuit, characterized in that it includes a selector for outputting a signal of one selected and the selected output line of the selection signal output line to the outside by the write address.