JP2633905B2 - Electron beam exposure system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] An electron beam exposure apparatus that combines a plurality of pattern data groups into the same deflection area (field) and performs exposure without re-conversion processing of the pattern data groups and exposure processing time For the purpose of efficiently exposing without causing a large increase in the number of patterns, the pattern data read from the storage device is temporarily stored in the data memory under the control of the central processing unit, and the pattern read from the data memory is temporarily stored. The data is converted into coordinate data necessary for exposure for each of a plurality of fields by a pattern generation unit, and the deflection means is controlled, and the stage is controlled to move by the central processing unit, and the electron beam from the electron gun is deflected and scanned. In an electron beam exposure apparatus for writing a pattern on a sample surface on a stage, the same deflection area is exposed from the data memory. Reading means for reading in parallel each pattern data group of a plurality of patterns for each pattern, and comparing the position coordinates of the plurality of pattern data groups read in parallel for each pattern, respectively, to the most upstream in the moving direction of the stage. And a comparison means for sequentially outputting the pattern data in the pattern generation section and outputting the pattern data to the pattern generation section.

[Industrial applications]

The present invention relates to an electron beam exposure apparatus, and more particularly to an electron beam exposure apparatus that combines and exposes a plurality of pattern data groups in the same tendency area (field).

In recent years, IC chips have become more sophisticated and complex, and IC chips based on a mixture of different processes, such as a composite chip combining a memory and a logic circuit or a composite chip combining a MOS transistor and a bipolar transistor, have appeared. Reached. When this composite chip is formed by electron beam exposure, pattern data of all chips is newly processed, or data conversion processing is performed only on a portion to be changed or corrected in design.

On the other hand, the integration of ICs (integrated circuits) has become more advanced, the number of pattern data has become enormous, and the data conversion processing time for converting design data into pattern data for an electron beam exposure apparatus has become longer even with a large computer. . For this reason, when the highly integrated composite chip is formed by electron beam exposure, it is important that the pattern data group can be drawn by the exposure apparatus in a short time without performing reconversion processing.

[Conventional technology]

FIG. 8 shows a configuration diagram of an example of a conventional electron beam exposure apparatus. In the figure, 1 is a central processing unit (hereinafter referred to as a CPU).
Controls the entire electron beam exposure apparatus. Reference numeral 2 denotes a magnetic disk which stores various data including pattern data, which is graphic information to be exposed, and control information. Reference numeral 3 denotes an interface circuit, which interfaces the CPU 1 with each component described later. Reference numeral 4 denotes a data memory, which is a large-capacity memory circuit for temporarily storing pattern data read from the magnetic disk 2.

Reference numeral 5 denotes a pattern generation unit which sequentially reads pattern data from the data memory 4 and decomposes the pattern data into a plurality of rectangular beams to create coordinate data and rectangular beam sizes required for exposure. The 6-pattern correction unit corrects the amount of electron beam deflection according to the state of the pattern drawing area of the sample. Further
7a is an amplifier (AMP), and 7b, 7c and 7d are each a D / A for converting a digital signal from the pattern correction unit 6 into an analog signal.
Amplifier (AMP) that amplifies the analog signal of the converter (DAC)
It is a circuit provided with.

Reference numeral 8 denotes a column in which an electron beam emitted from an electron gun 9 is transmitted or cut off by a blanking electrode 10, shaped into a rectangular beam of an arbitrary shot size by a beam size changing electrode 11, and further sub-deflected. After a small deflection area of, for example, about 100 μm square is deflected by the electrode 12, a deflection area (field) of, for example, about 2 to 5 mm square is deflected by the main deflection coil 13, and the pattern is irradiated onto the surface of the sample 15. To draw.

In the electron beam exposure apparatus having such a configuration, the ninth
When exposing the composite chip 17 as shown in the figure, the memory 1
8. Each of the logic circuits 19 and 20 is subjected to pattern drawing. At this time, a plurality of pattern data groups need to be combined and exposed in the same deflection area (field). That is, as shown in FIG. 10, when a pattern C is superimposed on a pattern A based on the first pattern data group and a pattern B based on the second pattern data group in the same deflection area, the following two methods are conventionally used. He was taking the street method.

In the first method, as schematically shown in FIG. 11 (a), both pattern data groups of patterns A and B are combined to form a pattern data group of pattern C, and data conversion is performed for electron beam exposure. And a pattern data group C ′ is obtained and exposed.

In the second method, as schematically shown in FIG. 11 (b), only the pattern data group of the pattern A to be changed or corrected out of the pattern data groups of the patterns A and B is converted into an electron beam. This is a method of obtaining a pattern data group A 'for exposure, exposing the pattern data group of the pattern B, and then superposing the pattern data group A' for exposure.

That is, when the composite chip 17 shown in FIG. 9 is created by electron beam exposure, the layout of the memory 18 is automatically determined if the memory capacity or the cycle time is determined, and the pattern data once subjected to the data conversion processing is registered as a library. If so, the memory 18 can be created only by exposing the pattern data to the designated position. Therefore, the pattern data group of the logic circuits 19 and 20 (FIG. 11 (b)
In this case, if only the data conversion processing is performed,
A new composite chip 17 can be created without processing the entire pattern data group of the chip as shown in FIG.

Further, even when only a part of the pattern data group is designed to be changed or modified, the data can be combined at the time of exposure by executing a data conversion process of only the pattern data group to be designed or modified. .

[Problems to be solved by the invention]

According to the first conventional method, however, the number of pattern data is very large due to the high integration of the IC, and even if a slight design change or correction is made, the two pattern data groups are synthesized each time and the data conversion is performed. However, there is a drawback that extremely long data conversion processing time is required even when a large computer is used.

On the other hand, the second conventional method has an advantage that the data conversion processing time is shorter than the first conventional method, but has the following disadvantages. That is, when exposing a pattern having a large chip size and exceeding a region (field: usually 2 to 5 mm square) that can be deflected by the main deflection coil 13, the exposure time is long.

For example, as shown in the pattern (chip) A, B are respectively Figure 12, it is intended to each be drawn into six deflection region of _{A 1 ~A 6, B 1 ~B} 6 ( field), and the deflection Region A ₁ and
B ₁ is being located draw over their pattern in the same position, similarly deflection area A ₂ and B _2, A ₃ and B _3, ..., is in the A ₆ and B ₆ are each the same position, their pattern Assuming that they are drawn in an overlapping manner, the exposure order is A ₁ , A ₂ ,…, A ₆ , B ₁ , B ₂ ,…, B ₆ and A
₁ , B ₁ , A ₂ , B ₂ ,..., A ₆ , B ₆ .

In the former exposure order, the stage 14 is not moved until the drawing of one deflection area (field) is completed, and the stage 14 is moved for the next one field drawing after the completion of one field drawing. In both cases, the main deflection coil 13 scans and deflects the electron beam twice at the same position even in the case of the continuous movement method in which the stage 14 is constantly moved in a constant direction, so that the exposure time is long and the exposure time is long. Would.

On the other hand, in the case of the latter exposure order, 2 in the same deflection area.
Since the two patterns are sequentially exposed, it is less susceptible to the effects of electron beam drift and fluctuations in deflection current than the former exposure order, and is possible with the step-and-repeat method. If the beam is not sorted in the direction orthogonal to the continuous movement direction of the stage 14, pattern data cannot be exposed.
Because if the pattern data is random,
This is because the stage 14 is continuously moved and may exceed the deflection range (about 2 to 5 mm square) of the main deflection coil 13. In the continuous stage moving method, the above-described sorting is conventionally performed only on the pattern data of each deflection area, so that the deflection may have to be performed to the full deflection range of the main deflection coil 13. It was difficult.

The present invention has been made in view of the above points, and provides an electron beam exposure apparatus that can efficiently perform exposure without re-converting a pattern data group and without significantly increasing an exposure processing time. The purpose is to provide.

[Means for solving the problem]

FIG. 1 shows a principle configuration diagram of the present invention. 8, the same components as those in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 1, reference numeral 21 denotes a reading means, and 22 denotes a comparing means.

The reading means 21 reads, from the data memory 4, each pattern data group of a plurality of patterns exposed to the same deflection area in parallel for each pattern.

The comparing means 22 sequentially outputs the pattern data from the plurality of pattern data groups in the moving direction of the stage 14 at the most upstream side in the moving direction.

It should be noted that the deflection means in the present invention does not have to include the main deflection coil 13 and the sub deflection electrode 12, and may be a single.

[Action]

There are two patterns, A and B, that are overlaid on the same deflection area (field). When the position coordinates of each pattern data group are arranged in order from the upstream side with respect to the moving direction of the stage 14, the pattern of pattern A As for the data
_{a 11, a 12, a 13} , ..., with respect to the pattern data of the pattern _{B b 11, b 12, b} 13, ... are assumed to be the order of.

Comparison means 22 a ₁₁ and b ₁₁ and compares the Trip a ₁₁ is on the upstream side of the b ₁₁ relative to the stage moving direction (which a ₁₁
<And shall be represented as b _11), and outputs the pattern data of a _11, then compares the a ₁₂ and b _11, a _12> when b ₁₁ is
b Output the pattern data of ₁₁ . Therefore, the comparison means 22
, Pattern data sorted in units of small deflection areas, not in units of fields.

When the pattern data group includes a main deflection data group that determines the position of the small deflection area in the electron beam exposure deflection area and a sub deflection data group that describes the pattern data in the small deflection area, the main deflection data Are compared, and as a result, one main deflection data and a sub-deflection data group related thereto are output respectively.

Therefore, according to the present invention, a plurality of pattern data groups can be combined without newly synthesizing a plurality of pattern data groups to generate one pattern data group, and without superimposing and exposing each pattern sequentially. The exposure can be performed in a predetermined order.

[Example]

FIG. 2 is a block diagram showing a first embodiment of the main part of the present invention. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 2, the data memory 4 has storage areas 4a and 4b in which pattern data groups of the patterns A and B are stored. These pattern data groups are divided into address control circuits 24a, 24b for each pattern.
, And are individually read from an arbitrary address. This reading is performed under the control of the CPU 1.

The pattern data separately read from the storage areas 4a and 4b are temporarily stored in the read registers 25a and 25b, and then supplied to the comparison circuit 26, respectively. The comparing circuit 26 compares the pattern data of the two patterns (compares the data in the sorting direction of the pattern data and, if the data is sorted in the Y direction, the Y coordinate data), and the data having the smaller value (the drawing order is the Y coordinate). The smaller data is output when the value is smaller than the larger value, and the larger data is output when the value is smaller.

FIG. 3 is a block diagram showing a second embodiment of the main part of the present invention. In the figure, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof will be omitted. The present embodiment is an example in which three patterns A, B and C are exposed to the same deflection area. The data memory 4 is provided with pattern data group storage areas 4a, 4b and 4c for patterns A, B and C. Have been.

Compared with the first embodiment, an address control circuit 24c for reading a pattern data group of pattern C and a read register 25c for temporarily storing the same are added, and a comparison circuit 27 compares the position coordinates of three pattern data groups. .

The above is an example in which the pattern data is not divided into the main deflection data and the sub deflection data. The third and fourth embodiments described below show examples in which the pattern data is divided. Here, the main deflection data is pattern data of an electron beam exposure deflection area (field), and is pattern data of an area (for example, 2 to 5 mm square) that can be deflected by the main deflection coil 13.

On the other hand, the sub-deflection data is a pattern data of an area (for example, 100 μm square) which is a small deflection area divided by the hardware limitation of the apparatus and which can be deflected by the sub-deflection electrode 12. As shown in FIG. 4, the main deflection area A ₁ (which corresponds to A ₁ shown in FIG. 12) is 2 to 5 mm square, and the sub deflection areas are A ₁₁ , A ₁₂ ,. Corresponds to one rectangular region indicated by a broken line. Assuming that the direction of continuous movement of the stage is indicated by 29 in FIG. 4, the direction of deflection of the electron beam by the main deflection coil 13 is a direction orthogonal to the direction of movement.

The main deflection data indicates a deflection region (field) the relative position coordinates of the center O ₁ to the center O ₂ of the sub-deflection region of (M _X, M _Y) as shown in Figure 5. The sub-deflection data is, for example, data consisting of the position coordinates (S _X , S _Y ) of the lower left end and the width W and height H of the pattern 31 at the time of drawing the pattern indicated by 31 in FIG.

FIG. 6 shows a block diagram of a third embodiment of the present invention. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. The data memory 4 is provided with a pattern data storage area 32a for pattern A and a pattern data storage area 32b for pattern B, and both storage areas 32a and 32b store the main deflection data group and the sub deflection data group. Become. Also,
Each pattern data is provided with an identification flag at the head position. For example, when the value is “0”, it indicates main deflection data, and when the value is “1”, it indicates sub deflection data.

The read registers 25a and 25b store the main deflection data and the sub deflection data from the storage areas 32a and 32b, respectively, and these are determined by the data determination circuits 33a and 33b based on the value of the identification flag. It is determined whether the data is deflection data, and the main deflection data is output to the data registers 34a and 34b, and the sub deflection data is output to the data registers 35a and 35b.

The comparison circuit 36 compares the position coordinates of the main deflection data from the data registers 34a and 34b, outputs the smaller main deflection data, and stores the sub deflection data group related to the main deflection data. The data register that is performing the read operation is output as readable. Therefore, for example, when the main deflection data is output from the data register 34a, the sub deflection data group is output from the data register 35a, and the reading of the data register 35b is prohibited.

Next, a fourth embodiment of the main part of the present invention will be described with reference to FIG. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. This embodiment is a data memory for main deflection data.
It is characterized in that the data memory 4 is composed of the data memories 38a and 38b and the data memories 39a and 39b for sub deflection data. Therefore, in the present embodiment, the main deflection data and the sub deflection data are separated in advance, so that the data determination circuits 33a and 33 shown in FIG.
b is unnecessary. Although this embodiment also requires an address control circuit, it is not shown for convenience.

In FIG. 7, the main deflection data separately read from the data memories 38a and 38b are stored in the read registers 40a and 40b, respectively. At the same time as reading the main deflection data, the sub deflection data group connected by the pointer is read from the data memories 39a and 39b and read registers 41a and 4b.
It is supplied to 1b and stored.

Each time one main deflection data is read from the read registers 40a and 40b, the comparison circuit 42 compares the magnitudes of the main deflection data and outputs the smaller main deflection data. The deflection data group is output from the read register 41a or 41b, and reading of the other read register 41b or 41b is prohibited.

As described above, according to each embodiment, while continuously moving the stage 14, each pattern data group of two or three patterns is selectively output in order from the upstream one in the stage continuous movement direction and exposed. Therefore, pattern drawing can be performed in a short time, and time for new data conversion processing can be eliminated.

It should be noted that the present invention can be similarly applied to a pattern data group of three or more complicated patterns, and is also applicable to a step-and-repeat method.

〔The invention's effect〕

As described above, according to the present invention, when a plurality of pattern data groups are combined and exposed at the same position, the data conversion processing time for obtaining one new combined pattern data group from all the pattern data groups is reduced. Since exposure can be made unnecessary and the pattern data groups of multiple patterns are mixed and exposed based on the comparison result of the smallest area unit, even when the stage is continuously moved, the exposure processing time is greatly reduced. It has such features as being possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIGS. 2 and 3 are block diagrams of first and second embodiments of a main part of the present invention, respectively, and FIG. FIG. 5 is a diagram showing the relationship between the main deflection data and the sub deflection data. FIGS. 6 and 7 are block diagrams of the third and fourth embodiments of the main part of the present invention, respectively. FIG. 8 is a diagram showing an example of a conventional electron beam exposure apparatus, FIG. 9 is a diagram showing an example of a composite chip, FIG. 10 is an explanatory diagram of pattern data synthesis, and FIG. 11 is an example of a synthesized pattern drawing method. FIG. 12 is an explanatory diagram of a configuration of a pattern group to be drawn in an overlapping manner. In the figure, 1 is a central processing unit (CPU), 4 is a data memory, 9 is an electron gun, 12 is a sub deflection electrode, 13 is a main deflection coil, 14 is a stage, 15 is a sample, 21 is a reading means, 22 Denotes a comparison means, 26, 27, 36, and 42 denote comparison circuits, 33a and 33b denote data determination circuits, 38a and 38b denote main deflection data data memories, and 39a and 39b denote sub deflection data data memories.

Claims (2)

(57) [Claims] 1. Pattern data read from a storage device (2) under the control of a central processing unit (1) is temporarily stored in a data memory (4), and the pattern data read from the data memory (4) is stored. Is converted into coordinate data necessary for exposure for each of a plurality of fields by a pattern generation unit (5) to control the deflecting means (12, 13) and to control the movement of the stage (14) by the central processing unit (1). An electron beam exposure apparatus for deflecting and scanning an electron beam from an electron beam (9) to draw a pattern on the surface of a sample (15) on the stage (14). A reading means (21) for reading each pattern data group of a plurality of patterns to be exposed in parallel for each pattern and a position coordinate of the plurality of pattern data groups read in parallel for each pattern are compared. Comparison means for outputting the pattern data in the moving direction on the most upstream side of the stage (14) to output in order to the pattern generator (5) (2
2) An electron beam exposure apparatus comprising: 2. A pattern data group comprising: a main deflection data group for determining a position of a small deflection area in an electron beam exposure deflection area; and a sub deflection data group for describing pattern data in the small deflection area. The comparing means (22) compares the position coordinates of the plurality of main deflection data groups read for each pattern, and compares the main deflection data of one small deflection area with the sub deflection data group of the one small deflection area. 2. An electron beam exposure apparatus according to claim 1, wherein