JP2632761B2 - Semiconductor element mounting substrate and method of manufacturing semiconductor element mounting substrate - Google Patents

Semiconductor element mounting substrate and method of manufacturing semiconductor element mounting substrate

Info

Publication number
JP2632761B2
JP2632761B2 JP22346892A JP22346892A JP2632761B2 JP 2632761 B2 JP2632761 B2 JP 2632761B2 JP 22346892 A JP22346892 A JP 22346892A JP 22346892 A JP22346892 A JP 22346892A JP 2632761 B2 JP2632761 B2 JP 2632761B2
Authority
JP
Japan
Prior art keywords
layer
semiconductor element
substrate
metal
conductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP22346892A
Other languages
Japanese (ja)
Other versions
JPH0653382A (en
Inventor
俊也 松原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MITSUI HAITETSUKU KK
Original Assignee
MITSUI HAITETSUKU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MITSUI HAITETSUKU KK filed Critical MITSUI HAITETSUKU KK
Priority to JP22346892A priority Critical patent/JP2632761B2/en
Publication of JPH0653382A publication Critical patent/JPH0653382A/en
Application granted granted Critical
Publication of JP2632761B2 publication Critical patent/JP2632761B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body

Landscapes

  • Chemically Coating (AREA)
  • ing And Chemical Polishing (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、特定の機能を有する電
子機能素子が搭載される半導体素子搭載用基板及び半導
体素子搭載用基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for mounting a semiconductor element on which an electronic functional element having a specific function is mounted, and to a method of manufacturing the substrate for mounting a semiconductor element.

【0002】[0002]

【従来の技術】従来の半導体装置に使用する多層の半導
体素子搭載用基板は、予めプレス加工によって、所定の
形状に形成された複数の薄板金属板を中間部に接着剤層
を介して重合して製造するか、あるいは絶縁性のある樹
脂板の上に金属箔を貼着し、これに所定のエッチング加
工した単位基材を接着剤によって複数枚接合して製造さ
れていた。そして、前記半導体素子搭載用基板の表面に
はインナーリードが形成されて、該半導体素子搭載用基
板の中央に半導体素子を搭載すると共に、該半導体素子
のパット部と前記インナーリードとを金属ワイヤによっ
て連結し、更に別に用意された外側のアウターリードと
前記インナーリードの端部とを連結し、周知の樹脂封止
を行って半導体装置を製造していた。
2. Description of the Related Art A multi-layer semiconductor element mounting substrate used in a conventional semiconductor device is formed by laminating a plurality of thin metal plates formed in a predetermined shape to an intermediate portion thereof through an adhesive layer by press working. Alternatively, a metal foil is stuck on a resin plate having an insulating property, and a plurality of unit base materials that have been subjected to a predetermined etching process are bonded to each other with an adhesive. An inner lead is formed on the surface of the substrate for mounting a semiconductor element, and a semiconductor element is mounted at the center of the substrate for mounting a semiconductor element, and a pad portion of the semiconductor element and the inner lead are connected by a metal wire. The semiconductor device is manufactured by connecting the outer lead and the end of the inner lead, which are further prepared separately, and performing a well-known resin sealing.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、前記従
来例に係る半導体素子搭載用基板においては、プレス加
工した金属板を使用する場合には、各金属板を所定厚み
の接着剤層(通常は、両面テープ)を介して重合するの
で、基材全体が厚くなって、これを用いる半導体装置が
厚くなり用途に制限があった。従って、前記従来法によ
っては、近年要求される高密度の半導体装置の薄型化が
困難であるという問題点があった。また、プレス加工に
よって、各金属板を個別に成形し、重合わせる場合に
は、各金属板が位置れを起こしやすく、この為、細心
の注意を払って製造する必要があり、結果としてコスト
高になるという問題点もあった。そして、前記単位基材
を重合して半導体素子搭載用基板を製造する場合には、
厚くなるという問題点の他、組立作業中に表面の金属箔
が剥離する場合があり、後の組立工程において支障が生
ずるという問題点があった。本発明はかかる事情に鑑み
てなされたもので、薄型化が可能で、しかも高品質で製
造コストの安い半導体素子搭載用基板及び半導体素子搭
載用基板の製造方法を提供することを目的とする。
However, in the case of using a pressed metal plate in the semiconductor element mounting substrate according to the conventional example, each metal plate is bonded to an adhesive layer having a predetermined thickness (usually, Since the polymerization is carried out via a double-sided tape, the entire base material becomes thicker, and the semiconductor device using the same becomes thicker, which limits the application. Therefore, the conventional method has a problem that it is difficult to reduce the thickness of a high-density semiconductor device required in recent years. Further, by press working, shaping each metal sheet individually, when combining it heavy, prone to the metal plate Re not a position, Therefore, it is necessary to manufacture with great care, as a result There was also a problem that the cost was high. And when manufacturing the semiconductor element mounting substrate by polymerizing the unit base material,
In addition to the problem that the metal foil becomes thick, the metal foil on the surface may be peeled off during the assembling operation, which causes a problem in the subsequent assembling process. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor element mounting substrate and a method for manufacturing a semiconductor element mounting substrate that can be reduced in thickness, are high-quality, and have low manufacturing costs.

【0004】[0004]

【課題を解決するための手段】前記目的に沿う請求項1
記載の半導体素子搭載用基板は、中央に半導体素子が搭
載され、周辺には該半導体素子のパットに金属ワイヤを
介して連結される多数のインナーリードと電源用導体層
接地用導体層が層状に設けられた半導体素子搭載用基
板において、基材に金属板を使用すると共に、該基材上
に、下層に接合する絶縁性の接着剤層、該接着剤層の表
面に固着された金属粉層及び該金属粉層の表面に形成さ
れためっき層からなる下部絶縁導体層を、前記素子搭載
部分においては、それぞれの前記めっき層が下段から順
次露出するように複数段形成し、しかも、最上部のめっ
き層はフォトエッチングによって前記インナーリードが
形成されて構成されている。また、請求項2記載の半導
体素子搭載用基板の製造方法は、金属製の薄板条材の側
部にパイロット孔を形成すると共に、その内部に、複数
の連結片によって内外が部分的に連結された分離用透孔
によって囲まれる四角形の基材を形成し、該基材の特定
領域に、まず絶縁性のある接着剤を塗布し、該接着剤の
上に金属粉を散布固着した後、該散布された金属粉末上
にめっきを行って導電層を形成する被膜形成処理を複数
回行って複数段の下部絶縁導体層を形成し、しかも、前
記被膜形成処理においては、中央に搭載する半導体素子
の周囲に、前記下部絶縁導体層の導電層を下段から順次
露出させて、電源用導体層と接地用導体層を形成する
共に、最表面の導電層にはフォトエッチング処理によっ
て前記半導体素子に金属ワイヤを介して連結するインナ
ーリードを形成するようにして構成されている。以上の
発明において、金属粉は銅粉、めっきは銅めっきを用い
るのが、好ましいが、エッチング可能な金属(例えば、
ニッケル、ニッケル合金等)であれば、前記金属粉及び
めっきに、他の金属、あるいは合金を使用することも可
能である。
According to the present invention, there is provided a semiconductor device comprising:
In the substrate for mounting a semiconductor element described above, a semiconductor element is mounted in the center, and a number of inner leads, a power supply conductor layer, and a grounding conductor layer which are connected to a pad of the semiconductor element via a metal wire are formed in the periphery. In the substrate for mounting a semiconductor element provided in the above, a metal plate is used as a base material , an insulating adhesive layer to be joined to a lower layer on the base material, and a metal powder fixed to a surface of the adhesive layer. A lower insulating conductor layer composed of a layer and a plating layer formed on the surface of the metal powder layer, in the element mounting portion, a plurality of steps are formed so that each of the plating layers is sequentially exposed from a lower step; The upper plating layer is formed by forming the inner leads by photoetching. According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device mounting substrate, wherein a pilot hole is formed in a side portion of a thin metal strip, and the inside and outside of the pilot hole are partially connected by a plurality of connecting pieces. Forming a rectangular substrate surrounded by the separation through-holes, first applying an insulating adhesive to a specific region of the substrate, spraying and fixing metal powder on the adhesive, A plurality of lower-layer insulated conductor layers are formed by performing a coating process of forming a conductive layer by plating on a metal powder sprayed a plurality of times, and in the coating process, a semiconductor element mounted at the center around, said by sequentially exposing the lower insulated conductor layer conductive layer from the lower, both <br/> a power conductor layer to form a conductor layer for grounding, the conductive layer of the outermost surface by photoetching Connected to the semiconductor element via a metal wire And it is configured so as to form inner leads to. In the above invention, it is preferable to use copper powder for the metal powder and copper plating for the plating.
Other metals or alloys can be used for the metal powder and the plating as long as they are nickel, a nickel alloy, or the like.

【0005】[0005]

【作用】請求項1記載の半導体素子搭載用基板、請求項
2記載の半導体素子搭載用基板の製造方法においては、
基材に金属板を使用しているので、これによって、半導
体素子から発生する熱を放散することができる。そし
て、前記金属板の上に、接着剤層を塗布し、その上に金
属粉を、そして該金属粉の上にめっきを施した下部絶縁
導体層を複数段形成しているので、金属粉と接着剤層と
の馴染みが良く、この上にめっきをしているので、金属
粉とめっきからなる導電層の剥離を防止できる。そし
て、前記下部絶縁導体層の中央の素子搭載部分において
は、前記導体層が下段から徐々に露出するように形成し
ているので、これらの導体層をグランド(接地)、電源
として使用することができ、これによって半導体素子と
インナーリードとの配線の簡略化を図ることができると
共に、下部絶縁導体層間にコンデンサーが形成されて雑
音等を回避でき、これによって半導体素子の誤動作を防
止できる作用を有する。更には、最上段のめっき層はフ
ォトエッチングによってインナーリードが形成されてい
るので、これによって素子からの信号線を結線すること
ができる。
According to the method of manufacturing a substrate for mounting a semiconductor element according to the first aspect and the method of manufacturing the substrate for mounting a semiconductor element according to the second aspect,
Since the metal plate is used as the base material , heat generated from the semiconductor element can be dissipated. Then, an adhesive layer is applied on the metal plate, a metal powder is formed thereon, and a lower insulated conductor layer plated on the metal powder is formed in a plurality of stages. The adhesion to the adhesive layer is good, and the plating is performed thereon, so that the conductive layer made of the metal powder and the plating can be prevented from peeling off. In the element mounting portion at the center of the lower insulated conductor layer, since the conductor layer is formed so as to be gradually exposed from the lower stage, these conductor layers can be used as ground (ground) and power supply. Accordingly, the wiring between the semiconductor element and the inner lead can be simplified, and a capacitor can be formed between the lower insulated conductor layers to avoid noise and the like, thereby having the effect of preventing malfunction of the semiconductor element. . Further, since the inner lead is formed in the uppermost plating layer by photoetching, a signal line from the element can be connected.

【0006】[0006]

【実施例】続いて、添付した図面を参照しつつ、本発明
を具体化した実施例につき、説明し、本発明の理解に供
する。ここに、図1は本発明の一実施例に係る半導体素
子搭載用基板の製造方法を示す工程図、図2は同半導体
素子搭載用基板の部分拡大図、図3は同部分拡大断面
図、図4は他の実施例に係る半導体素子搭載用基板の平
面図である。なお、図1には各製造工程を隣合うリード
フレームの基板によって模擬的に示したが、(A)〜
(I)は個別に各処理工程の群を示すものである。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; Here, FIG. 1 is a process diagram showing a method for manufacturing a semiconductor element mounting substrate according to an embodiment of the present invention, FIG. 2 is a partially enlarged view of the semiconductor element mounting substrate, FIG. FIG. 4 is a plan view of a semiconductor element mounting substrate according to another embodiment. Although each manufacturing process is schematically shown in FIG. 1 by using a substrate of an adjacent lead frame, FIGS.
(I) shows a group of each processing step individually.

【0007】図1(A)に示すように、銅、銅合金から
なる薄板条材10に所定のパイロット孔10aを形成す
ると共に、その内部に複数の連結片11によって部分的
に接合した分離用透孔12によって囲まれる四角形の基
材13をプレス加工によって形成する。前記連結片11
の表面及び/又は裏面には後工程で、該基材13の分離
が容易なように、Vノッチ14を同じくプレス加工によ
って形成しておく。
As shown in FIG. 1 (A), a predetermined pilot hole 10a is formed in a thin strip member 10 made of copper or a copper alloy, and a plurality of connecting pieces 11 are used to partially separate the pilot hole 10a therein. A rectangular base material 13 surrounded by the through holes 12 is formed by press working. The connection piece 11
A V-notch 14 is also formed on the front and / or back surface by press working in a later step so that the substrate 13 can be easily separated.

【0008】次に、図1(B)に示すように、基材13
にその縁部分を残して絶縁性の接着剤を塗布する。この
処理はスクリーン印刷法によって行う。そして、この第
1の接着剤層15が乾かない内に、図1(C)に示すよ
うに金属粉の一例である銅粉16を塗布する。この銅粉
16の塗布は基材13の上に適当なマスキングを行っ
て、該銅粉16を吹きつけても良いが、通常は底部にス
クリーンを備えた升内に銅粉16を入れて、これを前記
第1の接着剤層15の上に乗せて、前記スクリーンを通
じて銅粉16を落下させ、第1の接着剤層15の所定領
域に接合させる。これによって銅粉16は第1の接着剤
層15の内部に食い込むので、銅粉16が充分な強度を
有して第1の接着剤層15に固着される。前記第1の接
着剤層15が充分に乾いた後、図1(D)に示すよう
に、他の部分はレジスト膜でマスキングして、前記銅粉
16の上に無電解銅めっきを行い、これによって、銅粉
16と銅めっき層が一体となって、前記第1の接着剤層
15の上に剥離困難な第1の導体層17を形成し、以上
の処理によって一層目の下部絶縁導体層を形成する。
Next, as shown in FIG.
Is applied with an insulating adhesive while leaving its edge. This process is performed by a screen printing method. Then, while the first adhesive layer 15 does not dry, a copper powder 16 which is an example of a metal powder is applied as shown in FIG. The copper powder 16 may be applied by performing appropriate masking on the substrate 13 and spraying the copper powder 16, but usually, the copper powder 16 is put in a box having a screen at the bottom, This is put on the first adhesive layer 15, and the copper powder 16 is dropped through the screen to be bonded to a predetermined area of the first adhesive layer 15. As a result, the copper powder 16 bites into the first adhesive layer 15, so that the copper powder 16 has a sufficient strength and is fixed to the first adhesive layer 15. After the first adhesive layer 15 is sufficiently dried, other portions are masked with a resist film, and electroless copper plating is performed on the copper powder 16 as shown in FIG. As a result, the copper powder 16 and the copper plating layer are united to form the first conductive layer 17 that is difficult to peel off on the first adhesive layer 15, and the first lower insulated conductive layer is formed by the above processing. To form

【0009】そして、図1(E)に示すように、中央の
素子搭載部より少し広い領域18を残して、第1の導体
層17の上にスクリーン印刷法によって絶縁性の接着剤
を塗布し、第2の接着剤層19を形成する。なお、該第
2の接着剤層19の外側は前記第1の導体層17を完全
に覆っても良いし、この実施例のように少し残しても良
い。この第2の接着剤層19が未硬化の内に、前記処理
と同様な処理によって、銅粉16を塗布し、その上に無
電解めっきを行い、図1(F)に示すように第2の導体
層20を形成し、これによって2層目の下部絶縁導体層
を形成する。
Then, as shown in FIG. 1E, an insulating adhesive is applied on the first conductor layer 17 by a screen printing method, leaving an area 18 slightly larger than the central element mounting portion. Then, a second adhesive layer 19 is formed. The outside of the second adhesive layer 19 may completely cover the first conductor layer 17 or may be slightly left as in this embodiment. While the second adhesive layer 19 is uncured, a copper powder 16 is applied by the same processing as described above, and electroless plating is performed thereon. Is formed, thereby forming a second lower insulated conductor layer.

【0010】この後、更に第2の導体層20の上に絶縁
性の接着剤をスクリーン法によって塗布し、図1(G)
に示すように、第3の接着剤層21を形成するが、内側
の素子搭載部の周囲領域に前記第2の導体層20が少し
の幅露出するようにして行う。そして、前記第3の接着
剤層21の上に、前記と同様な方法によって銅粉16を
塗布し、充分乾いてからこの上に銅めっきを行い、第3
の導体層22を形成し、最上部の下部絶縁導体層を形成
する。次に、全体をレジスト膜で覆った後、前記第3の
導体層22の上にインナーリード23をフォトエッチン
グする。
Thereafter, an insulating adhesive is further applied on the second conductor layer 20 by a screen method, and FIG.
As shown in (3), the third adhesive layer 21 is formed in such a manner that the second conductor layer 20 is exposed to a small width in the peripheral region of the inner element mounting portion. Then, a copper powder 16 is applied on the third adhesive layer 21 by the same method as described above, and after sufficiently dried, copper plating is performed thereon.
And the uppermost lower insulated conductor layer is formed. Next, after the whole is covered with a resist film, the inner leads 23 are photo-etched on the third conductor layer 22.

【0011】この後、図3に示すように、中央に所定の
半導体素子24を絶縁テープを介して固着し、銅、アル
ミ、金線等からなる金属ワイヤによって、半導体素子2
4のパットと前記インナーリード23とを結線する。こ
の場合、半導体素子24に多数設けられているグランド
及び電源の結線は、内側に露出している第1及び第2の
導体層17、20に接続する。そして、前記Vノッチ1
4部分で該基材13を分離した後、プレス加工によって
形成されるアウターリードに接続されるが、前記インナ
ーリードとアウターリードの接続は、半田、直接圧着、
金属ワイヤによるボンディングであっても良いし、導電
性接着剤によって接合しても良い。また、前記第1、第
2の導体層17、20と前記アウターリードとの結線
は、表面の特定のインナーリードと周知のインナーバリ
ヤーホールを用いて連結し、該インナーリードと前記ア
ウターリードを接続するようにしても良いし、第1、第
2の導体層17、20の一部を外部に露出させ、金属ワ
イヤを用いたボンディングによって行って良い。以上の
工程を経て、半導体素子24が搭載されて所定の結線が
行われた基材13、アウターリードの一部を樹脂封止を
行い、薄型の半導体装置が出来上がる。
Thereafter, as shown in FIG. 3, a predetermined semiconductor element 24 is fixed at the center via an insulating tape, and the semiconductor element 2 is connected to a metal wire made of copper, aluminum, gold wire or the like.
4 and the inner lead 23 are connected. In this case, a large number of grounds provided on the semiconductor element 24 are provided.
And the connection of the power supply is connected to the first and second conductor layers 17 and 20 exposed inside. And the V notch 1
After separating the base material 13 in four parts, the base lead 13 is connected to an outer lead formed by press working. The connection between the inner lead and the outer lead is performed by soldering, direct pressure bonding,
The bonding may be performed using a metal wire, or the bonding may be performed using a conductive adhesive. Also, the connection between the first and second conductor layers 17 and 20 and the outer leads is connected to a specific inner lead on the surface by using a well-known inner barrier hole, and the inner lead and the outer lead are connected. Alternatively, a portion of the first and second conductor layers 17 and 20 may be exposed to the outside, and bonding may be performed using a metal wire. Through the above steps, the base material 13 on which the semiconductor element 24 is mounted and the predetermined connection is made, and a part of the outer leads are resin-sealed, and a thin semiconductor device is completed.

【0012】前記実施例においては、一つの基材に一つ
の半導体素子を搭載した物について説明したが、図4に
示すように一つの基材25上に複数のインナーリード群
26、27を作って複数の半導体素子を搭載させるよう
にした半導体装置にも適用できる。この場合、これらの
半導体素子に共通なグランド(アース)、電源等を共通
導体層とすることもできる。また、前記実施例におい
ては、底部の薄板条材は、放熱板として作用するのみで
あるが、第3のめっき層を形成を省略し、第2のめっき
層の上にインナーリードをフォトエッチングし、第1の
めっき層及び前記条材を、電源あるいはグランドのライ
ンとして利用する場合も本発明は適用される。
In the above-described embodiment, the case where one semiconductor element is mounted on one base material has been described, but a plurality of inner lead groups 26 and 27 are formed on one base material 25 as shown in FIG. The present invention can also be applied to a semiconductor device in which a plurality of semiconductor elements are mounted. In this case, a ground (earth), power supply, and the like common to these semiconductor elements can be used as a common conductor layer. In the above embodiment, the thin strip material at the bottom only functions as a heat sink, but the formation of the third plating layer is omitted, and the inner lead is photo-etched on the second plating layer. The present invention is also applicable to the case where the first plating layer and the strip material are used as a power supply or ground line.

【0013】[0013]

【発明の効果】請求項1記載の半導体素子搭載用基板及
び請求項2記載の半導体素子搭載用基板の製造方法にお
いては、薄板条材からなる基材上に絶縁性の接着剤層、
該接着剤層の表面に固着された金属粉層及び該金属粉層
の表面に形成されためっき層からなる下部絶縁導体層を
複数段形成するようにしているので、従来の製法による
多重積層の半導体素子搭載用基板に比較して、薄く構成
することができる。これによって薄型の半導体装置を提
供できることになった。また、上下の導体層が位置ずれ
を起こすことがなく、これによって、上下の導体層ある
いはインナーリードを連結するインナーバリヤーホール
等の形成も容易となり、廉価に半導体装置を製造でき
る。更には、最上層のインナーリードや下部のめっき層
が組立中に剥離することがなく、歩留りが向上し、半導
体装置の信頼性も向上した。
According to the method for manufacturing a substrate for mounting a semiconductor element according to the first aspect and the method for manufacturing a substrate for mounting a semiconductor element according to the second aspect, an insulating adhesive layer is provided on a base made of a thin strip.
Since the lower insulated conductor layer composed of the metal powder layer fixed to the surface of the adhesive layer and the plating layer formed on the surface of the metal powder layer is formed in a plurality of stages, the multi-layer structure by the conventional manufacturing method is used. It can be made thinner than a semiconductor element mounting substrate. As a result, a thin semiconductor device can be provided. In addition, the upper and lower conductor layers do not displace, thereby making it easier to form inner barrier holes for connecting the upper and lower conductor layers or the inner leads, and to manufacture a semiconductor device at low cost. Furthermore, the uppermost inner lead and the lower plating layer did not peel off during assembly, and the yield was improved, and the reliability of the semiconductor device was also improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例に係る半導体素子搭載用基板
の製造方法を示す工程図である。
FIG. 1 is a process chart showing a method for manufacturing a semiconductor element mounting substrate according to one embodiment of the present invention.

【図2】同半導体素子搭載用基板の部分拡大図である。FIG. 2 is a partially enlarged view of the semiconductor element mounting substrate.

【図3】同部分拡大断面図である。FIG. 3 is a partially enlarged sectional view of the same.

【図4】他の実施例に係る半導体素子搭載用基板の平面
図である。
FIG. 4 is a plan view of a semiconductor element mounting substrate according to another embodiment.

【符号の説明】[Explanation of symbols]

10 薄板条材 10a パイロット孔 11 連結片 12 分離用透孔 13 基材 14 Vノッチ 15 第1の接着剤層 16 銅粉 17 第1の導体層 18 領域 19 第2の接着剤層 20 第2の導体層 21 第3の接着剤層 22 第3の導体層 23 インナーリード 24 半導体素子 25 基材 26 インナーリード群 27 インナーリード群 DESCRIPTION OF SYMBOLS 10 Thin strip material 10a Pilot hole 11 Connecting piece 12 Separation through hole 13 Base material 14 V notch 15 First adhesive layer 16 Copper powder 17 First conductor layer 18 Area 19 Second adhesive layer 20 Second Conductor layer 21 Third adhesive layer 22 Third conductor layer 23 Inner lead 24 Semiconductor element 25 Base 26 Inner lead group 27 Inner lead group

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 中央に半導体素子が搭載され、周辺には
該半導体素子のパットに金属ワイヤを介して連結される
多数のインナーリードと電源用導体層と接地用導体層が
層状に設けられた半導体素子搭載用基板において、基材 に金属板を使用すると共に、該基材上に、下層に接
合する絶縁性の接着剤層、該接着剤層の表面に固着され
た金属粉層及び該金属粉層の表面に形成されためっき層
からなる下部絶縁導体層を、前記素子搭載部分において
は、それぞれの前記めっき層が下段から順次露出するよ
うに複数段形成し、しかも、最上部のめっき層はフォト
エッチングによって前記インナーリードが形成されてい
ることを特徴とする半導体素子搭載用基板。
1. A semiconductor element is mounted in the center, and a number of inner leads, a power supply conductor layer, and a grounding conductor layer are provided in layers around the periphery of the semiconductor element and connected to a pad of the semiconductor element via a metal wire. in the substrate for mounting a semiconductor element, with the use of metal plates to the substrate, on to the substrate, insulating adhesive layer, the metal powder layer is adhered to the surface of the adhesive layer and the metal to be bonded to the lower layer A lower insulated conductor layer made of a plating layer formed on the surface of the powder layer is formed in a plurality of stages in the element mounting portion such that the plating layers are sequentially exposed from a lower stage, and furthermore, an uppermost plating layer A substrate for mounting a semiconductor element, wherein the inner leads are formed by photoetching.
【請求項2】 金属製の薄板条材の側部にパイロット孔
を形成すると共に、その内部に、複数の連結片によって
内外が部分的に連結された分離用透孔によって囲まれる
四角形の基材を形成し、該基材の特定領域に、まず絶縁
性のある接着剤を塗布し、該接着剤の上に金属粉を散布
固着した後、該散布された金属粉上にめっきを行って導
電層を形成する被膜形成処理を複数回行って複数段の下
部絶縁導体層を形成し、しかも、前記被膜形成処理にお
いては、中央に搭載する半導体素子の周囲に、前記下部
絶縁導体層の導電層を下段から順次露出させて、電源用
導体層と接地用導体層を形成する共に、最表面の導電
層にはフォトエッチング処理によって前記半導体素子に
金属ワイヤを介して連結するインナーリードを形成する
ことを特徴とする半導体素子搭載用基板の製造方法。
2. A square base material in which a pilot hole is formed in a side portion of a thin metal strip, and a pilot hole is formed inside the pilot hole and is surrounded by a separation through hole whose inside and outside are partially connected by a plurality of connecting pieces. Is formed, first, an insulating adhesive is applied to a specific area of the base material, and a metal powder is sprinkled and fixed on the adhesive, and then plating is performed on the sprinkled metal powder. A film forming process for forming a layer is performed a plurality of times to form a plurality of lower insulated conductor layers, and in the film forming process, a conductive layer of the lower insulated conductor layer is formed around a semiconductor element mounted at the center. the by sequentially exposed from the lower, together to form the power supply conductor layer for grounding conductor layer, the conductive layer of the outermost surface to form a inner leads connecting through the metal wire to the semiconductor device by a photo-etching process Characterized by the half A method for manufacturing a substrate for mounting a conductive element.
JP22346892A 1992-07-29 1992-07-29 Semiconductor element mounting substrate and method of manufacturing semiconductor element mounting substrate Expired - Fee Related JP2632761B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22346892A JP2632761B2 (en) 1992-07-29 1992-07-29 Semiconductor element mounting substrate and method of manufacturing semiconductor element mounting substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22346892A JP2632761B2 (en) 1992-07-29 1992-07-29 Semiconductor element mounting substrate and method of manufacturing semiconductor element mounting substrate

Publications (2)

Publication Number Publication Date
JPH0653382A JPH0653382A (en) 1994-02-25
JP2632761B2 true JP2632761B2 (en) 1997-07-23

Family

ID=16798618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22346892A Expired - Fee Related JP2632761B2 (en) 1992-07-29 1992-07-29 Semiconductor element mounting substrate and method of manufacturing semiconductor element mounting substrate

Country Status (1)

Country Link
JP (1) JP2632761B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2765623B2 (en) * 1995-09-29 1998-06-18 株式会社ユーテクノロジー Self-propelled blasting equipment

Also Published As

Publication number Publication date
JPH0653382A (en) 1994-02-25

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