JP2630258B2 - Delay optimization method and logic synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay optimizing method and a logic synthesizing apparatus, and more particularly to a delay optimizing method and a logic synthesizing apparatus for optimizing a delay by using a retiming method by moving registers.

[0002]

2. Description of the Related Art Retiming, which is one of the delay optimizing techniques in logic synthesis, is defined as a sequential circuit in which an input terminal or an output terminal of a path exceeding an allowable maximum delay value, which is one of constraint conditions, is used. By moving a register element (hereinafter referred to as a register) such as a DFF across (jumping) a combinational logic element between them, the maximum delay of the circuit can be reduced without changing the output logic with respect to the input signal, and each path delay can be reduced. This is a delay optimization method for equalizing the distribution of data and realizing a circuit operation in a faster clock cycle.

Here, an input terminal starts at an external input terminal (hereinafter referred to as an input terminal) or a register, and an output terminal terminates at an output terminal (hereinafter referred to as an output terminal) or a register via a combinational circuit. The signal path of the combinational logic circuit portion is called a path. A path that exceeds the allowable maximum delay value is called a critical path, and a path having the greatest degree of excess among the critical paths is called a worst critical path. The input terminal is the input terminal,
Since a path whose output terminal is an output terminal is a path that does not have a register at an end point, delay optimization by moving the register, that is, retiming cannot be applied to such a path.

[0004] A combinational logic circuit portion of a sequential circuit is called a combinational logic block (hereinafter, block), and each block is composed of a single or a plurality of combinational logic elements.

A conventional method for optimizing the delay of a sequential circuit by retiming is described in, for example, Technical Memorandum TM3.
72 MIT / LCS, MIT Laboratory, October 1987 (Technical Memo)
C. Lee Searson and J.B.Sachs (C.random MIT / LCS / TM372).
E. FIG. Leiserson and J.M. B. (Saxe)
Paper "Retiming Synchronous Circuit"
(Utry) ”, pp. 1-27 (Reference 1), the register directly connected to all the input terminals of a certain combinational logic element is deleted in the sequential circuit, and all the output terminals of this combinational logic element are removed. The basic theory describes that the operation of the output signal with respect to the input signal of the circuit does not change even if the register is directly inserted and connected, that is, even if the register is moved across the combinational logic element.

Further, as one of basic delay optimization methods based on retiming, it is determined whether a clock cycle given as a delay constraint condition can be realized by register movement as one of basic delay optimization methods by retiming. A delay optimization algorithm called FEAS is described. As a result of this determination, if it is feasible, an optimized circuit is obtained simultaneously with the determination, but if the clock cycle is too short to be feasible, an optimized circuit cannot be obtained.

In this algorithm FEAS, all external input and output terminals of a circuit to be optimized are virtually
The above circuit is formed into a loop by being collectively represented by a plurality of blocks, and the data structure has an equivalent circuit in which the combinational logic elements in the circuit are represented by blocks. The output terminals of all the critical paths are directly connected to the output terminals of this register so that the maximum delay of the path including the combinational circuit portion of the above-mentioned circuit is not more than the designated clock cycle. The movement in the output direction across the blocks is repeated until there is no more critical path in the circuit or up to a specified upper limit. If the critical path is resolved within the above upper limit number, it is determined that the circuit delay within the designated clock cycle can be realized, and at the same time, a circuit with the optimized delay is obtained.
If the critical path is not resolved even after repeating the upper limit, it is determined that the circuit delay within the designated clock cycle cannot be realized. In this case, a circuit with an improved delay cannot be obtained.

In the first conventional delay optimization method using the algorithm FEAS, the actual movement direction of the register is only one direction, but the register is moved across blocks representing external input and output terminals. Realizes a movement equivalent to register movement in the reverse direction.

As a modification of the first conventional delay optimization method, the second conventional delay optimization method allows the actual moving direction of the register to be changed not only in one direction but also in the opposite direction depending on the circuit structure. Can be applied.

[0010] Based on the algorithm FEAS described above,
Referring to FIG. 9, which shows a processing flow of a general conventional first delay optimization method using a loop-like equivalent circuit in which all the external input and output terminals are combined by one combinational logic block, The processing flow of the first delay optimization method includes a step Q1 of storing an initial arrangement of registers in register arrangement search history data, a step Q8 of reducing a maximum delay by moving a register to a worst critical path, and a register arrangement search history. Step Q9 for collating and additionally storing data.

For a circuit to be subjected to delay optimization, external input and output terminals are collectively represented in one virtual block to form a circuit loop, and an equivalent circuit in which a combinational logic element is represented by a block is as follows. Is performed.

First, in step Q1, the initial arrangement of registers is stored in register arrangement search history data. The register arrangement search history data is for sequentially storing and accumulating the searched register arrangement sequentially. By referring to the register arrangement search history data, the register arrangement searched in the past can be known. You can check if you have already searched.

At step Q3, a critical path is detected. However, for paths that pass through blocks representing external input and output terminals on the equivalent circuit, if the delay of the path from the input terminal to the output terminal register exceeds the constraint value, or if the path from the output terminal register to the output terminal If the delay of the path to the path exceeds the constraint value, it is defined as a critical path. If there is no critical path, the process is terminated. If a critical path is detected, the worst critical path is selected in step Q4.

In step Q5, the output end register of the worst critical path is moved in the input direction across the combinational logic block directly connected to the input terminal of the output end register. In step Q6, the register arrangement search history data is compared. If the register arrangement matches the register arrangement searched in the past, it can be determined that all possible register arrangements have been searched, and the delay optimization ends. Otherwise, in step Q7, the information of the register arrangement after the register is moved is additionally stored in the register arrangement search history data, and the process returns to step Q2.

An example of application of the first conventional delay optimization method is as follows: (a) before optimization of a target circuit;
FIG. 1 (e) shows the final result of the optimization in (f), respectively.
0, the target circuit shown in FIG.
1, R2, R3, an input terminal T1, an output terminal T3,
Block B1 expressing a combinational logic part of a sequential circuit
To 1B7. Normally, each block has a plurality of fan-ins and fan-outs, but here, for simplicity, each block is represented by a single fan-in and fan-out.

On the equivalent circuit, the output terminal T3 and the input terminal T
1 is regarded as one block, and a path indicated by a broken line from the register R3 to the register R1 via the output terminal T3 and the input terminal T1 is a path on the equivalent circuit.

In FIG. 10, it is assumed that each of the blocks B1 to B7 has a delay of 1 (unit time), a clock cycle = 2 is given as a delay constraint condition, and the delay is optimized so that the maximum delay of any path is 2 or less. The case where the conversion is performed will be described.

First, in FIG. 10A, the initial arrangement of registers is stored in register arrangement search history data in step Q1. By the steps Q2 and Q3, the path P
Since the delay of each of P1 and P2 is 4 and 3, respectively, it is known that these are critical paths. Since the worst critical path is P1, the worst critical path P1 is selected as a processing target in step Q4. I do. In step Q5, the register R3 at the output end of the critical path P1 is moved in the input direction across the block 107, and as a result, the state shown in FIG. In step Q6, the register arrangement search history data is compared to confirm that the register arrangement does not match the register arrangement searched in the past. In step Q7, the register arrangement information of FIG. 10B is additionally stored in the register arrangement search history data, and the process returns to step Q2.

Next, in FIG. 10B, steps Q2 to Q
4, the worst critical path P2 is selected as a processing target. Since the worst critical path P2 is terminated on the equivalent circuit by the register R1 via the output terminal T3 and the input terminal T1, the input terminal T1, the output terminal T3, and the block B7 are repeated by repeating steps Q2 to Q6. By moving the register R1 in the input direction, FIG.
The state shown in FIG. In step Q7, the register arrangement information of FIG. 10C is additionally stored in the register arrangement search history data, and the process returns to step Q2.

The processing is continued in the same manner as in FIG.
After (d) and (e), the final result shown in (f) is obtained.

In FIG. 10 (f), it is confirmed in step Q2 that the critical path has been resolved, and the processing is terminated. FIG. 10 (f) satisfies all delay constraints and eliminates the critical path.

[0022]

In the above-mentioned first conventional delay optimization method, a critical path in a circuit being optimized is selected, and a register at an output terminal of the selected critical path is moved in an input direction. A solution is sequentially searched for only by itself, but the actual moving direction of the register can be only one direction, and the register moving in the opposite direction is to move the register across combinational logic blocks representing external input and output terminals. Therefore, there is a disadvantage that a huge amount of processing time is required due to the fact that the register cannot be directly moved in the reverse direction depending on the circuit configuration and scale.

Further, the second conventional delay optimization method in which the direction of register movement is reversible depending on the circuit structure is a method of selecting a critical path to be processed and a method of determining a register to be moved and its moving direction. Is simplistic in that all possible solutions are searched inefficiently, redundant register moves are performed, and a huge processing time is required, especially when applied to a large-scale circuit. there were.
Therefore, it has been a problem to establish a method for efficiently determining a register to be moved and a moving direction of the register from the state of the circuit.

[0024]

SUMMARY OF THE INVENTION The delay optimization method of the present invention begins at either an input terminal or a register and terminates at either an output terminal or a register via a block comprising a combination of a plurality of logic circuits. A signal path straddling the block of registers at the input or output end of the first path of a sequential circuit including a first path and a second path not exceeding a predetermined maximum allowable delay value. In the delay optimizing method for reducing the maximum delay of the first path by moving and equalizing the delay distribution between the first and second paths and realizing a circuit operation with a faster clock cycle, A flag indicating a movable direction is added to each of the registers or each of the blocks in a data structure describing a logic circuit, and one end point is an input terminal or Detecting the first path whose input terminal is the other end of which is the register, and performing the selection of the register to be moved in the first path and the determination of the movement direction according to the information of the flag. It is a feature.

The logic synthesizing apparatus of the present invention is a signal path which starts at one of an input terminal and a register and ends at one of an output terminal and a register via a block composed of a combination of a plurality of logic circuits. A library input unit for reading information of a technology library block including a logic and a delay value constituting a logic synthesis target circuit including a sequential circuit including a first path not exceeding an allowable maximum delay value and a second path not exceeding the allowable maximum delay value A circuit input unit for reading connection information of the logic synthesis target circuit, a constraint input unit for reading constraint conditions including the allowable maximum delay value, and a logic of a synthesis result of the read logic synthesis target circuit. A logic optimization unit for optimizing, a technology mapping unit for allocating the technology library block to the logic synthesis target circuit, Relocation of the register at the input or output end of the path by moving the block across the block reduces the maximum delay of this first path, thereby equalizing the distribution of delay between the first and second paths, and increasing the speed. And a delay optimizing unit for realizing a circuit operation in a specific clock cycle, wherein the delay optimizing unit can move to each of the registers or each of the blocks in the data structure of the technology library block. And a delay optimizing means for selecting the register to be moved in the first path and determining the moving direction according to the information of the flag. .

[0026]

FIG. 2 is a block diagram showing the data structure of a delay optimization target logic circuit to which the embodiment of the present invention is applied. Referring to FIG. 2, the delay optimization target logic circuit shown in FIG. , T2, an output terminal T3, combinational logic blocks (hereinafter, blocks) B1 to B3, and registers R1 to R3.
R3 and flags F1 to F3 that hold information for controlling the movable directions of the registers R1 to R3.

Flags F1 to F3 indicate "no direction restriction (N
L), “movable only in the input direction (MI)”, and “movable only in the output direction (MO)”.
It indicates a movable direction whose initial value is “no direction restriction (NL)”. When moving each of the registers R1 to R3,
The moving direction is determined according to the held information of the flag corresponding to the register.

Next, referring to FIG. 1 showing a flowchart of the first embodiment of the present invention, the processing flow of the present embodiment reduces the maximum delay of a critical path having an input terminal or an output terminal as one end point. Step S12 to select the worst critical path from all paths, determine the register to be moved by referring to the flag information and determine the direction of movement, and Step S14 to perform register movement and flag information setting Consists of

Step S12 comprises steps S1 to S3, step S13 comprises steps S4 to S6,
Step S14 includes steps S7 to S11.

The operation of this embodiment will be described with reference to FIGS. 1 and 2. First, in step S1, a critical path having an input terminal or an output terminal as one end point and the other as a register is detected. If not detected, the process proceeds to step S4. If it is detected, in step S2, for a critical path having an output terminal as an output terminal, the input terminal register is connected to a block directly connected to the output terminal of the register (hereinafter referred to as an output block) in an output direction. By moving the register at the output end for the critical path whose input end is the input terminal across the block directly connected to the input terminal of this register (hereinafter referred to as the input side block), The maximum delay of these critical paths is reduced.

At step S3, the flag of the moved register indicates "MO (movable only in the output direction)" if the register at the input end is moved in the output direction, and if the register at the output end is moved in the input direction. , Information of “MI (movable only in the input direction)” is set. Then, the process returns to step S1.

Next, in step S4, a critical path is detected for all paths. If no critical path is detected, the process ends. If a critical path is detected, the worst critical path is selected in step S5.

Next, in step S6, the flag of the register at the input end and the output end of the worst critical path selected in step S5 is referred to, and the combination of the information of the flag is used to determine the case 1, the case 2, the case 3, and the case 4. Proceed to one of them.

When the input terminal is an input terminal or the flag information of the input terminal register is "MI", and the output terminal is an output terminal or the flag information of the output terminal register is "MO". In some cases, neither the movement of the input end register in the output direction nor the movement of the output end register in the input direction to reduce the delay of the critical path is possible. The process ends (Case 1).

When the flag information of the input end register is "NL"
(No direction restriction) "or" M O ", and if the information of the flag of the output register is" MO "includes, but is not able to move to the input direction of the output terminal registers to the output direction of the input register Since the movement is possible, the process proceeds to step S7, in which the input end register is moved in the output direction across the output side block of this register, thereby reducing the delay of the worst critical path (case 2). Then, in step S10, the information of "MO" is set in the flag of the moved input terminal register, and the process returns to step S4.

When the flag information of the input end register is "MI"
And the information of the flag of the output end register is "NL"
Or, in the case of "MI", the input end register cannot be moved in the output direction, but the output end register can be moved in the input direction. By moving in the input direction across the input side block, the delay of the worst critical path is reduced (case 3). Then, in step S11, information of "movable only in the input direction" is set in the flag of the moved output end register, and the process returns to step S4.

The flag information of the input end register is "NL"
Alternatively, if the flag is “MO” and the information of the flag of the output terminal register is “NL” or “MI”, the input terminal register is moved in the output direction to reduce the delay of the critical path and the output terminal register is moved. Since both movement in the input direction are possible, the process proceeds to step S9. In this case, either the input terminal or the output terminal may be moved, but here, for convenience of explanation, the output terminal register is moved, and the output terminal register is input across the input side block of this register. By moving in the direction
Reduce the delay of the worst critical path (Case 4). However, in this case, no flag is set. Then, the process returns to step S4.

The above processing is repeated to optimize the delay so as to satisfy the delay constraint as much as possible.

Next, the application example of the delay optimizing method according to the present embodiment will be described with reference to FIG.
FIG. 3 (c) shows the final result of optimization in (f), respectively.
, The target circuit shown in FIG.
Registers R1, R2, and R3 having F2 and F3, respectively;
It includes an input terminal T1, an output terminal T3, and blocks B1 to B7 expressing a combinational logic circuit portion of a sequential circuit. Each ordinary block has a plurality of fan-ins and fan-outs. However, as in the conventional case, each block is simplified and represented by a single fan-in and a fan-out.

As in the conventional case, the blocks B1 to B7
Is 1 (unit time), clock cycle = 2 is given as a delay constraint condition, and delay optimization is performed so that the maximum delay of any path is 2 or less.

In step S1, the critical path P2 including the output terminal T3 is selected in preference to the worst critical path P1 not including the output terminal. By repeating steps S1, S2, and S3, the critical path P2 is selected.
Is moved in the output direction until the path P2 is no longer a critical path, and information of "MO (movable only in the output direction)" is set in the flag F3 of the register R3. become.

In FIG. 3B, since the critical path including the output terminal T3 has been eliminated and there is no critical path including the input terminal T1, the process proceeds to step S4. In step S4, a critical path is detected for all paths, and in step S5, the worst critical path P1 is selected. In the branch processing in step S6, the output end register R3 of the worst critical path P1 no longer has the flag F
3 cannot move in the output direction, the process proceeds to case 2. By repeating steps S4, S5, S6, S7, and S10, the output end register R2 of the path P1 is changed to the path P1.
Move in the output direction until is no longer the worst critical path, and in step S14, the information of "MO" is set in the flag F2 of the register R2, and as a result, the state of (c) is reached.

In FIG. 3C, a new worst critical path P3 is selected in steps S4 and S5. By the branching process in step S6, the output terminal register R2 of the worst critical path P3 cannot be moved in the output direction by the flag F2, so the process proceeds to case 2. In step S7, the input terminal register R1 is moved in the output direction. Then, in step S10, the information of "MO" is set in the flag F1 of the register R1, and the state of (d) is reached. In step S4, it is confirmed that the critical path has been resolved, and this processing is ended.

In the present embodiment, the path including the input or output terminal is preferentially processed, so that the time required for the calculation until the movement of the register is completed is calculated for all the critical paths of the equivalent circuit in a conventional loop. The method can be shortened by about 20% as compared with the method of moving the register. Further, by providing a flag for limiting the direction in which the register can be moved in the data structure, when 5% of the registers in the circuit are restricted in the movable range, the total calculation time is reduced by approximately Can be reduced by 10%.

Next, referring to FIG. 4, which is a block diagram showing a logic synthesizing apparatus including a delay optimizing unit 6 for executing the delay optimizing process according to the first embodiment which is the second embodiment of the present invention. The logic synthesizing apparatus according to the present embodiment shown in FIG. 1 includes a library input unit 1 for inputting technology library block information including logic and a delay value used for technology mapping of a logic circuit, and a circuit input unit 2 for reading a logic synthesis target circuit. A constraint input unit 3 for reading constraints such as a maximum delay value, a logic optimization unit 4 for optimizing the logic of the read logic synthesis target circuit, and a technology for allocating a technology library block to the logic synthesis target circuit The delay optimization according to the first embodiment includes a mapping unit 5, a flag addition unit 61 for adding a flag to a register of each path of the logic synthesis target circuit, and an optimization processing unit 62. A delay optimizing unit 6 for optimizing the delay of the logic synthesis target circuit by a logical method, a storage unit 7 for holding the technology library, the logic synthesis target circuit, and the constraint conditions, and outputting the logic circuit of the logic synthesis result. And a circuit output unit 8 that performs the operation.

Next, the operation of the present embodiment will be described with reference to FIG. 4 and FIG. 5 which shows the flow of processing of the present embodiment. The method of reducing the delay of the path is utilized in that the method is limited to the movement of the output terminal in the input direction of the register when the input terminal is included, and the movement of the input terminal in the output direction of the register when the output terminal is included. .

First, the library input unit 1 inputs the technology library 11 in which information such as the logic of the technology library block and the delay value is described by the library input process A 1, and stores the technology library 11 in the storage unit 7. Circuit input unit 2
Inputs the circuit description 12 by the circuit input processing A2 and stores it in the storage unit 7. The constraint condition input unit 3 inputs constraint conditions 13 such as delay and area for the circuit description 12 by the constraint input process A3, and stores them in the storage unit 7. Next, the logic optimization unit 4 optimizes the logic of the logic synthesis target circuit held in the storage unit 7 by the logic optimization process A4. Next, the delay optimizing unit 6 adds the flag corresponding to the register described in the first embodiment to the logic synthesis target circuit input in the circuit input processing A2 and held in the storage unit 7, In order to satisfy the above-mentioned delay constraint condition input in the input processing A3 and held in the storage unit 7, delay optimization such as register movement in a technology independent state is performed by the delay optimization processing A5 of the first embodiment. .

Next, the technology mapping unit 5 applies, to the logic synthesis target circuit held in the storage unit 7, the constraint condition such as the area input by the constraint input processing A 3 and held in the storage unit 7. A predetermined technology library block is allocated by technology mapping processing A6 for the purpose of satisfying the condition. This technology mapping process A6
After that, the delay optimizing unit 6 again executes the logic optimization target circuit held in the storage unit 7 by the delay optimizing process A7 in the technology dependent state for the purpose of satisfying the delay constraint condition. Performs delay optimization such as register movement. After the end of the delay optimizing process A7, the circuit output unit 8 outputs the circuit description 14 of the logic synthesis circuit resulting from the processes A1 to A7 by the circuit output process A8.

Next, referring to FIG. 7 which shows, by blocks, the data structure of a second delay optimization target logic circuit to which the third embodiment of the present invention is applied, a diagram of the second logic circuit shown in FIG. The difference from the first logic circuit shown in FIG.
Instead of the flags F1, F2, F3 for indicating the movable direction corresponding to each of R2, R3, blocks B1, B2, B3
Are provided with flags F11 to F13 which hold information on direction restrictions that can be moved by straddling an arbitrary register.

The flags F11 to F13 are set to "no direction limitation (NL)" and "movable to look in the input direction (MI
J) ”,“ Move in the output direction (MOJ) ”
, And indicates a movable direction whose initial value is “NL”. Registers R1 to R4
In the case of moving each of R3, the moving direction is determined according to the holding information of the flag of the block to be straddled. For example, if the information of the flag F13 is " MOJ ", the register R3 cannot move over the block B3 in the input direction.

Next, referring to FIG. 6, which is a flowchart showing the third embodiment of the present invention, the difference between the processing flow of the present embodiment and the first embodiment of FIG. When the register at the input end is moved in the output direction, "MOJ (movable by looking at the output direction)" is set in the flag of the inserted block. When the register at the output end is moved in the input direction, "MIJ ( 3A to set the information of the input terminal of the worst critical path selected in place of step 6 and the input side block of the output terminal register. Step 6A in which the process proceeds to one of Case 1, Case 2, Case 3, and Case 4 by referring to the flags
Step 10A for setting the information of “MOJ” in the flag of the block straddling in place of Step 10, and “MIJ” in the flag of the block straddling in place of Step 11
And step 11A for setting the above information.

The operation of this embodiment will be described with reference to FIGS. 6 and 7. First, the same step S as in the first embodiment is performed.
At 1, a critical path is detected. If not detected, the process proceeds to step S4. If detected, step S
In step 2, the register at the input terminal is moved in the output direction across the output side block of this register for the critical path whose output terminal is the output terminal, and the output is performed for the critical path whose input terminal is the input terminal. Moving the end registers in the input direction across the input blocks of these registers reduces the maximum delay of these critical paths.

In step S3A, if the register at the input end is moved in the output direction to the flag of the block straddled by the moved register, the register at the output end is set to "MOJ (movable by looking at the output direction)". When moving in the input direction, "MIJ (Move in the direction of the input is possible)"
Set the information of each. Then, the process returns to step S1.

Next, in step S4, critical paths are detected for all paths, and if detected, the worst critical path is selected in step S5.

Next, in step S6A, the respective flags of the output side block of the input end register of the worst critical path and the input side block of the output end register are referred to, and the combination of the information of the flags is used for Case 1, Case 2, The process proceeds to either Case 3 or Case 4.

When the input terminal is an input terminal or the information of the flag of the output block of the input terminal register is "MIJ", and the output terminal is the output terminal or of the input block of the output terminal register. If the flag information is "MO
In the case of "J", neither the movement of the input end register in the output direction nor the movement of the output end register in the input direction is possible, so that the delay of the worst critical path cannot be reduced. Case 1).

[0057] Information of the flag of the output-side block of the input register is "NL (no direction restriction)" or "M O J"
If the flag information of the input side block of the output end register is "MOJ", the output end register cannot be moved in the input direction but the input end register can be moved in the output direction. Proceeding to step S7, the delay of the worst critical path is reduced by moving the input end register in the output direction across the output side block of this register (case 2). Then, in step S10A, the information of “MOJ” is set to the flag of the block straddled by the moved input end register, and step S4
Return to

The flag information of the output side block of the input end register is "MIJ", and the flag information of the input side block of the output end register is "NL" or "MIJ".
, The input end register cannot be moved in the output direction, but the output end register can be moved in the input direction. Therefore, the process proceeds to step S8, where the output end register is connected to the input side block of this register. Further, by moving in the input direction, the delay of the worst critical path is reduced (case 3). Then, in step S11A,
The information of “MIJ” is set in the flag of the input side block of the moved output end register, and the process returns to step S4.

When the information of the flag of the output side block of the input end register is “NL” or “MOJ” and the information of the flag of the input side block of the output end register is “NL” or “MI”, Since both the movement of the input end register in the output direction and the movement of the output end register in the input direction are possible, the process proceeds to step S9. For convenience of explanation, it is assumed that the output end register is moved, and the output end register is moved in the input direction across the input side block of this register, thereby reducing the delay of the worst critical path (Case 4). In this case, the process returns to step S4 without setting the flag.

Next, the application example of the delay optimizing method of the present embodiment will be described as (a) before optimizing the target circuit and (b) during the optimizing of the target circuit.
Referring to FIG. 8, which shows the final result of the optimization in (c) and (f) common constituent elements with those of FIG. 3 with common reference characters / numbers, respectively, the target circuit shown in FIG. Registers R1, R2, R3, input terminal T1, and output terminal T3
Represents the combinational logic circuit portion of the sequential circuit and the flag F1
1 to F17, respectively. These flags F11 to F17 are initially set to "N
L (no movement direction restriction) "is set.

Further, similarly to the first embodiment, the block B
It is assumed that each delay of 1 to B7 is 1 (unit time), clock cycle = 2 is given as a delay constraint, and delay optimization is performed so that the maximum delay of any path is 2 or less.

Steps S1 to S3A of step S12A
Is repeated, the input end register R3 of the selected critical path P2 is moved in the output direction until the path P2 is no longer a critical path, and the flag F14 of the block B4 on the input side of the register R3 is set to "MOJ (look in the output direction). (Movable)), and the state (b) results.

Next, step S4 of step S13A,
In S5, the worst critical path P1 is selected. In the branch processing of step S6A, the worst critical path P
Since the output end register R3 of No. 1 cannot move in the output direction, the process proceeds to Case 2, and steps S4, S5, S6A, S
7 and S10A, the output end register R2 of the path P1 is moved in the output direction until the path P1 is no longer the worst critical path, and the flags F11 to F13 of the blocks B1 to B3 straddled by the register R2 in step S14A. Is set to the information of “MOJ”, and as a result, the state of FIG.

Next, in steps S4 and S5, a new worst critical path P3 is selected. Step S6A
Since the output end register R2 of the worst critical path P3 cannot move in the output direction, the process proceeds to Case 2 at step S7.
1 in the output direction, and in step S10A, register R
"MOJ" is set in the flag F11 of the block B1 straddled by 1
Is set, and the state of (d) is set. In step S4, it is confirmed that the critical path has been resolved, and the process is terminated.

[0065]

As described above, the delay optimizing method and the logic synthesizing apparatus according to the present invention indicate the movable direction to each of the registers or each of the blocks in the data structure describing the logic circuit to be delay-optimized. By adding a flag, and giving priority to the path whose one end point is an input terminal or an output terminal, there is an effect that the calculation time until the completion of register movement can be significantly reduced as compared with the conventional case.

Further, as described above, since the register or the block has the restriction flag of the direction in which the register can be moved, it is not necessary to search for the redundant register movement, so that the entire calculation time can be further reduced. .

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a delay optimizing method according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a data structure of a logic circuit to which the present embodiment is applied;

FIG. 3 is an operation explanatory diagram showing a process of delay optimization by the delay optimization method of the embodiment.

FIG. 4 is a block diagram showing a logic synthesizer according to a second embodiment of the present invention.

FIG. 5 is an operation explanatory diagram showing a flow of processing in the embodiment.

FIG. 6 is a flowchart illustrating a delay optimizing method according to a third embodiment of the present invention;

FIG. 7 is a block diagram illustrating a data structure of a logic circuit to which the present embodiment is applied;

FIG. 8 is an operation explanatory diagram showing a process of delay optimization by the delay optimization method of the embodiment.

FIG. 9 is a flowchart showing a conventional delay optimization method.

FIG. 10 is an operation explanatory diagram showing a process of delay optimization by a conventional delay optimization method.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Library input unit 2 Circuit input unit 3 Constraint condition input unit 4 Logic optimization unit 5 Technology mapping unit 6 Delay optimization unit 7 Storage unit 8 Circuit output unit 11 Technology library 12, 14 Circuit description 13 Constraint condition 61 Flag addition unit 62 Optimization processing unit B1 to B7 Block F1 to F3, F11 to F17 Flag P1 to P3 Path R1 to R3 Register T1 to T3 terminal

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naotaka Maeda 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (56) References JP-A-3-238555 (JP, A) JP-A-6 −243195 (JP, A)

Claims (4)

(57) [Claims] 1. A signal path that starts at one of an input terminal or a register and ends at one of an output terminal or a register via a block composed of a combination of a plurality of logic circuits, and exceeds a predetermined allowable maximum delay value. Moving the register of the input or output end of the first path of the sequential circuit including the first and non-exceeding second paths across the block reduces the maximum delay of this first path. A delay optimizing method for equalizing the distribution of delay between the first and second paths and realizing a circuit operation in a faster clock cycle, wherein each of the registers in a data structure describing the logic circuit is provided. Alternatively, a flag indicating a movable direction is added to each of the blocks, and one end point is an input terminal or an output terminal, and the other end point is the register. It said first detecting path delay optimizing method characterized by the determination of the first of said selection of the mobile target register to the moving direction of the path be effected in accordance with the information of the flag that. Wherein each of said registers comprising said flag, to the second information and output direction indicated only movably to the first information and the input direction shows the no information of each said flag in direction only limited Holding any one of the movable third information and an initial value indicating a movable direction in which the first information is the first information; an input terminal or an output terminal as one end point; A first step of detecting a certain first path; and, when an output terminal of the first path is the output terminal, the first register which is the register of the input terminal is replaced with the first register.
In the output direction across the first block, which is the block directly connected to the output terminal of the register, the second register, which is the register at the output end when the input terminal is the input terminal, this by moving to the input direction across the second block is directly connected to said block to the input terminal of the second register first
A second step of reducing the maximum delay of the path of the second step, and when the register moved in the second step is the first register, the third flag corresponding to the first register is added to the third flag. If information is stored in the second register, the second flag corresponding to the second register is stored in the second flag.
A third step of setting the information of each of the first and second paths, and detecting the first path from all the paths, and exceeding the allowable maximum delay value of all the detected first paths most. A fourth step of selecting a third path that is present; and setting a third and a fourth flag of each of the third and fourth registers that are the registers at the input end and the output end of the third path. With reference to the information, execution of the movement of the third and fourth registers and resetting of the information of the third and fourth flags are performed by combining the first to third information of the third and fourth flags. 5. The method according to claim 1, further comprising the step of: Wherein each of said blocks comprising the flag, the fourth information and the output direction shown movably across only information of each said flag in the first information and the input direction shows the no direction restriction In this case, any one of the movable fifth information is held, and the initial value indicates the movable direction, which is the first information. A first step of detecting the first path which is the register; and, when an output terminal of the first path is the output terminal, the first register which is the register of the input terminal. 1
In the output direction across the first block, which is the block directly connected to the output terminal of the register, the second register, which is the register at the output end when the input terminal is the input terminal, this by moving to the input direction across the second block is directly connected to said block to the input terminal of the second register first
A second step of reducing the maximum delay of the path of the first block, and when the register moved in the second step is the first register, the fifth information is stored in a fifth flag of the first block. A sixth step of setting the fourth information to a sixth flag corresponding to the second block when the second register is the second register; and a step of setting the first path among all the paths. And selecting a third path that exceeds the allowable maximum delay value of all the detected first paths, and an input terminal and an output terminal of the third path. Of the seventh and eighth flags of the third and fourth blocks respectively corresponding to the third and fourth registers, which are the above-mentioned registers, respectively. First, fourth and fifth information The combination of these 3
2. The delay optimizing method according to claim 1, further comprising a seventh step of executing the movement of the fourth and fourth registers and resetting the information of the seventh and eighth flags. 4. A signal path which starts at one of an input terminal or a register and ends at one of an output terminal or a register via a block composed of a combination of a plurality of logic circuits, and exceeds a predetermined allowable maximum delay value. A library input unit for reading information of a technology library block including a logic and a delay value constituting a logic synthesis target circuit including a sequential circuit including a first path not exceeding and a second path not exceeding the second path; A circuit input unit for reading connection information of a circuit, a constraint input unit for reading a constraint condition including the allowable maximum delay value, and a logic optimization for optimizing a logic of a synthesis result of the read logic synthesis target circuit A technology mapping unit that allocates the technology library block to the logic synthesis target circuit; and an input terminal or output of the first path. Relocation by moving end registers across the block reduces the maximum delay of this first path, equalizes the distribution of delay between the first and second paths, and provides a faster clock cycle circuit. A logic optimizing device comprising a delay optimizing unit for realizing an operation, wherein the delay optimizing unit adds a flag indicating a movable direction to each of the registers or each of the blocks in the data structure of the technology library block A logic synthesizing apparatus, comprising: a flag adding unit that performs a selection of the register to be moved in the first path and a determination of the moving direction according to the information of the flag.