JPH04215130A - Instruction execution processing system for parallel pipeline instruction processing device - Google Patents

Abstract

PURPOSE:To improve the processing performance of a parallel pipeline instruction processing device by suppressing the increase of idle fields of a branch instruction block. CONSTITUTION:Plural instruction executing units are provided for the instruction execution processing of the parallel pipeline instruction processing device, and plural instructions are executed in parallel to prevent the occurrence of branch delay. When a conditional branch instruction exists in the branch instruction field of one instruction block consisting of plural instruction fields to be executed in parallel in instructions as the processing unit of this instruction processing device, an instruction execution selecting means (branch instruction executing unit) 6 selects whether each instruction other than the conditional branch instruction in this instruction block should be executed at the time of conditional branch or not. Since this means 6 is provided, the number of idle instruction fields in the instruction block including the conditional branch instruction is reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to an instruction execution selection processing method when executing a branch instruction in a parallel instruction processing apparatus that executes a plurality of instructions in parallel.

0002

[Prior Art] Conventionally, instruction pipeline processing and VLIW (VLIW) have been used as methods for improving the performance of computer systems.
Very Long Instruction W
There is a parallel pipeline instruction processing method that combines two processing methods: ord) type parallel instruction processing. To explain this processing method, we will explain instruction pipeline processing and VLIW
Type parallel instruction processing will be explained.

[0003] Instruction pipeline processing is a process in which instruction execution is divided into multiple stages, separate hardware units are provided for each stage, and each stage of instruction execution is executed in an overlapping manner. It is. If the execution time of each stage is the same and is equal to a machine cycle, a calculation result can be obtained every machine cycle. Therefore, in instruction pipeline processing,
Maximum performance is achieved when instructions and data are constantly supplied and there is no idle time at each stage.

One of the factors that disturbs this instruction pipeline processing is the execution of conditional branch instructions. It is not known until later in the pipeline whether the branch condition of a conditional branch instruction is satisfied or not. If the branch condition is satisfied, the instructions that have already been taken into the instruction pipeline have no effect, and the process must start over from the introduction of the branch destination instruction. In this way, when the branch condition is satisfied and the branch is executed, a delay occurs in the instruction pipeline processing (branch delay), and the overall processing performance deteriorates.

On the other hand, VLIW type parallel instruction processing is a process in which a relatively long instruction (hereinafter referred to as an instruction block) consisting of multiple instruction fields is processed as one instruction.
This is a process in which each instruction field can independently control a large number of arithmetic units, registers, interconnection networks, memories, etc. In this VLIW type instruction processing method, those that can be operated in parallel are extracted from the source program at the time of compilation and synthesized into one instruction block. can be achieved. However, when the degree of parallelism of instructions is low, empty spaces occur in the instruction field, and processing performance deteriorates.

[0006] An instruction processing method that combines both the VLIW type parallel instruction processing and instruction pipeline processing described above is a parallel pipeline instruction processing method.

In this parallel pipeline instruction processing method,
By providing a field dedicated to branch instructions in the instruction format and separating the branch instruction processing unit from other instruction processing units, the processing speed of branch instructions is increased. Then, the branch instruction and other instructions are processed in parallel.

[0008] Since parallel processing of arithmetic instructions and load/store instructions has been realized so far, in reality,
It is a processing system that can process three units in parallel: a processing unit for arithmetic instructions, a processing unit for load and store instructions, and a processing unit for branch instructions.

By adding a unit dedicated to branch instruction processing, conditional branch instructions are executed at high speed, and even if a conditional branch occurs, there is no delay due to the branch, and the flow of instruction pipeline processing is not disturbed. . Further, in order to control independent instruction processing units in parallel, a VLIW type instruction is adopted as an instruction format, which is composed of a plurality of instruction fields for controlling each instruction unit.

The performance of a parallel instruction processing device having this parallel pipeline instruction processing method depends on how many instruction functions can be embedded in one instruction block. There are two methods for optimizing programs: local optimization and global optimization.Currently, the basic arithmetic operation sequence has no branch operations except for the exit, and there are no branch operations except for the entrance. Focusing on sequences that are never branched from the outside (hereinafter referred to as basic blocks), local optimization examines data dependencies within each basic block, detects basic arithmetic operations that can be executed in parallel, and VLIW
It is an optimization that is synthesized as type instructions, and global optimization is an optimization that involves moving basic arithmetic operations between basic blocks. However, in a parallel instruction processing device using a parallel pipeline instruction processing method, there are a large number of conditional branch instructions and the basic block length is short, so that these optimizations do not produce a large effect.

Conventionally, in parallel instruction processing devices having this parallel pipeline instruction processing method, an optimization method called a trace scheduling method is particularly effective when conditional branches are highly biased (in applications such as chemical engineering calculations). is used.

FIGS. 21 and 22 are schematic diagrams showing an overview of the trace scheduling method.

The boxed area in FIGS. 21(a) to 21(d) is a basic block, in which basic operation instructions are arranged. FIG. 21(a) shows the flow structure of a certain program, and the optimization procedure in this case is as follows.

Step 1: Analyze the flow graph in FIG. 21(a) using data such as sample program execution, and find paths that are executed with a high probability (hereinafter referred to as traces).
Find. Here, the path shown by the diagonal line in FIG. 21(b) is assumed to be a trace.

Step 2: Paying attention to the data dependencies within the trace found in Step 1, detect arithmetic operations that can be executed in parallel, synthesize them as sequential VLIW instructions, and perform intra-trace optimization (Fig. 21(c)). In this process, basic arithmetic instruction operations existing in the trace are moved.

Step 3: As the basic operation instruction moves within the trace, the code outside the trace is modified as shown in FIG. 21(d). In the figure, blocks indicated by R are blocks added at confluence points, and blocks indicated by S are blocks added at branch points.

Step 4: Repeat the above steps for the non-trace code modified in Step 3.

[0018] Here, the modification of code outside of tracing in step 3 will be explained.

FIG. 22(a) shows processing at a confluence point. By moving the code on the trace in step 2, m11, m1
2, m13, m31, m32, m33, m34 (Fig. 22
(a) x1) is m11, m12, m32, m33,
Suppose that the values are m13, m31, and m34 (x2 in FIG. 22(a)). At this time, the new merging point is determined to be a point where there is no "arithmetic operation on the trace upstream of the old merging point" downstream, and in this figure, the series A merges at the new merging point m31. However, since processes m32 and m33 that were downstream of the old confluence point have been moved upstream of the new confluence point, processes m32 and m33 will not be executed on the path from series A if this continues. Therefore, processes m32 and m33 (x3) are added to series A.

On the other hand, at a branch point, the processing is as shown in FIG. 22(b). By moving the code on the trace in step 2, m11, m12, m13, m14, m21, m22,
m23 (Fig. 22(b) x4) is m11, m13, m1
4, m12, m21, m22, m23 (Fig. 22(b) x
5). Although it is the same as the new branch point m14, the process m12 that was upstream of the branch point has been moved to the downstream of the new branch point, so if it continues as it is, the path of series B will
will not be executed. Therefore, process m1 for series B.
2(x6) is added.

[0021]

In the parallel pipeline processing system described above, instructions other than the branch instruction in the instruction block containing the conditional branch instruction are executed regardless of whether the branch condition is satisfied or not. Therefore, as instructions other than branch instructions in an instruction block containing conditional branch instructions, it is necessary to extract and embed instructions that can be executed regardless of whether the branch condition is met or not.

For example, a VLI with four instruction processing units of the instruction pipeline system arranged in parallel and four fields is constructed.
Consider a parallel pipeline instruction processing device that executes W-type instructions. One of the stages of this parallel pipeline is a branch instruction-only stage that executes only branch instructions, and is a parallel pipeline instruction processing device that does not cause delays due to conditional branches.

In this case, there are three instruction fields other than the conditional branch instruction in the instruction block containing the conditional branch instruction, and it is necessary to embed instructions that can be executed regardless of whether the branch condition is satisfied or not in these three fields. be. However, if an executable instruction cannot be embedded, up to three empty fields will be created.

[0024] In a delayed branch mechanism in a non-parallel instruction pipeline, even embedding one valid instruction in the instruction slot immediately after a branch instruction has a rate of about 80 to 90% even when using the current state-of-the-art compiler technology. It has become. Considering this, instruction scheduling in which executable instructions are embedded in the three instruction fields of an instruction block containing conditional branch instructions in a parallel pipeline processing device is extremely difficult, and it is necessary to embed NOP instructions in most parts. It will stop happening.

Therefore, even in a parallel pipeline instruction processing device that does not cause delays due to branches, the number of empty instruction fields increases in instruction blocks containing conditional branch instructions, resulting in a significant drop in processing performance when executing instruction blocks containing conditional branch instructions. There is a problem with that.

Furthermore, as described above, the trace scheduling method is optimized for basic arithmetic operations on long traces. Therefore, although the effect is great, on the other hand, there is a drawback that the code size of the generated program becomes very large because blocks are frequently copied. In addition, instructions that can be executed must be embedded in the other instruction fields of the instruction block including the conditional branch instruction of the VLIW instruction to be synthesized, regardless of whether the branch condition is satisfied or not.

However, in a delayed branch mechanism in a non-parallel instruction pipeline, even embedding one valid instruction in the instruction slot immediately after a branch instruction has a rate of about 80% to 90% with current state-of-the-art compiler technology. Therefore, instruction scheduling that embeds and utilizes instructions in multiple fields other than this branch instruction is extremely difficult, and it ends up embedding NOP instructions in most fields, leaving empty instruction fields in the instruction block containing the conditional branch instruction. This causes a problem in that processing performance is significantly degraded when executing an instruction block containing conditional branch instructions.

An object of the present invention is to provide an instruction execution selection function for instructions other than conditional branches in an instruction block containing conditional branch instructions, which makes it possible to select instruction execution depending on whether a branch condition is met or not. An object of the present invention is to provide an instruction processing method for a parallel pipeline instruction processing device that prevents an increase in empty instruction fields in an instruction block including a conditional branch instruction and improves processing performance.

Another object of the present invention is to provide an instruction processing method for a parallel pipeline instruction processing device that can generate effective code using execution selection processing, thereby reducing loop execution processing time and improving processing performance. Our goal is to provide the following.

[0030]

[Means for Solving the Problems] The configuration of the present invention provides a parallel pipeline instruction processing device that is equipped with a plurality of instruction execution units and executes a plurality of instructions in parallel to avoid branch delays. In the execution processing method, if there is a conditional branch instruction in the branch instruction field of one instruction block that is composed of multiple instruction fields that are executed in parallel with instructions that are the processing unit of this instruction processing device, the conditional branch of that instruction block For each instruction other than the instruction, an instruction execution selection means is provided to select whether or not to execute the instruction at the time of conditional branching, thereby reducing the number of empty instruction fields in the instruction block containing the conditional branching instruction.

In the present invention, if the number of instructions excluding the number of free instruction fields of the header block of the loop is smaller than the number of free fields of the Taylor block in a natural loop in which instruction blocks are connected, the header block Move the instruction of the entry block of the header block to a free field of the Taylor block, copy the instruction of the entry block of this moved header block to a new basic block, and copy the entry block of the header block to the empty field of the Taylor block.
By reorganizing this loop by removing it from blocks, the number of instruction blocks within the loop can be reduced and the code optimized.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a parallel pipeline instruction processing device according to an embodiment of the present invention when instruction blocks are executed.

The instruction string fetch means 2 fetches the instruction block specified by the address bus 32 from the instruction block memory 1 via the instruction block bus 31. Instruction (1), instruction (2), instruction (3) shown in FIG.
and branch instructions are transferred to instruction execution units 3 to 5 and branch instruction execution unit 6 via instruction buses 33 to 36, respectively. Each instruction execution unit 3~
5 decodes each transferred instruction and sends the operands used in each instruction to register read buses 37 to 40, respectively.
from data register 7 via . Then, each instruction is executed, and the instruction execution results are sent as data via the register write buses 49 to 52.
Write back to register 7.

On the other hand, the branch instruction execution unit 6 decodes the transferred branch instruction and generates a branch destination address. At the same time, the instruction block address held internally is incremented to generate the next address. Then, it refers to the operand given via the register read bus 40 to determine whether the branch condition is satisfied or not, and if a branch occurs, the branch destination address is determined, and if the branch does not occur, the next address is determined. address bus 3
Output to 2.

Furthermore, in the case of a branch instruction that simultaneously stores the next address in a register, that is, a branch and link instruction, the branch destination address is output to the address bus 32, and the next address is It is written back to data register 7 via register write bus 52. The fourth instruction execution unit of this parallel pipeline instruction processing device is dedicated to branch instructions, and can output the next address or branch destination address to the address bus without causing a delay due to conditional branching.

Now, the flow of a program sequence including a conditional branch instruction and an instruction with an execution selection function in the above-described parallel pipeline instruction processing device without branch delay will be explained.

The instructions in this parallel pipeline instruction processing device are an instruction block consisting of four instructions, as shown in FIG. Four instruction fields embedded in each instruction block are called field 1, field 2, field 3, and field 4 from the MSB side, and field 4 is a branch instruction field.

As shown in FIG. 3, the program sequence in this case is that there is no branch instruction in instruction block 1;
A NOP instruction is embedded in the instruction field 4. Therefore, this instruction block 1 is executed as is. In the instruction block 2, a conditional branch instruction is embedded in the instruction field 4. If the branch condition is met at this time, the program sequence moves to instruction block A. If the branch condition is not met, the sequence continues to the next instruction block 3. Therefore, instructions 4 to 6 are normally executed both when a branch instruction is established and when a branch instruction is not established.

Assume now that instruction block 2 in FIG. 3 is an instruction block as shown in FIG. In the instruction block of FIG. 4, instruction fields 1 and 3 contain logical shift instructions (lsl...Logical Shift Left
), an addition instruction is embedded in instruction field 2, and a conditional branch instruction (branch condition is satisfied when the value of register "r23" is "0") is embedded in instruction field 4.

Here, a "+" sign is added to the beginning of the addition instruction in instruction field 2. FIG. 5 is a schematic layout diagram of the object format of this addition instruction. This object code has a length of 32 bits, and the object code is embedded in each field of the operation code, source register 1, source register 2, and destination register. The 0th and 1st bits in FIG. 5 are instruction execution selection fields, which are used to select whether or not to execute an instruction depending on the condition of the conditional branch instruction in the instruction block.

In the case of the instruction block shown in FIG. 4, there is a conditional branch instruction in instruction field 4, and it is desired to execute the instruction in instruction field 2 only when the branch condition is satisfied. For this reason,
A “+” sign is added to the beginning of the instruction in field 2. At this time, the code "01" is filled in the instruction execution selection field of the object code. This results in
If the branch condition is met when this instruction block is executed, the instruction in instruction field 2 is executed, and if the condition is not met, this instruction is not executed.

On the other hand, if you want to execute an instruction only if the branch condition is not satisfied, write " at the beginning of the instruction.
-" symbol is added. At this time, the code "10" is filled in the instruction execution selection field of the object code. Also, if the instruction can be executed regardless of whether the branch condition is met or not, the instruction execution selection field of the object code is filled with the code "10". An instruction is written. At this time, a code "00" is embedded in the instruction execution selection field of the object code.

Next, the procedure for executing the instruction block shown in FIG. 4 will be explained.

The instruction block fetch means 12 fetches the instruction block specified by the address bus 32 from the instruction block memory 1 via the instruction block bus 31. Then, the instructions for each field in FIG. 4 (instruction 4
, instruction 5, instruction 6, branch instruction) are transferred to the operand fetch means 14-17 via instruction buses 33-36 and output. At this time, regarding the instruction field 2 in FIG. 4, since the instruction execution selection field is "+", the execution tip plus signal 53 is output to the instruction execution means 20. Regarding the other instruction fields, since the execution selection field is filled with the "00" code, no execution selection signal is output.

Next, the operand fetch means 14 to 17
decodes the transferred instruction and transfers the necessary operands from the data register 13 to the register read bus 37.
~40. For the above operation, please refer to 4.
The same is true for the three instruction execution units 3-5.

The address generating means 18 of the branch instruction execution unit 6 increments the internally held instruction block address and generates the next address. At the same time, the branch instruction provided via the instruction bus 36 is decoded and a branch destination address is generated. Then, it refers to the operand given via the source operand bus 41 to determine whether the branch condition is satisfied or not, and if a branch occurs, the branch destination address is determined, and if the branch does not occur, the next address is determined. Output to address bus 32.

If the branch condition is satisfied and a branch occurs, "1" of the branch condition satisfied signal 54 is output to the instruction execution means 19 to 21, and if the branch does not occur, the branch condition satisfied signal 54 is outputted to the instruction execution means 19 to 21. 54 "0"s are output. Then, the branch instruction is a branch that requires saving the next address.
If it is an AND link instruction, the branch destination address is output to the address bus 32, and the branch condition fulfillment signal “1” is output.
” is output, and at the same time, the next address is output to the operand write means 22 via the destination operand bus 45.
performs a register write with the next address as the operand.
Write to data register 13 via bus 52.

The instruction execution means 19 and 21 also execute the source code.
The instructions are executed using the operands transferred via operand buses 42 and 44, and the results are transferred to the operands via destination register buses 46 and 48.
The data is transferred to the write means 23 and 25. Operand write means 23 and 25 write each result operand to the register specified by each instruction via register write buses 49 and 51, respectively.

On the other hand, in the instruction execution means 20, the execution selection plus signal 53 is active. At this time, if both branch condition fulfillment signals 54 are active, the instruction execution means 20 executes the instruction using the operands transferred via the source operand bus 43, and stores the result in the destination register. The data is transferred to the operand write means 24 via the bus 47, and the operand write means 24 transfers the resulting operand to the register specified by the instruction via the register write bus 50.
Write to register 13.

However, if the branch condition fulfillment signal 54 is inactive, the execution selection plus signal 53 is active, so this instruction is not executed.
Both 4 do nothing.

In the above embodiment, the case where the instruction execution selection field is "+" has been explained, but when the instruction execution selection field is "-", the execution selection minus signal is similarly sent from the instruction block fetch means. It is output to the corresponding instruction execution means. At this time, if the branch condition satisfied signal is active, the instruction will not be executed, and if the branch condition satisfied signal is inactive, the instruction will be executed. This is summarized in Tables 1 and 2.

In the table showing the relationship between the instruction execution selection field and the execution selection signal 53 in Table 1, when the instruction execution selection field is "+", the instruction is executed only if the branch condition is satisfied; ”, the instruction is executed only if the branch condition is not satisfied. If nothing is specified in the instruction execution selection field, the instruction is executed regardless of whether the branch condition is met.

[0053]

Table 2 is a table showing the relationship between the values of the execution selection signal and branch condition fulfillment signal and the output of the result by the instruction execution means, and the fact that the result of the instruction execution means is not output means that the instruction is desired to be executed. is equivalent to

[0055]

As explained above, in this method, each instruction in a plurality of other instruction fields of an instruction block including a conditional branch instruction has an instruction whose execution can be selected depending on whether a branch condition is met or not. Since the execution selection function is provided, it is possible to embed an instruction to be executed only when a branch condition is met or not met in an instruction block containing a conditional branch instruction, and an increase in empty fields can be prevented.

In this VLIW type parallel instruction processing method, as an instruction parallelization method in which instructions are parallelized so that as many instructions as possible are embedded in one instruction block,
There are top aligned and middle aligned instruction parallelization methods.

In the top-aligned instruction parallelization method, instructions are embedded in order from the instruction block with the earliest execution cycle. That is, at first, as many instructions as possible are embedded in the instruction block of cycle 0, and when no more instructions can be embedded in the instruction block of cycle 0, instructions are then embedded in the instruction block of cycle 1. When the instruction block of cycle 1 can no longer be filled in, the instruction block of cycle 2, and so on.

Now, when embedding instructions in the instruction block of cycle n, the instructions that can be embedded in the instruction block of that cycle are called instructions in the data ready state.

[0060] An instruction in the data ready state here means that if there is an instruction that directly evaluates the operand data referenced by that instruction, that instruction is in the instruction block of the cycle before the current cycle. It means that it has already been placed. In other words, when the operand data to be handled has been evaluated in the previous cycle and the correct value has been set, the instruction can refer to the operand data for the first time, and can be said to be in a data ready state.

[0061] In this way, when executing a certain instruction, an instruction that has a data dependency with the operand handled by that instruction and must be executed in a cycle before that instruction is executed. It is called the former of the command,
An instruction that must be executed after or in the same cycle as the instruction is called the latter of the instruction. Therefore, an instruction in a data ready state is an instruction for which all former instructions have been placed.

In the top-align method, an instruction block is constructed by selecting instructions from among the instructions in the data ready state so that as many instructions as possible can be embedded in the instruction block. If there are many data-ready instructions that can be placed in the current cycle's instruction block, the top-align method places the instructions in the data-ready state in descending order of height. I will do it.

The height of this instruction is as follows within the basic block:
This is the number of cycles of the longest (longest cycle) path by tracing the latter of that instruction, then the latter, and so on until reaching an instruction that does not have the latter.

In such a top-align method, the instruction filling rate of the instruction field is relatively good in the instruction block near the entrance of the basic block, and the filling rate becomes worse as the instruction field gets closer to the exit of the basic block.

Next, the middle aligned instruction parallelization method will be explained.

In the middle-aligned instruction parallelization method, first, from among the heights of all instructions in a basic block, the value of the height of the highest instruction in the basic block is divided by 2, and this value is calculated. Use the basic height.

Here, the block in which an instruction with the basic height is placed first is designated as instruction block 0, and the instruction blocks executed before instruction block 0 are designated as minus blocks.
An instruction block executed after instruction block 0 is called a plus block. At this time, the instruction blocks to be filled with instructions are first instruction block 0, then instruction block 1 of the minus block, as shown in FIG.
, then instruction block 2 of the plus block, then instruction block 3 of the minus block, and so on.

In this middle alignment method, first, an instruction of the basic height is placed in the instruction block of cycle 0,
Based on the instructions placed here, as many instructions as possible are subsequently embedded in the instruction block as close as possible to the instruction block of cycle 0. The instruction blocks to be placed are minus blocks, plus blocks, as described above.
Blocks alternate.

Basically, an instruction block in a minus block contains an instruction whose height is 1 greater than the former instruction already placed in the block to be executed after that cycle. can be placed. If there are many instructions that can be placed in the minus block that is the placement target, the instructions are placed in order from those with the deepest instructions.

[0070] The depth of an instruction here refers to the longest path (the longest path) in a basic block, tracing instructions such as the former of that instruction, then the former of that instruction, and finally arriving at an instruction without the former. This refers to the number of cycles in a path (long cycle).

Similarly, in the instruction block of the plus block, place an instruction that is the latter of the instructions already placed in the block to be executed before that cycle, and whose depth is 1 greater than the already placed instructions. can do. If there are many instructions to be placed, the instructions are placed starting from the instruction with the highest height.

FIGS. 7A and 7B show examples of loop optimization performed using the instruction execution selection function. First, Figure 7 (
Consider a basic block of a program flow as shown in a). In the first instruction block of basic block 1, instructions valid only in instruction fields (1) and (2) are embedded. Assume that the final instruction block of basic block 2 has a conditional branch instruction embedded only in branch field (3). When the branch condition of the final instruction block of basic block 2 is satisfied, the program flow loops back to basic block 1.

At this time, the instruction execution selection function can be used to move the instruction as shown in FIG. 7(b). In other words,
Move instructions (1) and (2) embedded in the first instruction block of basic block 1 to the empty instruction field of the last block of basic block 2 with "+" attached, and move the instructions (1) and (2) embedded in the first instruction block of basic block 1 to delete. At the same time, a new basic block 0 is created and inserted immediately before basic block 1. By operating the above instructions, basic block 1
The number of instruction blocks in the program is reduced, and as a result, the number of clock cycles required for the loop can be reduced without changing the meaning of the program. In order to perform optimization using such an instruction execution selection function, it is desirable that the first block and the last block of basic blocks have as many as three empty fields.

In this case, if the number of instructions embedded in the first instruction block of basic block 1 is greater than the number of empty instruction fields in the last instruction block of basic block 2, all of the first instruction blocks of basic block 1 are cannot be moved to basic block 2, the number of instruction blocks in basic block 1 cannot be reduced, and optimization cannot be performed. Therefore, in order to effectively perform optimization using this instruction execution selection function, it is necessary to
It is preferable to parallelize using the middle alignment method rather than the alignment method.

Let us now consider the case where the final instruction of the basic block to be parallelized is not a branch instruction. At this time, instructions will not be moved from other basic blocks to the final instruction block of the basic block with "+" or "-" attached, and there is no need for the final instruction block to have many empty instruction fields. Conversely, an instruction placed in the first instruction block of that basic block may be moved to a basic block executed before that basic block with "+" or "-" attached. Therefore, if the final instruction of the basic block is not a branch instruction, optimization using the instruction execution selection function is better if the first block of the basic block is parallelized so that there are more free instruction fields. It becomes easier to do.

In this conventional middle-aligned parallelization method, depending on the number of instructions in a basic block and the data dependencies of each instruction, there may be more free instruction fields in the last block than in the first block. . if,
Consider a case where a certain basic block does not include branch instructions, has seven instructions, and has no data dependencies at all between the instructions. At this time, if the instructions are arranged in the order of base block, minus block, and plus block, the empty field for instructions increases in the final instruction block as shown in Table 3 (a), and the base block, plus block , minus block, the number of empty instruction fields increases in the first instruction block as shown in Figure 3(b).

[0077]

In this way, in the middle alignment method, depending on the number of instructions in a basic block and the data dependencies between each instruction, even if it is known that a basic block does not contain a branch instruction, , it is difficult to arrange so as to increase the number of empty instruction fields in the first instruction block.

In other words, even in the conventional middle-aligned instruction parallelization method, when parallelizing basic blocks that do not include branch instructions, optimization using the instruction execution selection function may be effective in some cases. It may not be done.

FIG. 8 is a flowchart illustrating a second embodiment of the present invention. In this embodiment, four instruction processing units using an instruction pipeline system are arranged in parallel, and all instructions are processed in one
This is the case of a VLIW type parallel pipeline processing device that can be executed by a clock, and one of the stages of the instruction pipeline is a branch instruction-only stage that executes only branch instructions, so there is no delay due to conditional branches, and the result is Assume that all instructions can be executed in one clock.

In step S1 of FIG. 8, it is checked whether the final instruction of the basic block to be parallelized is a branch instruction. Here, if the final instruction is a branch instruction,
This block is parallelized using the middle alignment method in step S2. If the final instruction is not a branch instruction, step S is executed for this block.
Parallelization is performed using the bottom alignment method in step 3.

FIGS. 9 and 10 show flow charts for the middle align parallelization method and the bottom align parallelization method of FIG. 8.

First, the middle align method will be briefly explained according to the flow chart of FIG. Here, Table 4 shows the sequence of instruction statements corresponding to the basic block, Table 5 shows the height and depth of each instruction in Table 4, and Table 5 shows the former and latter instructions of each instruction and the data dependence relationship between the two instructions. 6.

[0084]

[0085]

[0086]

[0087] Here, the types of data dependencies are as follows:
The following three types are considered.

1. The data written by the former instruction connected by the WR (Write-Read) side is referenced by the latter instruction.

2. Instructions connected by the RW (Read-Write) side The latter instruction writes data referenced by the former instruction.

3. Instructions connected by the WW (Write-Write) side The latter instruction also writes data to the data written by the former instruction.

In the case of instructions connected by the WR side or the WW side, the latter instruction must always be executed after the clock following the former instruction. However, in the case of instructions connected on the RW side, the latter instruction only needs to be executed at the same clock as the former instruction or at a later time.

In step S11 of FIG. 9, a basic height is determined from among the heights of all instructions in the basic block. This is the value obtained by dividing the height of the highest instruction in the basic block by 2 (rounding up the decimal point). Table 4
For the basic block, the basic height will be 3 (see Table 5).

From now on, the block in which an instruction with the basic height is placed first is defined as the base block, and the instruction block executed before the base block is defined as the minus block, and the block executed after the base block is defined as the base block. This block is called a plus block. At this time, the instruction blocks to be filled with instructions are, as shown in FIG. 6, first the base block instruction block 0, then the minus block instruction block 1, and then the plus block instruction block 2. , then instruction block 3 of the minus block, and so on.

Next, in step S12, since the last instruction of the basic block in Table 4 is a branch instruction, statement 9 of the branch instruction is saved. Since a branch instruction must be executed in the last instruction block of its basic block, by saving it, it is removed from the target of subsequent placement logic.

Then, in step S13, instructions are placed in block 0 of the base block. Step S1
Instructions that can be placed in the base block in step 3 are those that meet the following three conditions.

(1) Instructions that have a basic height (2) Instructions that are connected to already placed instructions by the RW side and have no dependency relationship with other placed instructions (3) Basic height An instruction that has the following height and all ancestors have not been placed yet: When placing this instruction, place all instructions that fall under (1), and if there is an empty instruction field ( Place all instructions corresponding to 2), and when there is an empty instruction field (
Arrange the instructions corresponding to 3). Also, (1) (2
) (3) If there are multiple instructions that meet each condition, the instructions with the deepest depth are placed first.

In the basic block of Table 5, first, the command sentences (5) and (6
) are placed in the base block in the order of instruction depth (6) and (5). Furthermore, an instruction (2) that satisfies the condition (2) is placed. At this point, there is no longer an empty instruction field in which to place instructions other than branch instructions, so the placement in block 0 is completed. The arrangement state of the instruction blocks at this time is as shown in Table 7(a). Furthermore, since there are still unplaced instructions remaining in step S14, the process advances to step S15.

[0098]

The instructions that can be placed in the minus block in step S15 are unplaced instructions that meet the following four conditions.

(1) An instruction with a basic height (2) An instruction placed in an instruction block to be executed after the next block, whose height is (height of the latter instruction + 1)
(3) An instruction that is connected to an instruction already placed in the current block by the RW side, and is not the former instruction of other instructions in that block (4) An instruction that has a height less than or equal to the basic height, In addition, when placing instructions whose ancestors have not yet been placed, place all instructions that fall under (1), and place all instructions that fall under (2) if there is an empty instruction field. , when there are more empty instruction fields (3
), and when there is an empty instruction field, an instruction corresponding to (4) is placed. Also,
If there are multiple instructions that apply to each condition,
Place the commands with the deepest commands first.

In the basic block of Table 4, first, there are no unplaced instructions that meet condition (1), and instructions (1) and (4) that meet condition (2) are sorted in descending order of instruction depth. (4) and (1) are placed in instruction block 1. There are still empty instruction fields in instruction block 1, but (3)
Since there is no instruction that satisfies the condition (4), instruction allocation to instruction block 1 is completed. The arrangement state of the instruction blocks at this time is as shown in Table 7(b). Further step S
At step 16, there are still unplaced instructions, so the process proceeds to step 7. The instructions that can be placed in the plus block in step S17 are unplaced instructions that meet the following four conditions.

(1) Instructions that have the basic height (2) Instructions that are the latter of the instructions placed in the instruction block that is executed before the previous block and whose depth is (depth of the former instruction + 1) ( 3) The latter instruction is connected to the instruction already placed in the current block by the RW side, and is not the latter instruction of other instructions in that block. (4) The instruction has a height less than or equal to the basic height, and all When placing instructions whose ancestors have already been placed, place all instructions that fall under (1), and if there is an empty instruction field, place all instructions that fall under (2), and then place all instructions that fall under (2), and then place all instructions that fall under (2), and then When there is a free instruction field, an instruction corresponding to (3) is placed, and when there is an empty instruction field, an instruction corresponding to (4) is placed. In addition, if there are multiple instructions that meet each condition, (2), (3), and (4)
), the instructions with the highest height are placed first, and regarding (1), the instructions with the deepest instructions are placed first.

In the basic block of Table 4, there are no unplaced instructions that meet condition (1), and instructions (7) and (8) that meet condition (2) are placed in instruction block 2. Although there is still a vacant instruction field in instruction block 2, there is no instruction that satisfies the conditions (3) and (4), so instruction placement in instruction block 2 is completed. The arrangement state of the instruction blocks at this time is as shown in Table 7(c). Further, in step S18, since there are still unplaced instructions, the process proceeds to step S15.

In step S15, the instruction is placed in instruction block 3 because it satisfies the conditions of instructions (3) and (2), which are not placed in the basic block of Table 4. At this point, the instruction block arrangement state is as shown in Table 7(d). And step S1
6, there are no unplaced instructions, so the process advances to step S19.

In step S19, the evacuated instruction (9) is placed in an appropriate location. If the instruction that has been saved is not the latter of the instructions placed in the final block at that time, the instruction is placed in the branch instruction field of the final block at that time. However, if it is the latter of the instructions placed in the final block, a new instruction block is added as the final block, and the branch instruction is placed in the branch instruction field of that instruction block.

In the case of the basic block in Table 4, instruction (9) is the latter of the instructions placed in the final block at this point, so a new instruction block is added and instruction (9) is placed in the branch instruction field. Place. At this point, the parallelization process is finished, and the arranged instruction blocks are shown in Table 7 (
e).

Next, the bottom align parallelization method will be explained according to the flow chart of FIG. In explaining the bottom-align parallelization method, Table 8 shows
Table 9 shows the sequence of instruction sentences corresponding to a certain basic block, the height and depth of each instruction in Table 8, and Table 10 shows the data dependence of the two instructions corresponding to the former and latter of each instruction.

[0108]

[0109]

[0110]

Note that in the bottom aligned parallelization method,
Instructions are embedded in order starting from the instruction block with the slowest execution cycle. In other words, the instruction block of the last cycle is set as instruction block 0, and as many instructions as possible are placed in instruction block 0. When no more instructions can be filled, the next instruction is placed in instruction block 1 of the previous cycle. Place. When no more instructions can be placed in instruction block 1, the instruction block of the previous cycle is next, and so on.

First, in step S21 in FIG. 10, instructions without the latter are placed in instruction block 0 in descending order of instruction depth. In the case of Table 8, instructions (3) (4) (
6) and (7) are instructions without the latter (Table 10). From among these, instructions are placed in instruction block 0 in descending order of depth. As shown in Table 9, the instruction depth is (3),
(4) is the same at depth 1, but (6) is 2 and (7) is 3. Therefore, instructions (7) (6) are placed in instruction block 0.
When (1) is placed, there are no empty fields for instructions. Therefore, the process advances from step S22 to step S25. At this point, there are still unplaced instructions, so in step S26 the instruction placement in the current target block, instruction block 0, is finished, the placement target is changed to the next instruction block 1, and the process proceeds to step 1. At this time, the arrangement state of the instruction blocks is as shown in Table 11(a).

[0113]

[0114] In step S21, the instructions without the latter or with the latter placed are instructions (2) to (5).
It is. When these instructions are arranged in order of instruction depth, instructions (5), (2), and (3) are arranged in instruction block 1. At this point, there are no more empty instruction fields, so the process advances from step S22 to step S25, and since instruction (4) has not been placed, the process proceeds to step S26, where instruction placement in instruction block 1 is completed and the next instruction block 2 is the placement target. Change. At this time, the arrangement state of the instruction block is shown in Table 11(b).
become that way.

Further, in step S21, the latter instruction (4), all of which have been placed, is placed in the instruction block 2. In step S21, there are still empty instruction fields, but since there are no instructions remaining that have not been placed in step S23, the placement of all instructions is completed at this point. The final arrangement of instructions is as shown in Table 11(c). Note that when the basic block instructions in Table 8 are parallelized using the middle aligned instruction parallelization method, the results are as shown in Table 12. It is clear that compared to the bottom-aligned instruction parallelization method, there are fewer empty instruction fields in the first instruction block of the basic block.

[0116]

The pipeline instruction processing device having this parallel instruction execution selection processing method is a method for solving the problem during code generation of the parallel pipeline instruction processing device. Optimized code that effectively utilizes the processing method cannot be generated. In order to optimize code that is effective for such a pipeline instruction processing device, it is necessary to generate code that is effective for loops in which most of the program execution time is spent.

FIGS. 11 and 12 are flowcharts for explaining the code optimization method and its loop optimization section according to the third embodiment of the present invention. FIGS. FIG. 4 is a program sequence diagram before and after optimization in a line instruction processing device. This embodiment also uses a pipeline instruction processing device having the parallel instruction execution selection processing method shown in FIG. Note that here it is assumed that the program has already been subjected to local optimization and global optimization obtained with current optimizing compiler technology, so the program in Figure 13 is designed to move the invariant code inside the loop out of the loop. This shows the program sequence after optimization, which is optimized for the following variables and induced variables (variables that change by a constant value as the loop repeats).

In FIG. 11, "basic block division" is performed in step 101. What is this "basic block"?
It is a series of basic arithmetic operations that are executed one by one in order from the first instruction to the last instruction. If a branch instruction exists in the branch field, the basic block is cut off, so there is no branch instruction in the middle, and the "entrance of the basic block" is the first instruction block of the basic block, and the "exit of the basic block" is the last instruction block of the basic block. Become. To simplify the explanation, it is assumed that each instruction of the program is arranged so as to increase the free fields of the instruction blocks at the entrance and exit of the basic block as much as possible.

The next step 102 is "flow analysis", in which label definition/reference relationships are analyzed to determine the flow between basic blocks. This flow of control is indicated by "former" and "latter", and when the flow of control moves from basic block A to basic block B (this is written as "basic block A → basic block B"), the basic block A is the former of basic block B, and basic block B is the latter of basic block A.

In the next step 103, "depth priority order calculation" is performed. This "depth-first order" is the result of exploring a program by starting with the first basic block in the program and visiting basic blocks as quickly as possible away from the first basic block (depth-first).
It is a sequence of all basic blocks of a program.

[0122] In the next step 104, "Detection of ruler"
I do. This "ruler" is a basic block that is always executed before each basic block is executed.

In the next step 105, "construction of a natural loop" is performed. This "natural loop" means that on the opposite side "A → B" (the side "A → B" where basic block B dominates basic block A), it is possible to reach A without passing through B. This is an arrangement of basic blocks that includes basic blocks plus A and B. Basic block B is called the header block of this natural loop, and basic block A is called the Taylor block.

[0124] In the next step 106, "analysis of living variables" is performed. register a and a point p in the program
, we analyze whether the value of register a at point p can be used within a certain path starting from point p. If it can be used, it is said to be "alive," and if it cannot be used, register a at point p is said to be "dead." The purpose of live variable analysis is to find the set of live variables at the exit of each basic block.

Further, in step 107, "loop optimization" is performed. Here, code optimization is performed on each natural loop constructed in step 105 to generate a code that is effective for a pipeline instruction processing device having a parallel instruction execution selection processing method. Shorten the length of the loop (the number of instruction blocks that make up the loop) and shorten the time required to execute the loop.

In the loop optimization section of step 107 in FIG. 12, steps 111 to 113 perform "pre-determination as to whether loop optimization is possible."

First, in step 111, the number y of empty fields at the exit of the Taylor block is determined.

[0128] In the next step 112, step 111
Determine whether optimization is possible based on the value of y found in
If the number of empty fields y=0, optimization is not possible and the process ends.

In the next step 113, it is determined whether optimization is possible based on the register definition/reference data of the instruction block at the entrance of the header block and the instruction block at the exit of the tailor block. If a register defined or referenced in the instruction block at the entrance of the header block is defined in the instruction block at the exit of the Taylor block (if there is a definition/reference dependency), optimization cannot be performed and the process ends. do.

Steps 114 to 119 show actual optimization processing.

First, in step 114, the number x of instructions in the instruction block at the entrance of the header block is calculated, and in the next step 115, among the instructions [number of instructions x] of the instruction block at the entrance of the header block, the number of instructions in the instruction block The number of instructions [z] that can be moved without using execution selection processing and the empty instruction field m that can be moved are determined. An instruction whose defining register is not included in the live variables at the exit of the header block is a movable instruction. In addition, the free instruction field of the instruction block where the register defined by the movable instruction is referenced, and the instruction block after that instruction block and the instruction block after the instruction block where the referenced register is referenced, is the free instruction field that can be moved. be.

In the next step 116, x(step 1
14) and y (step 111), z (step 115)
Determine whether optimization is possible based on the value of (x-z)
If >y, optimization cannot be performed and the process ends.

The next steps 117-119 illustrate moving/copying the code and reconfiguring the loop. First, in step 117, the instruction in the instruction block at the entrance of the header block counted as z (step 115) is moved to the empty field m of the tailor block. Further, the instructions in the instruction block at the entrance of the header block that are not listed in z are moved to the empty field at the exit of the Taylor block with execution selection processing [+] attached.

Next, in step 118, a new basic block is generated, and in step 117, the instructions in the instruction block at the entrance of the header block moved are copied.

Finally, in step 119, the loop is reconfigured. Specifically, the instruction block at the head of the header block is deleted from the header block. As a result, the length of the loop (the number of instruction blocks forming the loop) is shortened by one instruction block. In addition, the following flow information and branch destination changes are performed.

a) The former header block is combined with the Taylor block and the new basic block F generated in step 118
shall be.

b) The latter of the basic blocks is a header block in addition to the Taylor block.The latter of the basic blocks can be changed from the header block to the new basic block F in step 118.

c) If the branch destination of the basic block whose latter was changed in b) is a header block, the branch destination is changed to the new basic block in step 118.

d) Make the former of the new basic blocks in step 118 all the basic blocks whose latter were changed in b).

e) Make the latter of the new basic blocks of step 118 a header block.

When the program sequence shown in FIG. 13 is optimized, the program sequence shown in FIG. 14 is obtained. Assuming that a natural loop with opposite sides "E→B" can be optimized, first calculate the number of instructions in step 117 for the instructions in the instruction block at the entrance of header block B consisting of instructions 5 to 7. Move the instruction 6 counted by z into Taylor block E, and move the remaining instructions (
Instructions 5 and 7) are moved to the exit instruction block of Taylor block E with execution selection processing [+] attached. Next, in step 118, a basic block F having one instruction block consisting of instructions 5 to 7 is generated.

Finally, in step 119, the loop is reconfigured and the instruction block at the beginning of header block B (instruction 5
, instruction 6, instruction 7, NOP) are deleted from the header block, and the flow is changed to the one shown in FIG.

In this case, the instruction block at the beginning of header block B (instructions 5 to NOP) is deleted from the loop and becomes shorter by one instruction block, so the repeated instruction processing time in the loop of basic blocks B to F is shortened. It turns out.

FIGS. 15 and 16 are flowcharts of a fourth embodiment of the present invention. The third embodiment shows the case of a "natural loop", but this embodiment shows the case of no branching. In addition, FIGS. 17 to 20 show a program for a pipeline instruction processing device having a parallel instruction execution selection processing method.
This is an example of code optimization of this embodiment for a sequence. In each case of FIGS. 17 to 20, (a) is the program sequence before optimization of this embodiment, (
b) is the program sequence after optimization. It is assumed here that the program (a) has already been subjected to local optimization and global optimization provided by current optimizing compiler technology.

In FIG. 15, the difference from the third embodiment is that step 106 is not provided, and steps 102a and 1
07a has been changed.

Step 102a is a "flow analysis" in which label definition/reference relationships are analyzed to determine the flow of control between basic blocks. The control flow is indicated by "former", "latter", and "edge type (branch taken edge, branch not taken edge, or function call edge)". An edge where control is transferred from the former to the latter is a branch taken edge, an edge where there is a function call instruction in the branch field of the former and control is transferred to the latter after returning from the function is a function call edge, and other edges are called edges. is the branch failure edge. Step 102a classifies all control flows between basic blocks by edge type.

Step 107a is "code optimization". From the result of the flow analysis in step 102a, edges with no branch taken are extracted and code optimization is applied to each edge with no branch taken, thereby shortening the execution time of the flow where the branch is not taken. FIG. 16 shows a detailed flow of code optimization in step 107a. The branch unsatisfied component to be optimized is edge 'A
→B' (A: former block, B: latter block).

Steps 110 to 113 are "pre-determination as to whether optimization is possible". Step 110
Now, it is determined whether optimization is possible based on the number of instruction blocks of basic block B, which is the latter of the branches not taken, and information on the branch field of basic block B. Optimization cannot be performed if the following condition (described as condition α in FIG. 16) is satisfied.

Conditions 1) [Basic block B=1 instruction block] 2)
[There is a branch instruction in the branch field of basic block B] In step 111, the number y of empty fields at the exit of basic block A, which is the former branch failure edge, is determined. In step 112, depending on the value of y obtained in step 111,
Determine whether optimization is possible. [Number of empty fields y
=0], optimization cannot be performed and the process ends.

In the next step 113, basic block B
It is determined whether optimization is possible based on register definition/reference data of the instruction block at the entrance of basic block A and the instruction block at the exit of basic block A. If a register defined or referenced in the instruction block at the entrance of basic block B is defined in the instruction block at the exit of basic block A (if there is a definition/reference dependency), optimization cannot be performed and the process ends. becomes.

Steps 114 to 119a are actual optimization processing. First, in step 114, the number x of instructions in the input instruction block of basic block B is determined.

In step 115, among the instructions [number of instructions x] of the instruction block at the entrance of basic block B, an instruction [number of instructions x] that can be moved to basic block A without using execution selection processing [-] is selected.
The number of instructions z] and the movable empty field m are determined. Among the instructions in the instruction block at the entrance of the basic block B, those instructions whose registers are not included in the living variables at the exit of the latter block B are movable. Also,
Free fields of instruction blocks in which registers defined by movable instructions are referenced in basic block A, and instruction blocks subsequent to the instruction blocks and subsequent to instruction blocks in which referenced registers are defined, are free fields that can be moved. It is.

In step 116, x (step 114
), y (step 111), and z (step 115), it is determined whether optimization is possible. [(x-z)
>y], optimization is not possible and the process ends.

Step 117a is moving/copying code and changing program flow. First, in step 117a, the instruction in the instruction block at the entrance of basic block B is moved to basic block A (former block) as a count of z (step 115). The place to move is empty field m. The instructions in the input instruction block of the latter block B that are not listed in z are moved to the empty field at the exit of the former block A with an execution selection process [-] attached (step 117a). If there is no branch that takes basic block A as the former, all the instructions in the instruction block at the entrance of basic block B can be moved without using execution selection processing.

Next, in step 118a, if there is a branch that takes basic block B as the latter, a new basic block C is generated, and the instruction of the instruction block at the entrance of basic block B moved in step 117a is copied. (step 118a).

Finally, the program flow is changed (step 119a). Specifically, the first instruction block of basic block B, which is the latter of the branches not taken, is deleted from basic block B, and the flow information and branch destination are changed (FIGS. 17 to 20). As a result, the execution time is shortened by one instruction block in a flow in which a branch is not taken.

[0157] Here, changes in flow information and branch destinations will be explained with reference to FIGS. 17 to 20. In each case in the figure, (a) shows the program sequence before optimization of this embodiment, and (b) shows the program sequence after optimization. Use abbreviations.

FIG. 17 is a program sequence diagram in the case of (B does not exist from branch taken edge X) and (before optimization: B=1 instruction block).

a) Add basic block D, which is the latter of basic block B, to the latter of basic block A.

b) Remove basic block B from the latter of basic blocks A.

c) Replace [former: basic block B] of basic block D with basic block A.

FIG. 18 is a program sequence diagram in the case where (B does not exist from the branch taken edge X) and (before optimization: B≠1 instruction block), and in this case, nothing special is done.

FIG. 19 is a diagram for the case (B exists from the branch taken edge) and (before optimization: B=1 instruction block).

a) [ of basic blocks X (X1,...Xn) other than basic block A, with basic block B as the latter
The latter: basic block B] is replaced with basic block C.

b) Change [branch destination: basic block B] of basic block X to basic block C.

c) Make the latter of basic block A "the latter block D of basic block B/branch destination block of basic block A."

d) Let the former of basic block C be basic block X.

e) Let the latter of basic block C be basic block D.

f) Embed an unconditional branch instruction to basic block D in the branch field of basic block C.

g) Among the former basic blocks D, basic blocks other than basic block B are Y(Y1,...Yn)
shall be. The former basic block D is referred to as "basic block Y, basic block A, and basic block C."

FIG. 20 is a program sequence diagram in the case (B exists from the branch taken edge) and (before optimization: B≠1 instruction block).

a) [ of basic blocks X (X1,...Xn) other than basic block A, with basic block B as the latter
The latter: basic block B] is replaced with basic block C.

b) Change [branch destination: basic block B] of basic block X to basic block C.

c) The former of basic block A is changed to "basic block A. basic block C."

d) Let the former of basic block C be basic block X.

e) Let the latter of basic block C be basic block B.

f) Embed an unconditional branch instruction to basic block B in the branch field of basic block C.

[0178]

Effects of the Invention As described above, in a parallel pipeline processing system that does not cause branch delays, the present invention enables instructions other than branch instructions in an instruction block containing conditional branch instructions to be executed depending on whether the branch condition is met or not. Since it is possible to select whether to do so or not, this has the effect of suppressing the increase in empty fields in the branch instruction block and improving the processing performance of the parallel pipeline instruction processing device. In addition, it is possible to generate effective code using execution selection processing for loops, which consume most of the program execution time, reducing program execution time for loops and improving the processing capacity of pipeline instruction processing units. The effect is that it can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a system illustrating an embodiment of the present invention.

FIG. 2 is a layout diagram of instruction blocks used in the system of FIG. 1;

FIG. 3 is a layout diagram of a program sequence used in the system of FIG. 1;

FIG. 4 is a layout diagram of an instruction block as a specific example of instruction block 2 in FIG. 3;

FIG. 5 is a schematic layout diagram of the object format of the addition instruction in FIG. 3;

FIG. 6 is a layout diagram of instruction blocks in a general middle-aligned instruction parallelization method.

FIG. 7 is a block layout diagram illustrating loop optimization using an instruction execution selection function.

FIG. 8 is a flowchart explaining a second embodiment of the present invention.

FIG. 9 is a flowchart illustrating the middle align parallelization method of FIG. 8;

FIG. 10 is a flowchart illustrating the bottom-align parallelization method of FIG. 8;

FIG. 11 is a flowchart illustrating a third embodiment of the present invention.

FIG. 12 is a flowchart illustrating the loop optimization section of FIG. 11;

FIG. 13 is a program sequence diagram before optimization in FIG. 12;

FIG. 14 is a program sequence diagram after optimization of FIG. 12;

FIG. 15 is a flowchart explaining a fourth embodiment of the present invention.

FIG. 16 is a flowchart illustrating the code optimization section of FIG. 15;

17 is a program sequence diagram before and after optimization in a first case in which the program flow in FIG. 16 is changed; FIG.

18 is a program sequence diagram before and after optimization in a second case in which the program flow in FIG. 16 is changed; FIG.

19 is a program sequence diagram before and after optimization in a third case in which the program flow in FIG. 16 is changed; FIG.

20 is a program sequence diagram before and after optimization in a fourth case in which the program flow in FIG. 16 is changed; FIG.

FIG. 21 is a schematic diagram illustrating an overview of a trace scheduling method.

FIG. 22 is a schematic diagram illustrating a merging and branching processing method in the trace scheduling method.

[Explanation of symbols]

1 Instruction block memory 2 Instruction block fetch means 3 to 5
Instruction execution unit 6 Branch instruction execution unit 7 Data registers 14 to 17 Operand fetch means 18
Address generation means 19-21 Instruction execution means 22-25 Operand write means 31
Instruction block bus 32 Address bus 37-40 Register read bus 41-44
Source operand bus 45-48
Destination operand bus 49-52
Register write bus 53 Execution selection plus signal 54 Branch condition fulfillment signals 101 to 107, 111 to 119, S1 to S3, S11
~S19, S21~S26 Processing steps

Claims (5)

[Claims] 1. An instruction execution processing method for a parallel pipeline instruction processing device that is equipped with a plurality of instruction execution units and executes a plurality of instructions in parallel to avoid branch delays. If there is a conditional branch instruction in the branch instruction field of one instruction block that is composed of multiple instruction fields that are executed in parallel by instructions that are a processing unit, each instruction other than the conditional branch instruction in that instruction block is An instruction execution processing method for a parallel pipeline instruction processing device, characterized in that an instruction execution selection means for selecting whether or not to execute an instruction is provided to reduce an empty instruction field in an instruction block containing the conditional branch instruction. . 2. First and second analysis means for analyzing the control flow of the program and the data flow of the program, and the program does not stop or branch at points other than entrances and exits detected by the first analysis means. a first parallelizing means for parallelizing instructions in the program based on data flow information obtained by the second analyzing means, targeting a basic block that is a group of consecutive instruction statements; 1st
2. The parallelization means according to claim 1, wherein the instructions in the basic block are arranged so that a cycle near the center of the basic block has a good instruction filling rate and there are many empty instruction fields near the entrance and exit of the basic block. An instruction execution processing method for a parallel pipeline instruction processing device. 3. A branch checking means for checking whether the final instruction of the basic block is a branch instruction; and a branch checking means for checking whether the final instruction of the basic block is a branch instruction; and a second parallelizing means for parallelizing so as to improve the instruction filling rate, and based on the information obtained by the branch checking means, if the final instruction of the basic block is not a branch instruction, the second 3. The instructions of the parallel pipeline instruction processing device according to claim 2, wherein the second parallelizing means parallelizes the instructions, and if the final instruction of the basic block is a branch instruction, the first parallelizing means parallelizes the instructions. Execution processing method. 4. If the number of instructions excluding the number of free instruction fields of the header block of the loop is smaller than the number of free fields of the Taylor block in a natural loop in which instruction blocks are concatenated, the number of instructions at the entrance of the header block Move the instructions of the block to a free field of the Taylor block, copy the instructions of the moved header block's entry block to a new basic block, and delete the header block's entry block from this header block. 2. The instruction execution processing method for a parallel pipeline instruction processing device according to claim 1, wherein the number of instruction blocks in the loop is reduced and code is optimized by reorganizing the lever loop. 5. When the first analysis means detects a flow that does not cause a branch, the data flow information is used to move an instruction in the program or move it with execution selection, and determine the state of the flow in which this movement was performed. A new instruction block is generated in accordance with the instruction block, the instruction that has been moved is copied to the new instruction block, and a branch destination or flow information is changed for a flow in which the branch does not occur. 4. The instruction execution processing method of the parallel pipeline instruction processing device according to 4.