JP2629715B2 - Message receiver - Google Patents

Description

Description: TECHNICAL FIELD [0001] The present invention relates to a paging receiver that receives message information at the same time as receiving a call by radio and displays the message information on a screen.

[Prior art and its problems] Conventionally, there has been a paging receiver which notifies a call by a sound such as a buzzer, a horn or the like when a call is received by wireless and the call number is its own call number. In general, a call is made by calling the telephone number of the receiver to be called, that is, the calling number, and this calling number is transmitted from the radio base station of the telephone station and received by the paging receiver. Also, recently, there is a paging receiver that receives message information at the same time as receiving a call and displays the message information on a display unit. Paging receivers that can display this message are:
This is very convenient because it is not only possible to simply confirm whether or not the call has been made, but also to confirm, for example, where the call is made from or who is called. However, the display section of this paging receiver generally has only one line, and there is a problem that a long message cannot be displayed.

On the other hand, in recent years, portable liquid crystal televisions have been put to practical use, and have become widely used. This liquid crystal television has a display screen which is considerably large as compared with the display unit of the paging receiver even if it is portable. The paging receiver and the liquid crystal television are both portable and portable. Therefore, if a message is displayed on a television screen by combining them, a long message can be displayed.

[Object of the Invention] The present invention has been made in view of the above circumstances, and when message information addressed to itself is received while image information such as a television is displayed on a display screen, first, the message information is transmitted. An object of the present invention is to provide a message receiver capable of displaying received message information and displaying the received message information on a display screen when the notification is canceled.

In addition, the present invention relates to a method for temporarily storing message information when self-addressed message information is received while image information of a television or the like is displayed on a display screen and turning off the display of the image information. It is another object of the present invention to provide a message receiver for displaying stored message information on a display screen.

[Summary of the Invention] The present invention is a message receiver provided with a display screen for displaying image information of a television or the like, and receives message information addressed to itself while displaying image information on the display screen. Then, a reception interrupt process is performed, the received message information is fetched into a buffer while the image information is being displayed on the display screen, and is displayed together with the image information on the display screen. It is characterized in that it is deleted from the display screen.

Further, the message receiver according to the present invention, when displaying both image information and message information on the display screen,
A means for erasing only the message information by a predetermined operation is provided.

Furthermore, when the message receiver according to the present invention receives the message information addressed to itself while displaying the image information on the display screen, the message receiver performs a reception interruption process, and the image information remains displayed on the display screen. The received message information is fetched into the buffer, the reception flag is turned on without displaying the message information on the display screen, and the mode for displaying the image information on the display screen is switched to another mode. In this case, the message information captured in the buffer is displayed on a display screen.

First Embodiment of the Invention Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, the external configuration of a paging receiver according to the present invention will be described with reference to FIG. In FIG. 1, reference numeral 1 denotes a case, a rod antenna 2 is provided on an upper portion of the case 1, and a liquid crystal display panel 3 is provided on a front surface. On both sides of the case 1, a main switch 4 for turning on / off the paging reception function and a volume control volume 5 are provided. Further, a TV reception mode changeover switch 6, search keys 7a and 7b, a reset key 8, a write key 9, a message key 10, and a clear key 11 are provided on a front surface of the case 1. The TV reception mode switch 6 switches the TV reception mode between TV off, VHF on, and UHF on. Search key 7a, b
Plays a role of page switching for tuning up / down instructions when receiving television, and which of a plurality of messages to display when displaying messages in paging reception. A reset key 8 is a switch for stopping when a calling alarm is sounding, and a light key 9 is a switch for turning on / off the backlight of the liquid crystal display panel 3. The message key 10 is a switch for displaying message data. When the search keys 7a and 7b are pressed in the message display state by this key, the messages are sequentially changed. Clear key 1
A switch 1 clears a message displayed on the liquid crystal display panel 3 on the screen. In this case, N messages are stored in the message memory as will be described in detail later, and when the memory is full, newly received messages are at the top and sequentially deleted from the oldest.

Next, an electronic circuit provided in the case 1 will be described with reference to FIG. The antenna 2 is an antenna that receives a TV broadcast radio wave and a radio wave generated from a radio base of a telephone station. As a radio wave output from the radio base station of the telephone station, for example, a 280 MHz FM radio wave is used. This FM radio wave is modulated by the FSK signal (NRZ) method, and is 512 bits / sec.
Bit rate information. The signal received by the antenna 2 is input to the radio receiving circuit 21. The radio receiving circuit 21 is a circuit that demodulates the FSK FM signal to generate signals of “0” and “1”, and includes a circuit for selecting 280 MHz and a demodulation circuit for demodulating the FSK signal. And outputs the demodulated signal to the communication control circuit 22. In the present embodiment, a POCSAG method, which will be described in detail later, is used. The communication control circuit 22 performs data processing on a signal transmitted from the wireless reception circuit 21 according to the POCSAG method. That is, the communication control circuit 22 analyzes the data by the Poxag method and determines whether or not the call number is its own.If the call number is its own call number, the communication control circuit 22 sends a reception fetch command to the CPU 23 to receive the data. Output. This CPU23
Are connected to a function buffer 24, a key input unit 25, a message memory 26, a display buffer 27, a speaker 28, and the like. The CPU 23 detects and processes a signal from the key input unit 25, stores the received data in the message memory 26, reads out the stored data in response to the operation of the search keys 7a and 7b, and displays the read data in the display buffer. Then, the caller 27 is notified by a speaker 28 that there is a call. Note that F
Is a flag memory according to the second embodiment of the present invention, the details of which will be described later.

Also, at 30 the television tuner in Figure 2, from the radio wave of the television received by the antenna 2, to select the specified channel according to the tuning voltage V _T from the tuning control circuit 31, and converted into an intermediate frequency signal Linear Output to the circuit 32. The linear circuit 32 includes an intermediate frequency amplifier, a video detector, a video amplifier, an audio detector, an audio amplifier, a synchronization separator, and the like, and tunes a part of the intermediate frequency signal output from the intermediate frequency amplifier. Control circuit 31
To the A / D conversion circuit 33, the audio signal output from the audio amplification circuit to the speaker 34, and the vertical synchronization signal V.SY output from the synchronization separation circuit.
It outputs the NC and horizontal synchronization signal H.SYNC to the timing control circuit 35, respectively. The timing control circuit 35 generates various timing signals based on the synchronization signal from the linear circuit 32, outputs the basic clocks φ1 and φ2 to the A / D conversion circuit 33, and outputs the basic clocks φ1 and φ2 clock .phi.10, and outputs the shift data phi _DT and clock phi _L for φ20 and the display control on the CPU 23. The above operation clock φ1
0 and φ20 are output at a period later than the basic clocks φ1 and φ2. The CPU 23 controls the operation of each unit in accordance with the timing signal from the timing control circuit 35, and also performs the search keys 7a, 7
When b is operated, the tuning control circuit 31
Output a down command.

The A / D conversion circuit 33 samples the video signal sent from the linear circuit 32 in synchronization with the basic clocks φ1 and φ2, converts it into 4-bit video data, and outputs it to the coupling circuit 36. . The coupling circuit 36 stores the message data stored in the message memory 26 in the CP.
Read and input by U23. Since this message data is in 1-bit units and the video data is in 4-bit units, each bit of the message data is converted by the combining circuit 36 into "1111" or "0000". The above coupling circuit 36
Selects the video data from the A / D conversion circuit 33 or the message data from the CPU 23 according to the switching signal from the CPU 23, and outputs it to the segment drive circuit 37. Moreover, this segment driving circuit 37, the basic clock φ1 from the timing control circuit 35, .phi.2, latch clock phi _L, clock phi _C is applied for creating gradation signal. The above segment drive circuit 37
Stores the 4-bit data sent from the coupling circuit 36 for one line in synchronization with the basic clocks φ1 and φ2, and then creates a gradation signal in accordance with the stored data. The segment electrodes are driven for display. The common electrode of the liquid crystal display panel 3 is selectively driven by a common drive circuit 38. The common drive circuit 38 generates a common signal to shift data phi _DT in synchronization with the vertical synchronizing signal supplied from the timing control circuit 35 sequentially shifted by clock phi _L. Further, the liquid crystal display panel 3 is illuminated from the back side by a backlight device 39. The driving of the backlight device 39 is controlled by the CPU 23. Further, the CPU 23 is provided with a timekeeping function, not shown, so that the current time is always timed.

3 (A) to 3 (F) are data configuration diagrams of the poxag method.

FIG. 3 (A) shows the entire transmission signal format. In the Poxag system, the first 57
It is composed of a 6-bit 101010, a preamble signal A successively following, and a plurality of batch signals B, C,. The preamble signal is a signal for causing the paging receiver to recognize that data is to be transmitted from now on and for synchronization. The communication control circuit 22 detects this preamble signal and recognizes that batch data will be sequentially added below.

FIG. 3B shows a batch format of the batch data. This batch format consists of a synchronization code SC, and then each code of two words. Each code has two words. For example, in the embodiment of the present invention, one word is 32 bits, and one batch is composed of CD1 to CD8 blocks, for a total of “32 × 2 × 8 = 512 bytes”.
Is made up of

FIGS. 3 (C) and 3 (D) show the structure of each code which becomes the aforementioned two code words. FIG. 3 (C) shows an address code word, which is headed by a message flag,
After the message, an address code, a function bit, a BCH parity, and an even parity are configured.

The message flag is a flag for identifying whether the next code is an address code or a message code. When 0, an address code word is shown, and when 1, the message code word is shown. The 2nd to 19th bits after the message flag are the address code, which corresponds to the above-mentioned call number. Further, there are two function bits after this. This is a bit for indicating a display mode and a sound mode, for example, "00", "01",
There are four types of functions according to "10" and "11".
In the poxag method, an error may occur within one code, for example, an address code. In particular, when the reception state is poor, the demodulation of the FSK signal is not complete, and an error occurs. To correct this, BCH parity is provided in bits 22 to 31.
Correction is performed when an error occurs due to the 10-bit data. This is called BCH parity. Thereafter, an even parity bit is provided in bit 32. This even parity indicates whether the total number of bits from the beginning to the end indicating the number of “1” is odd or even. For example, if one bit “0” is mistaken for “1”, By checking the even parity, it can be determined whether a bit is missing or added.

In the case of the message code word shown in FIG. 3D, a message bit is added after the message flag. This is in addition to the message from the caller, for example a telephone number and also other information. Further, similarly, data of BCH parity and data of even parity are similarly added to the same code word to form a message code word.

In the poxag method, the power of the wireless reception circuit 21 is not always turned on, but is turned on only when necessary. Each paging receiver has a block CD1 in one batch
.. CD8 are assigned, and a signal for detecting the position of the assigned one block is a synchronization code word. The receiver is powered on for the duration of the synchronization codeword and the assigned block.
The preamble signal is a signal for synchronizing the whole, and when the synchronism is not obtained, the power is turned on to receive this signal. FIG. 3 (E) is a diagram showing the bit configuration of the synchronization code word, which is "0111110011010010000101011101".
"1000" is the bit configuration. When receiving the bit-structured signal, the radio receiving circuit 21 receives one block from the subsequent blocks in the time allocated to each receiver. For example, the receiver is set to be always in the receiving state during the time period of the synchronization code, and after detecting the synchronization code, the radio reception is again performed during the code word of the block assigned to its own frame, for example, CD2 in FIG. 3 (B). The power of the circuit 21 is turned on, and it is determined whether or not the received code word, for example, the address data in FIG. 3 (C) is its own data. If not, turn off the power.

On the other hand, if they match, the next message code word is also received and its data is fetched. The receiver turns on the power of the radio reception circuit 21 when receiving the synchronization code and when the code word of the block assigned to itself is received. In other words, the receiver always turns on the power when the synchronization code and its assigned block are in units of one batch word. Since the entire receiver is not synchronized when the power of the receiver is turned on for the first time, the power of the wireless receiving circuit 21 is periodically turned on to detect the preamble. To summarize the above-described Poxag method, when the receiver detects a preamble, it turns on the power of the wireless reception circuit 21 when receiving a synchronization code and further receiving a codeword assigned to itself.

It is the communication control circuit 22 that performs these controls, and the radio receiving circuit 21 performs a receiving operation by the on / off control of the communication control circuit 22. For example, when the preamble can be detected and the whole is synchronized, the power of the radio reception circuit 21 is turned on when the synchronization code and the block assigned to itself in the eight blocks CD1 to CD8 are used. In this way, power consumption is reduced.

In the poxag scheme, a word called an eye link code word is provided in addition to the aforementioned code word. FIG. 3 (F) is a diagram showing the bit configuration of the idle link code word. The idle link codeword is a null code, and when this codeword is received, it is as if the paging receiver did not receive any data. For example, when the idle code word is at the position of the synchronization code word, the synchronization is lost when it is received, and when it is present in the address code word or the message code word, it is the same as when nothing is received.

Next, the details of the main part in FIG. 2 will be described.

FIG. 4 is a detailed circuit configuration diagram of the communication control circuit 22 in FIG. The reception signal input from the wireless reception circuit 21 is input to the input synchronization circuit 41. The input synchronization circuit 41 is a circuit that corrects the disturbance of the "0" and "1" signals with respect to the demodulation of the FSK signal. The input synchronization circuit 41 can take in stable data. Input synchronization circuit
The signal captured by 41 is applied to a BCH error correction circuit 45, a preamble detection circuit 42, and a synchronization code detection circuit 44. The preamble detection circuit 42 detects a preamble, and the detection signal is sent to the timing control circuit 43. When the preamble is detected by the preamble detection circuit 42, the preamble detection circuit 42 operates to detect whether or not a synchronization code has been entered, and outputs a detection signal to the timing control circuit 43. The BCH error correction circuit 45 is a circuit which takes in all the data of the block allocated to itself in the batch format, determines whether or not there is a BCH error, and corrects if there is an error.
When an address code is received by the BCH error correction circuit 45, an error-corrected code is input to the call number detection circuit 46. An ID-ROM 47 and an ID-ROM II 48 storing ID numbers are connected to the calling number detection circuit 46, and the data of the corrected code is compared with the data entered from each ID-ROM. Is detected. In the embodiment of the present invention, the ID-ROM 47 and the ID-ROM II 48 store the first address and the second address in each paging receiver. The timing control circuit 43 always has a clock that detects the timing for the synchronization code, and the transmitting side sequentially sends a preamble, batch format, and multiple batch data, so the timing control circuit 43 detects the synchronization code when it detects the preamble The power supply control circuit 49 is turned on until the operation is completed. In addition, the power control circuit 49
Turn on. When an ON signal is applied from the power supply control circuit 49, the synchronization code detection circuit 44 detects the synchronization code, and the BCH error correction circuit 45 corrects the received data and inputs the data to the call number detection circuit 46. This call number detecting circuit 46 recognizes whether or not the call is its own call. If the call number is not its own call number, the process is terminated as it is, and the code word is detected again.

On the other hand, if the call number is its own, a reception interrupt signal is generated, and an interrupt is issued to the CPU 23 in FIG. The signal of the calling number detection circuit 46 is
When the signal is added to 0 and the signal indicating that the calling numbers match is input, the CPU control circuit 50 outputs a reception interrupt signal to the CPU 23. Thus, the CPU 23 performs a process described later.

Further, the data stored in the BCH error correction circuit 45 received later or currently received is input to the SP conversion circuit 51 via the call number detection circuit 46. The SP conversion circuit 51 is a circuit for transferring 1-bit data that enters the serial to the CPU 23 in 8-bit units. As will be described later, this circuit is connected to the address / control bus and data bus of the CPU 23, and an interrupt signal is output from the CPU control circuit 50 in 8-bit units, whereby the CPU 23 takes in 8-bit data.

When the CPU control circuit 50 completes reception of all other data, it outputs a termination interrupt signal. The received data is added in units of 8 bits. In addition, 2 function bits included in the address code are also
Output to the buffer in U23. This is performed under the control of the CPU control circuit 50. Further, the message code is also sequentially distributed in 8-bit units as error-corrected message data in 8-bit units.
Incorporated in U23.

The communication control circuit 22 always operates, and the timing control circuit 43 turns on / off the power supply via the power supply control circuit 49 as described above, thereby preventing the entire power consumption.

FIG. 5 shows details of the message memory 26 in FIG. The message memory 26 includes a message buffer 26a and N message registers 1 to N.
, And then written to the message register 1. At this time, the data in the message register 1 is shifted to the register 2, and the data in the last register N is pushed out and disappears. That is, the message memory 26 has a FIFO buffer configuration.

FIG. 6 shows the details of the main part of the CPU 23 in FIG. 2, that is, the part for converting the message data stored in the display buffer 27 into 1-bit data for display and outputting it to the coupling circuit 36. In 231 Figure 6 at the address counter counts up operation by the clock phi _L, it is reset by the shift data phi _DT. The count data of the address counter 231 is sent to the character generator 232 as address data,
It is sent to the display buffer 27 via the selector 233 as a read address. Also, this display buffer 27 contains CPU2
A write address is given from a control unit (not shown) in 3 via a selector 233. The selector 233 switching operation according to a control signal from the control unit, a write cycle selects the address data AD _W from the control unit, the display in the read cycle, by selecting the address data AD _R from the address counter 231 buffer Output to 27. The display buffer 27 has a capacity capable of storing character data for display of one screen, and is stored in the message memory 26 in the CPU 2.
The message data sent via the server 3 is stored and sequentially output to the character generator 232 according to the designated address. The character generator 232 generates 6-bit character data for the data from the display buffer 27 in accordance with the address specified by the address counter 231 and outputs it to the parallel / serial converter 234. The parallel / serial converter 234 in synchronization with the latch clock phi _L latches 6-bit data, and outputs bit by bit in synchronism with the basic clock phi _1. Bit data output from the parallel / serial converter 234, a flip-flop in synchronization with the basic clock phi ₂
235 and sent to the second combining circuit 36.

The coupling circuit 36 is configured as shown in FIG. That is, the 4-bit TV video data sent from the A / D conversion circuit 33 in FIG. 2 is input to the OR circuits 365 to 368 via the gate circuits 361 to 364. The 1-bit message data transmitted from the CPU 23 is input to the OR circuits 365 to 368 via the gate circuit 369. The gate circuits 361 to 364, 369 are on / off controlled by a control signal from the CPU 23. That is, in the television reception mode, control is performed such that the normal gate circuits 361 to 364 are turned on and the gate circuit 369 is turned off. However, when paging reception is performed in the television reception mode, the gate circuit 369 is turned on, and the television image data and the message resulting from the paging reception are combined by the OR circuits 365 to 368. Then, the 4-bit data output from the OR circuits 365 to 368 is sent to the segment drive circuit 37 shown in FIG.

Next, the operation of the above embodiment will be described with reference to the timing charts of FIGS. When the power supply of the receiver is turned on, the operation shown in the flowchart of FIG. 8 is executed by the communication control circuit 22 shown in detail in FIG. That is, when the power of the receiver is turned on, first, the process of step A1 of the preamble search is performed. This search request is made by the timing control circuit 43. The preamble consists of 576 bits, but the preamble detection circuit 4
2 is added to the timing control circuit 43 as a preamble detection when it continues continuously with 8 bits “10101010” therein. When the preamble is detected, the timing control circuit 43 causes the synchronization code detection circuit 44 to start the operation of detecting the synchronization code. The synchronization code appears immediately after the preamble, and if the batch data is continuous, it comes at the head of each batch data. When detecting the first preamble, the timing control circuit 43 operates the synchronization code detection circuit 44 immediately after the preamble detection signal is applied. When the synchronization code is detected by the synchronization code detection circuit 44, that is, when the synchronization code is detected in step A2, the data of the own block is taken into the BCH error correction circuit 45 next. At this time, the power supply of the ignore receiving circuit 21 is on as described above. Then, after taking in the data of the own block, the call number detecting circuit 46 is operated, and the ID-ROM I 47, ID-ROM II
A process for detecting whether or not the content of 48 matches the received code, that is, a word search process shown in step A3 is performed. Next, it is determined whether the synchronization code has been lost twice. In general, there is a case where the synchronization code is not detected once due to noise or the like. Therefore, in the embodiment of the present invention, it is determined that the synchronization is lost when the synchronization is lost twice. Then, the process is executed again from the preamble search process in step A1.

On the other hand, if the ID code has been lost only once or once (when the determination result in the determination step A4 is NO), it is determined in a determination step A5 whether the ID codes match. ID
If there is no code, step A3 of the word search (ID code search) is executed again.

If the ID codes match, the message is fetched next (step A6. This fetch is performed by the CPU 23 as will be described later).
Is converted into data in units of 8 bits by the SP conversion circuit 51 and sent to the CPU 23. Then, when the CPU 23 finishes taking in the data, that is, when step A6 ends, it is determined in step A7 whether the message has ended. That is, the message flag of the first bit of the message code word is checked. If the message flag is "1", it is determined that the next message data follows. If the message flag is "0", the message has been completed. Judge. If the decision result in the step A7 is NO, the message fetching process is performed again, and the above operation is sequentially repeated. This is performed in units of 8 bits as described above. For example, it is determined whether or not the entire 20 bits of the message bits 2 to 21 have been fetched, that is, whether or not the end of the message has been reached. When it is determined in step A7 that the message is at the end of the message, the process is performed again from the word search process in step A3. If the preamble is not detected at the time of turning on the power, or if the preamble is not detected, the synchronization cannot be achieved, so that the synchronization code is naturally lost twice. At this time, the process is performed again from the preamble search process in step A1. In the preamble search process, the power of the wireless reception circuit 21 is turned on for 62.5 msec, and it is determined whether or not the preamble is present.
If it is not the preamble, the power of the wireless receiving circuit 21 is turned on again after 1062.5 msec, and the process is repeated from the preamble search in step A1. In this preamble search processing, the preamble sent before the batch data can be detected by repeating the preamble search processing several times.

As described above, the power supply of the wireless reception circuit 21 is turned on at regular intervals, a preamble is detected during that time, and further synchronization is established so that the power supply is turned on only at the time of a block to which the user has been assigned, and his own address is used. It is determined whether or not there is. As a result, power consumption is reduced.

Next, processing operations of the CPU 23, that is, processing operations for various key operations, reception interrupts, timed interrupts, and the like will be described with reference to the flowchart of FIG. When the power of the paging receiver is turned on by the main switch 4, the CPU 23 enters a standby (HALT) state as shown in a ninth step B1, and interrupts due to various key inputs from the key input unit 25, a reception interrupt, and a timing interrupt are performed. Prepare for etc. When the mode is switched by the TV reception mode changeover switch 6 in this state, an interruption of step B2 is performed, and "TV off", "VHF on", and steps B4, B5 and B6 shown in steps B4, B5 and B6 are performed.
The operation mode of "UHF ON" is specified.

In the case of "TV off", the process returns to the standby state of step B1 and prepares for an interruption due to the next key input or the like. In this case, the processing of steps B7 and B8 following step B4 is in the second embodiment of the present invention, and details thereof will be described later. In the case of “VHF on” shown in step B5 and “UHF on” shown in step B6, the TV receiving circuit system in FIG. The signal is selected by the tuner 30 and sent to the linear circuit 32. The video signal output from the linear circuit 32 is converted by the A / D conversion circuit 33 into four.
The data is converted into digital data of bits and sent to the coupling circuit 36. In this TV reception mode, since the gate circuits 361 to 364 in the coupling circuit 36 (see FIG. 7) are turned on by the control signal from the CPU 23, the video data output from the A / D conversion circuit 33 is segment driven. Sent to circuit 37,
It is displayed on the liquid crystal display panel 3. At this time, the common drive circuit 38 generates a common signal based on the timing signal from the timing control circuit 35, and sequentially and selectively drives the common electrodes of the liquid crystal display panel 3.

When the search keys 7a and 7b are operated in the TV reception mode, an interruption shown in step B9 is performed, and it is determined in step B10 whether the operation mode at that time is the TV mode or the message display mode. like
If it is in the TV mode, the auto tuning operation shown in step B11 is performed. That is, by operating the search key 7a, and 7b, the up / down signal U / D from CPU23 in accordance with the operation it is output, tuning control circuit 31 outputs a tuning control voltage V _T accordingly. Tuning operation of the tuner 30 is performed by the tuning control voltage V _T. At this time, the tuning control circuit 31 performs tuning control based on the intermediate frequency signal IF from the linear circuit 32, and correctly selects a channel. After the end of the auto tuning operation, the process returns to step B1. If it is determined in step B10 that the current mode is the message display mode, the display data switching process in step B12, which will be described in detail later, is executed, and the process returns to step B1.

The CPU 23 has an internal clock function. When a clock timing signal is generated, the CPU 23 performs a clock interrupt shown in step B13 regardless of the operation mode, executes the clock processing in step B14, and then returns to step B1.

Further, when paging reception is performed in the TV mode or other modes, that is, when a reception interrupt signal is added, the CPU 23 performs a reception interrupt shown in step B15, and performs a message fetching process in step B16.

The above message fetching process is executed in accordance with the flowchart shown in FIG. First, function bits are taken into the function buffer 24 as shown in step C1. Next, in step C2, it is determined whether a serial / parallel (S / P) interrupt, that is, an 8-bit interrupt has been added. If there is no interrupt, the apparatus enters a standby state until an interrupt is added. When an S / P interrupt is detected in step C2, the 8-bit serial data is converted to SP conversion circuit 51.
Is converted into 8-bit parallel data, and is taken into the message buffer 26a in the message memory 26 in step C3. Next, in step C4, it is determined whether the message has ended. If not, the process returns to step C3.
The data stored in the message buffer 26a is stored in the register area of the message memory 26. This completes the message fetching process, and then proceeds to step B17 in FIG.

In this step B17, an alarm operation is performed, the speaker 28 is driven for a predetermined time, for example, 8 seconds, and the user is notified that paging has been received. This alarm is
After a lapse of seconds, the power is automatically turned off, but when the alarm is to be stopped halfway, the reset key 8 is operated.
The operation of the reset key 8 causes an interruption in step B19 and turns off the alarm in step B20. When the processing in step B17 or B20 is completed and the alarm is turned off, the display processing shown in step B18 is executed.

The display processing in step B18 is performed according to the flowchart shown in FIG. First, in step D1, display data is created in the display buffer 27. First, the message data stored in the message register 1 of the message memory 26 is read, and only the lower part of the display buffer 27 is written as shown in FIG. Next, in step D2, it is determined whether the mode at that time is TV-on or TV-off.
Is read out and displayed on the liquid crystal display panel 3. That is, in FIG. 6, the message data stored in the display buffer 27 is sequentially read out according to the count value of the address counter 231 and input to the character generator 232 to be converted into 6-bit character data. The character data output from the character generator 232, a parallel / serial converter 234 to read in by the latch clock phi _L, then, is output bit by bit in synchronism with the basic clock phi _1. The serial data output from the parallel / serial converter 234 is sent to a coupling circuit 36 via a flip-flop 235, converted into 4-bit data of "1111" or "0000", and sent to a segment drive circuit 37. It is displayed on the liquid crystal display panel 3. For example, the message shown in FIG. 12 is displayed on the liquid crystal display panel 3. In step D2, the mode at that time is
If it is determined that the TV is turned on, the process proceeds to step D4 to superimpose a message on the TV screen. That is,
In the TV-on mode, both gates of the gate circuits 361 to 364 and the gate circuit 369 are opened in the coupling circuit 36 shown in detail in FIG. The message data sent from the CPU 27 through the CPU 23 are combined by OR circuits 365 to 368 and output to the segment drive circuit 37. As a result, the message is superimposed on the TV screen and displayed. And step
After the above message display is performed for, for example, 20 seconds as shown in D5, the message display is cleared. With the above, the reception interrupt processing is completed, and the process returns to the standby state of step B1. When combining the television image data and the message data in step D4, the timings need to be matched. Therefore, in the CPU 23, as shown in FIG. 6, the operation timing of the address counter 231 and the parallel / serial converter 234 is matched with the operation timing of the common drive circuit 38 in FIG. To be displayed.

When the user wants to view the message stored in the message memory 26 except at the time of the reception interruption,
Operate message key 10 with TV off. The operation of the message key 10 causes an interrupt in step B21, and in step B22, the message reading from the message memory 26 and display processing are performed in the same manner as in step B18. In this case, first, the message stored in the message register 1 in the message memory 26 is read and displayed. However, when the user wants to see the messages stored in other message registers, the search keys 7a, 7b Operate. This search key 7a, 7b
Interrupt of step B9 by the operation of
In B10, it is determined whether the current mode is the message display mode or the TV mode. At this time, since the message display mode is set, step B12
The display data switching process is performed. That is, the operation of the search keys 7a and 7b causes the message memory 26 to operate.
Are sequentially selected and designated, the message data stored in the designated register is read out to the display buffer 27, and sequentially switched and displayed on the liquid crystal display panel 3.

To delete the above message, press the Clear key
Operate 11 Steps can be performed by operating the clear key 11.
At step B23, the display message on the screen is cleared.

The liquid crystal display panel 3 is provided with a backlight device 39, which can be turned on / off by operating the light key 9. When the light key 9 is operated, an interrupt is performed in step B25, and in step B26, the backlight device 3
9 is switched on / off.

As described above, processes such as interruption to operation keys and reception interruption are performed, and even when paging is received during TV reception, the message is displayed as a superimpose on the TV screen.

[Second Embodiment of the Invention] In the first embodiment, when the reception interruption shown in step B15 occurs during TV reception, a message is superimposed on the TV screen to be displayed. In the example, the message data is displayed on the liquid crystal display panel 3 when the display of the television image is completed. That is, in the second embodiment, the processing shown in the flowchart of FIG. 13 is executed as the display processing shown in step B18, and then the processing of steps B7 and B8 in FIG. 9 is executed. If there is a reception interruption shown in step B15, after the message is fetched in step B16 and the alarm is notified in step B17, the process proceeds to the display process in step B18. First, the message is displayed on the display buffer 27 in step E1 in FIG. Create data. That is, the message data stored in the message memory 26 is read out by the current paging reception, and written into the display buffer 27. Next, in step E2, it is determined whether the mode at that time is TV on or TV off.If the mode is TV off, the message data written in the display buffer 27 is immediately read out as shown in step E3. The image is displayed on the liquid crystal display panel 3. However, if it is determined in step E2 that the mode is the TV mode, the process proceeds to step E4, where the reception flag is stored in the flag memory F provided in the CPU 23, and thereafter,
It returns to the standby state of step B1.

After that, when the mode is switched to the “TV off” mode by the TV reception mode changeover switch 6, the ninth mode is switched as described above.
The TV is turned off by the interrupt processing in steps B2, B3, and B4 in the figure. Thereafter, it is determined in step B7 whether the reception flag is set in the flag memory. If the reception flag has not been set, the process returns to the standby state. If the reception flag has been set, the process proceeds to step B8, where the message data stored in the display buffer 27 is read out and displayed on the liquid crystal display panel 3. This display message is cleared by operating the clear key 11 as described above.

[Effects of the Invention] As described in detail above, the present invention is a message receiver provided with a display screen for displaying image information such as a television set. When the message information addressed to is received, the reception interrupt processing is performed,
While the image information is being displayed on the display screen, the received message information is fetched into a buffer and displayed together with the image information on the display screen, and after a predetermined time has elapsed, only the message information is deleted from the display screen. Therefore, even if a message is received while watching image information on a TV or the like, the message information will not be overlooked, and only the message information will be deleted after a predetermined period of time. No hassle.

Further, according to the present invention, when both the image information and the message information are displayed on the display screen, there is provided a means for deleting only the message information by a predetermined operation. When both are displayed, the message information can be immediately deleted.

Further, according to the present invention, while displaying image information on the display screen, when receiving message information addressed to itself, a reception interrupt process is performed, and the image information is displayed on the display screen. When the received message information is fetched into the buffer, the reception flag is turned on without displaying the message information on the display screen, and when switching from the mode for displaying the image information on the display screen to another mode, Since the message information taken into the buffer is displayed on the display screen, the message information can be surely confirmed when the mode is switched without disturbing the viewing of the image information of the television or the like. .

[Brief description of the drawings]

1 to 11 show a first embodiment of the present invention. FIG. 1 is a front view showing an external configuration, FIG. 2 is a block diagram showing an entire circuit configuration, and FIG. To (F) are data configuration diagrams of the POCSAG system, FIG. 4 is a block diagram showing details of the communication control circuit in FIG. 2, FIG. 5 is a diagram showing the internal configuration of the message memory in FIG.
FIG. 6 is a block diagram showing a part of the CPU in FIG. 2,
FIG. 7 is a diagram showing details of the coupling circuit in FIG. 2, FIG. 8 is a flowchart and timing chart showing the operation of the communication control circuit, FIG. 9 is a flowchart showing the operation of the CPU,
FIG. 10 shows the message fetching step B16 in FIG.
FIG. 11 is a flowchart showing details of the display processing step B18 in FIG. 9, and FIG.
Figure 2 shows an example of writing a message to the display buffer.
FIG. 3 is a flowchart showing details of the display processing steps in the second embodiment of the present invention. 1 ... Case, 2 ... Antenna, 3 ... Liquid crystal display panel, 4 ... Main switch, 5 ... Volume adjustment volume, 6 ... TV reception mode changeover switch, 7a, 7b ... Search key, 8 ... ... Reset key, 9 ... Light key, 10 ...
... Message key, 11 ... Clear key, 21 ... Wireless receiving circuit, 22 ... Communication control circuit, 23 ... CPU, 24 ... Function buffer, 25 ... Key input unit, 26 ... Message memory, 27 ... … Display buffer, 28 …… Speaker, 30…
... Tuner, 31 ... Tuning control circuit, 32 ... Linear circuit, 33 ... A / D conversion circuit, 35 ... Timing control circuit, 36 ... Coupling circuit, 37 ... Segment drive circuit, 38 ...
... Common drive circuit, 39 ... Backlight device, 41 ... Input synchronization circuit, 42 ... Preamble detection circuit, 43 ... Timing control circuit, 44 ... Sync code detection circuit, 45 ... BC
H error correction circuit, 46 …… Called number detection circuit, 47 …… ID-R
OM I, 48… ID-ROM II, 49… Power supply control circuit, 50…
CPU control circuit, 51 SP conversion circuit, 231 address counter, 232 character generator, 233 selector, 234 parallel / serial converter, 235 flip-flop, 361-364,369 gate circuit , F... Flag memory.

Claims (3)

(57) [Claims] 1. A display means having means for displaying image information; a mode selecting means for selecting a mode for displaying image information and another mode; a receiving means for receiving message information; Notifying means for notifying that the information has been received, and interrupt means for performing reception interrupt processing when the receiving means receives message information while the mode selecting means has selected a mode for displaying image information, When the interrupting unit performs a reception interrupt process, a buffer unit that captures the message information received by the receiving unit while the image information is displayed on the display unit, and the message information captured by the buffer unit is Display control means for displaying the image information together with the image information on the display means, and the display control means displaying the image information and the message on the display means A message receiver comprising: an erasing means for erasing only the message information from the display means when a predetermined time elapses while displaying both information. 2. The apparatus according to claim 1, wherein said erasing means comprises means for erasing only the message information by a predetermined operation when the display control means displays both the image information and the message information on the display means. The message receiver according to claim 1, wherein: 3. A display unit having means for displaying image information, a mode selecting means for selecting a mode for displaying image information and another mode, a receiving means for receiving message information, and the receiving means comprising: Notifying means for notifying that the information has been received, and interrupt means for performing reception interrupt processing when the receiving means receives message information while the mode selecting means has selected a mode for displaying image information, When the interrupt unit performs a reception interrupt process, a buffer unit that captures the message information received by the reception unit while the image information is displayed on the display unit, and that the buffer unit captures the message information.
Flag control means for turning on a reception flag without displaying the message information on the display means; and when the mode selection means switches from a mode for displaying image information to another mode, the flag control means A message receiver, comprising: display control means for displaying, on the display means, message information taken into the buffer means when detecting that the reception flag is on.