JP2625730B2 - High frequency amplifier and adjustment method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency amplifier used for a television tuner circuit or the like.

2. Description of the Related Art In recent years, high-frequency amplifiers have been developed due to the development of new media and the like.

Hereinafter, an example of the above-described high-frequency amplifier will be described with reference to the drawings.

FIG. 3 shows a specific example of a conventional high-frequency amplifier, and FIG. 4 is a characteristic diagram thereof. In FIG. 3, 31 is
FET transistor, 32 is feedback source resistance, 33 is fixed power supply, 34 is bias resistance, 35 is coupling capacitance, 36 is bias resistance, 37 is choke coil, terminal 3A is signal input terminal, 3B
Indicates an AGC terminal, 3C indicates a power supply terminal, and 3D indicates a signal output terminal. The operation of the high-frequency amplifier configured as described above will be described below.

First, the FET transistor 31 has a coupling capacitance 3 from the terminal 3A.
5 via the signal is input to the first gate G _1, the second gate G
₂ is supplied with a bias potential from a terminal 3B via a resistor 36, and when a power supply voltage is applied to the drain via a choke coil 37 from a terminal 3C, a current flows between the drain and the source. The source current flows through the source feedback resistor 32 toward the fixed potential 33. The first gate potential is biased to a potential lower than the source potential by a potential drop due to the source feedback resistor 32. The operating current _ID flowing according to the magnitude of the resistor 33 changes, and the amount of the change changes according to the current I _DSS flowing when the potential between the first gate and the source of the FET is set to O, and the change is the fourth. It looks like the figure. At this time, an output signal is obtained from the terminal D from the drain.

Incidentally, the horizontal axis represents the value of the source feedback resistor R ₃₂ in FIG. 4, the vertical axis represents the change in the operating current I _D with respect to it I _DSS as a parameter.

The invention tries to solve to such problems, however the structure, the maximum value that can be used as the operating current for ensuring the performance I _DMAX, the minimum value is taken as I _DMIN, securing the source feedback resistor R ₃₂ Resistance R _f
In this case, due to the limitations of I _DMAX and I _DMIN , only those in the range of I _DSS between the intersections A and B with the I _DSS curve can be used, and the production yield of FET transistors is reduced.

The present invention has been made in view of the above problems, and provides a high frequency amplifying device having a function of expanding usable _IDSs .

Means for Solving the Problems In order to solve the above problems, the high frequency amplifying device of the present invention provides a current potential to the drain of the FET transistor in which ID _DSS varies, and a bias potential sufficient for operation to the second gate. And the source is connected to a fixed potential through a resistor whose characteristics can be changed by external means, and the fixed potential is applied to the first gate. Alternatively, the sources of the two FET transistors are connected to each other. A structure in which a power supply potential is applied to only one drain of a transistor, a current flowing through only one path is supplied to a fixed potential after passing through a common source variable resistor, and the fixed potential is applied to a first gate of each transistor. It is provided with.

Action The present invention is the configuration described above, by varying the source feedback resistor, in which can be held within the allowable range operating current even for a wide range of variation of I _DSS.

Embodiment Hereinafter, a high-frequency amplifier circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a high-frequency amplifier according to a first embodiment of the present invention. In FIG. 1, 11 and 18 are FET transistors, 12 is a variable resistor, 13 is a fixed power supply, 14, 110 is a bias resistor, 15, 111 is a coupling capacitance, 16, 112 is a bias resistor,
17 and 113 indicate choke coils, terminals 1A and 1H indicate signal input terminals, 1B and 1G indicate AGC terminals, 1D and 1E indicate signal output terminals, and 1C and 1F indicate power supply terminals. FIG. 2 shows the operating current characteristics of the high-frequency amplifier of FIG. 1, in which the horizontal axis represents the source feedback resistance, the vertical axis represents the operating current _ID , and _IDS is drawn as a variable.

The operation of the high-frequency amplifier configured as described above will be described below with reference to FIGS. In FIG. 1, a first gate of the FET transistor 11 is connected to a terminal 1A.
And an input signal is supplied through the coupling capacitor 15. The DC potential to the first gate is given via the resistor 14 as much as the potential dropped from the source by the variable resistor 12. The power supply voltage is applied to the drain of the FET from the terminal 1C via the choke coil 7, and the terminal 1D
A more amplified signal is output. FET transistor 11
A bias potential is applied to the second gate from the terminal 1B via the resistor 16, and the operating current of the FET transistor 11 is applied to the fixed potential 13 via the variable resistor 12. On the other hand, the source of the FET transistor 11 is connected to the source of the FET transistor 18 in common.
G ₁ and the second input signal via the coupling capacitor 111 from a terminal 1H is given. The second gate G ₂ of the transistor 18 is AGC potential is supplied through a bias resistor 112 from the terminal 1G,
A power supply voltage is supplied to the drain from the terminal 1F via the choke coil 13. The amplified signal can be obtained from the terminal 1E. The source of transistor 18 is transistor 11
And one of the terminals 1C and 1F is set to a high potential, so that only one of the FET transistors 11 and 18 operates and the current of one of the The fixed potential 13 flows via the variable resistor 12 to the fixed potential 13, and supplies the bias potential to the first gate of the transistor 18 via the bias resistor 110. Usually two FEs
The L _DSS of the T transistor has a different value. in this case,
If each source resistance is adjusted by setting the source resistance at two locations, a source resistance value corresponding to the I _{DSS of} each transistor can be obtained as described in the conventional example. There is a disadvantage that the adjustment position is doubled. This embodiment eliminates the disadvantages as follows. First, set the value of the variable resistor 12 to a constant value,
And the power supply of 1F are separately set to a high potential, and the larger of the source current in each case is selected. Assuming that the terminal 1C side is larger, the terminal 1C is fixed at a high potential and the terminal 1F is fixed at a low potential, and is _adjusted to be equal to or less than the maximum allowable value I _DSMAX of the operating current _ID shown in FIG. The resistance 12 is changed. With the variable resistor 12 at that value, replace the high and low potentials of the power supply terminals 1C and 1F, measure the source current in the same way, and
Confirm that it is I _DSMIN or more, and finish the adjustment. In the present example, the adjustment is started from the FET transistor with the larger operation current, but the adjustment may be started from the smaller one.

Note that an integrated circuit using a GaAs element may be used as the two FET transistors 11 and 18 in the text. Furthermore, the circuit is mounted on an alumina substrate, and as a variable resistor,
The value of the printing resistance may be changed by a laser.

As described above, by using the present invention, variations in the _IDSS of the FET transistor can be absorbed, and the yield when a circuit is formed is dramatically improved. Furthermore, when configuring an integrated circuit including two transistors, the number of adjustment points is halved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a high-frequency amplifier circuit according to an embodiment of the present invention, FIG. 2 is a characteristic diagram thereof, FIG. 3 is a circuit diagram of a conventional high-frequency amplifier circuit, and FIG. 4 is a characteristic diagram thereof. 11,18 …… FET transistor, 12 …… variable resistor, 13 …… fixed power supply, 14,110 …… bias resistor.

Claims (3)

(57) [Claims] 1. The source of two FET transistors is connected in common, and the drain of each FET transistor is provided with external switching means so that only one of them has a high potential. A high-frequency amplifier, wherein a fixed potential is supplied from a source via a variable resistor, and the fixed potential is supplied to a first gate of each FET transistor. 2. The high-frequency amplifier according to claim 1, wherein the variable resistor is a printed resistor on an alumina substrate, the resistance of which is variable by laser trimming. 3. The source of two FET transistors is connected in common, and the drain of each FET transistor is provided with external switching means so that only one of them has a high potential. A fixed potential is supplied from a source via a variable resistor, a fixed potential is supplied to a first gate of each FET transistor, and a high potential is applied to each drain of the two FET transistors in order. And record the drain current for
When operating from a transistor having a low drain current value, the variable resistor is changed so that the drain current becomes the operation allowable minimum value, fixed at that position, the other transistor is operated, and the drain current is set to the operation allowable maximum value. When setting the drain current to the maximum allowable value with a variable resistance value, fix it at that position and operate the other transistor so that the operating current does not fall below the minimum allowable value. A method for adjusting a high frequency amplifying device, characterized in that: