JP2622284B2 - Frequency range detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention automatically determines whether an input frequency is within a set band, a band below the set band, or a band above the set band. The present invention relates to a frequency range detection device for determining.

[Conventional technology]

The above-described frequency range detection apparatus controls the oscillation frequency of the local oscillator such that the intermediate frequency converted by detecting the shift of the intermediate frequency in a heterodyne receiver or the like is maintained within a set band. It is used to obtain control information for the AFC circuit.

By the way, taking the heterodyne type receiver as an example, conventionally, for example, the range of the input frequency is detected by an analog circuit.

In addition, as shown in FIG. 5, a low-pass filter (FIG. 5) for converting the input signal into a DC voltage using a frequency (f _if ) F / V converter (50) and removing a ripple of the DC voltage is used. After passing through 51), the converted DC voltage is converted by the analog window comparator (52) into a lower threshold (V ₁ ) corresponding to the lower limit of the set band and an upper threshold (V ₂ ) corresponding to the upper limit. , A pair of discrimination signals (T ₁ ) and (T ₂ ) corresponding to whether the signal is smaller than the lower threshold (V ₁ ) or larger than the upper threshold (V ₂ ). (See JP-A-55-23674).

[Problems to be solved by the invention]

However, in the above-mentioned conventional configuration, since it is of an analog type, it is susceptible to temperature fluctuations, and it is difficult to perform highly accurate detection. Further, there is a disadvantage that the long-term stability is low.

The present invention has been made in view of the above circumstances,
An object of the present invention is to provide a frequency range detection device that is not affected by temperature fluctuation.

[Means for solving the problem]

A first characteristic configuration of the frequency range detecting device according to the present invention is a counting means for counting the frequency of the input signal, and a count value of the counting means is a set band, a band lower than a lower limit of the set band, A determination unit that determines which band is higher than the upper limit of the set bandwidth; a storage unit that stores determination information of the determination unit; and the counting unit that is repeatedly initialized at a set cycle. And a gate pulse generating means for generating a gate pulse signal, wherein the storage means is configured to repeatedly update stored information in synchronization with the gate pulse signal.

Further, the second characteristic configuration is to specify a preferred mode when implementing the first characteristic configuration, wherein the counting unit includes a frequency dividing unit that divides a frequency of the input signal,
The gate pulse generating means includes a reference signal generating means and a frequency dividing means for dividing a reference frequency output from the reference signal generating means, and each of the frequency dividing means has a frequency dividing ratio. Is configured to be freely changeable.

(Operation)

In the first characteristic configuration, the frequency of the input signal is repeatedly counted for each cycle of the gate pulse signal, and the counted value is determined as a set band, a band lower than a lower limit of the set band, and the set band. Is determined, and the determination information is stored while being repeatedly updated in synchronization with the gate pulse signal.

In the second characteristic configuration, since the accuracy of the frequency range to be detected is determined by the resolution of the count value of the counting means, the input frequency is divided by the dividing means provided in the counting means, and By changing the frequency division ratio of the frequency dividing means, the resolution of the detection frequency range can be changed and set to a desired value. Since the response time required to complete the determination of the input frequency with respect to the set band is determined by the period of the gate pulse signal, the response time can be changed by changing the frequency division ratio of the frequency divider provided in the gate pulse generator. Thus, the response time required for frequency detection can be changed and set to a desired value.

〔The invention's effect〕

Therefore, in the first characteristic configuration, the detection of the frequency range is entirely performed by digital processing, so that it is possible to completely eliminate the influence of temperature fluctuation. Further, since the determination means determines the frequency range based on a numerical value, not only can the detection accuracy be set with high accuracy, but also the set value does not fluctuate with temperature, so that long-term stability is also high. .

In the second characteristic configuration, the response time of frequency range detection and the resolution of detection accuracy can be changed and set with high long-term stability and high accuracy.

〔Example〕

Hereinafter, an embodiment in which the present invention is applied to a receiver for satellite broadcasting will be described with reference to the drawings.

As shown in FIG. 2, a signal received by an outdoor antenna (1) is converted into a first intermediate frequency (f _in ) by a frequency converter (2) mounted on the antenna (1). , High frequency amplifier in receiver (3)
The signal is amplified by the mixer, and the amplified received signal and the oscillation frequency (f _L ) of the local oscillator (4) are mixed by the mixer (5) and converted into an intermediate frequency signal by the heterodyne method, and then the intermediate frequency amplifier (6) And demodulated by a demodulator (7) to obtain a demodulated signal (V ₀ ).

The local oscillator (4) maintains a high-precision oscillation frequency (f _L ) synchronized with a reference frequency (f _S ) oscillated by a crystal oscillator or the like by a frequency synthesizer circuit (8) using a so-called PLL circuit. It is configured as follows.

The frequency synthesizer circuit (8) includes a first frequency divider (9) for dividing the oscillation frequency (f _L ) of the local oscillator (4) and a second frequency divider for dividing the reference frequency (f _S ). And a first frequency divider (9) and a second frequency divider (1).
0), a phase difference detector (1
The local oscillator (4), comprising: (1) a low-pass filter (12) for integrating the output of the phase difference detector (11);
The voltage is controlled by the output signal of the reduction pass filter (12), so that the oscillation frequency (f _L ) of the oscillation frequency (f _L ) decreases the frequency division ratio (m) of the first frequency divider (9). Bowl (1
The frequency (m / n) divided by the frequency division ratio (n) of (0) is maintained at a frequency obtained by multiplying the reference frequency (f _S ).

That is, the intermediate frequency (f _if ) is configured to be the difference frequency (f _L −f _in ) between the oscillation frequency (f _L ) of the local oscillator (4) and the reception frequency (f _in ). -ing

However, in order to keep the intermediate frequency (f _if ) within the amplification band of the intermediate frequency amplifier (6) even _{if the} reception frequency (f _in ) changes, the first frequency divider (9) is used. ) Is based on channel selection information and information of a frequency range detection circuit (13) as a frequency range detection device for detecting a frequency range of the frequency (f _if ) of the intermediate frequency signal. It can be varied by the output of the operating division ratio setting circuit (14).

As shown in FIG. 1, the frequency range detection circuit (13)
Counts, as an input signal, a gate pulse generating means (100) for outputting a gate pulse signal (Cp) repeated at a set cycle, and a frequency (f _if ) of the intermediate frequency signal amplified by the intermediate frequency amplifier (6). Counting means (101);
First count value output from the counting means (101) to determine whether the intermediate frequency (f _{an if)} the set bandwidth (A ₁₎ or the lower limit of (FIG. 3 reference) (f ₁₎ from the lower Gate circuit (2
0), a second gate circuit (21) for determining whether or not the intermediate frequency (f _if ) is higher than an upper limit (f ₂ ) of the set band (A ₁ ); And a storage means (102) for storing the determination information of (21).

That is, the first gate circuit (20) and the second gate circuit (21) determine whether the intermediate frequency (f _if ) as the frequency of the input signal is within the set band (A ₁ ) or the lower limit value (f _1). ) Corresponds to the determination means for determining whether the frequency band is in the lower band and the higher band (f ₂ ).

The gate pulse generating means (100) is a reference oscillator (15) as a reference signal generating means using a crystal oscillator.
And a third frequency divider (16) as frequency dividing means for dividing a reference frequency output from the reference oscillator (15) by a set frequency division ratio (M), and the third frequency divider (16) And a gate pulse signal generator (17) for outputting a gate pulse signal (Cp) in synchronization with the output frequency.

The counting means (101) includes the intermediate frequency amplifier (6);
A fourth frequency divider (18) as frequency dividing means for _dividing the frequency (f _if ) of the intermediate frequency signal amplified by the above as an input signal by a set frequency dividing ratio (N), and the fourth frequency divider (18) And a counter (19) which counts the output frequency of (18) and is repeatedly cleared by the gate pulse signal (Cp).

The storage means (102) includes the first gate circuit (20)
And a pair of flip-flops (22) and (23) that operate using the output signal of each of the second gate circuit (21) as a clock signal and are repeatedly cleared by the gate pulse signal (Cp); (2
2) Output logic of (23) is changed to the gate pulse signal (Cp)
And a pair of latch flip-flops (24) and (25) that latch in synchronization with the flip-flops.

That is, the frequency range detection circuit (13) is basically configured to operate as a frequency counter, and as shown in Table I below, the input frequency (f
_if ) is lower than the lower limit (f ₁ ) or the lower limit (f ₁ )
And discrimination signals (T ₁ ) and (T ₂ ) as a pair of discrimination information corresponding to three states of being between the upper limit value (f ₂ ) and the upper limit value (f ₂ ). It is configured to output from a pair of latch flip-flops (24) and (25).

Since the frequency range detection circuit (13) is configured to process all signals digitally, it is possible to make the characteristics of the circuit not change due to a temperature change, a variation in components, or the like. Further, since all the signals are digitally processed, it is possible to easily form an LSI together with the respective circuits such as the frequency synthesizer circuit (8).

Next, based on the output signals (T ₁ ) and (T ₂ ) of the frequency range detection circuit (13), the frequency division ratio (m) of the first frequency divider (9) of the frequency synthesizer circuit (8) The operation for automatically adjusting is described.

The rated value of the intermediate frequency (f _if ), that is, the center frequency (f _if0 ) of the set band (A ₁ ), and the rated value of the reception frequency (f _if ), that is, the rating that becomes the center frequency (f _if0 ) The input frequency (f _if0 ) and the corresponding rated frequency division ratio (m ₀ ) are set so as to have a relationship shown in the following equation (i) based on channel selection information in the case of frequency conversion by the upper side heterodyne. You.

Therefore, the receiving frequency (f _if ) is equal to the rated input frequency (f _if ).
_If it shifts upward from ( _if0 ), the intermediate frequency (f _if ) becomes the shift frequency (Δf) as shown in the following equation (ii).
_The value ((f _if1 )) is lower than the center frequency (f _if0 ) of the intermediate frequency band by (if 0> 0).

Therefore, when said reception frequency (f _{an if)} rises the intermediate frequency (f _{an if)} falls below the lower limit value (f ₁₎ of the set bandwidth (A _1), the intermediate frequency (f _{an if)} The rated frequency division ratio (m ₀ ) is set based on the following equations (iii) and (iv) so as to change to a fourth threshold value (f ₂ ′) (where f ₁ <f ₂ ′ <f ₂ ). The value (p: a positive integer) is increased.

Similarly, when the reception frequency (f _in ) decreases and the intermediate frequency (f _if ) exceeds its upper limit (f ₂ ), the rated frequency division ratio (m ₀ ) is increased by a third value. The threshold value (f ₁ ′) (where f ₁ <f ₁ ′ <f ₂ ) and the upper limit value (f ₂ ) are set to positive integer values so as to satisfy the following equations (v) and (vi). That is, it is decreased by the set value (q).

The values of the third threshold value (f ₁ ′) and the fourth threshold value (f ₂ ′) are set to the center frequency (f _if0 ) of the intermediate frequency band (A ₁ ).
When the variable step width of the tuning frequency is set to be half of the width of the set band (A ₁ ) so as to be as close as possible to the above, the hysteresis width of the intermediate frequency (f _if ) is substantially vertically symmetrical and maximized. So that the intermediate frequency (f _if )
Can be minimized.

Incidentally, the case where the reception frequency (f _in) is the first channel BS as an example, specific values of the frequency and the division ratio be added the description, be a f _in0 = 1049.48MHz f _if0 = 402.78MHz , F ₁ = 402.63 MHz f ₂ = 402.93 MHz f ₁ ′ = f ₂ ′ = 402.78 MHz f _S = 4 MHz n = 128 m ₀ = 46472 From the equation (iv), P = 4.8 ≒ 5. From equation (iii), f ₂ ′ = 402.78625 MHz.

From equation (vi), q = 4.8 ＝ 5. Therefore, from equation (v), f ₁ ′ = 402.777375 MHz.

That is, the step width of the tuning frequency determined by the step width (p or q) for changing the division ratio (m) of the first frequency divider (9) By setting the intermediate frequency signal narrower than the bandwidth (f ₂ −f ₁ ) of the set band (A ₁ ), the lower limit value (f ₁ )
When 'a band between the third threshold value (f ₁ fourth threshold value (f _2)' to each of the bands between) and the upper limit value (f _2),
A state having hysteresis is established, and the intermediate frequency (f
_if ) becomes lower than the lower limit (f ₁ ), the actual intermediate frequency (f _if ) becomes the fourth threshold (f ₂ ′), and if it becomes higher than the upper limit (f ₂ ), the third threshold (f ₂ ) becomes higher. f ₁ ′), the division ratio (m) of the first frequency divider (9) is a combination of the logical values of the outputs (T ₁ ) and (T ₂ ) of the frequency range detection circuit (13). Is automatically changed at a step width corresponding to the set value (p or q).

Then, setting the third threshold value (f ') center frequency (f _if0) become as the set value of and the fourth threshold value (f _2') is the set bandwidth (A ₁₎ (p or q) When the variable step width of the tuning frequency is set to half or substantially half of the set band, the hysteresis width can be substantially vertically symmetrical and maximized.

(Another embodiment)

In the above embodiment, the intermediate frequency (f _if ) as the frequency of the input signal in the frequency range detection circuit (13) is within the set band (A ₁ ) or in a band less than the lower limit (f ₁ ). And whether it is in a band exceeding the upper limit value (f ₂ ).
Although the case has been exemplified in which the band of the stage is detected, for example, as shown in FIG. 4, the set band (A ₁ )
The band outside the lower limit value (f ₁ ) and the band outside the upper limit value (f ₂ ) may be divided into a buffer band and a band outside the buffer band so as to detect a deviation state outside the set band. Good.

Then, when the frequency deviation of the reception frequency (f _in ) is large, the tuning into the set band (A ₁ ) can be accurately performed while the pulling into the buffer band above or below the set band (A ₁ ) is accelerated. In order to achieve the above, the frequency division ratio (m) is roughly varied in a band above the upper buffer band or in a band below the lower buffer band, and is finely varied in the band. Good.

If you add the description, the set lower limit of the band (A ₁₎ (f ₁₎
And a fifth threshold value (f ₃ : f ₃ <f ₃ ) at both outer sides of the upper limit value (f ₂ ).
₁ ) and a sixth threshold (f ₄ : f ₂ <f ₄ ) are set, and the intermediate frequency (f _if ) is lower than the fifth threshold (f ₃ ) and the sixth threshold (f ₄ ) If high (the case intermediate frequency (f _{an if)} is in FIG. 4, a band indicated by a ₂ or a ₃₎
The intermediate frequency (f _if ) is set to the fifth threshold value (f ₃ ) and the sixth threshold value (f _4). ), It is possible to quickly and accurately follow a large change _{in the} input reception frequency (f _in ) due to channel selection.

As described above, the frequency division ratio (m) is roughly varied in a band above the upper buffer band or in a band below the lower buffer band, and is finely varied in the band. Also in the case of the configuration, when the intermediate frequency (f _if ) is in each of the upper and lower buffer bands, the variable step width of the frequency division ratio (m), that is, the variable step width of the tuning frequency is determined by the setting band (A _If it is set to half or substantially half of ₁ ), the hysteresis width can be substantially vertically symmetrical and maximized.

Further, in the above embodiment, the present invention is applied to a receiver for satellite broadcasting.
Although the case where the present invention is applied to the AFC circuit is illustrated, the present invention is applicable to various devices for detecting a frequency range. For example, the present invention is applicable to the frequency synthesizer circuit (8) and the frequency range detecting circuit (13). The present invention can also be applied to an inspection device or the like for inspecting or selecting the frequency of a crystal oscillator for generating a reference frequency to be used.

When applied to an inspection device, the third frequency divider (16) and the fourth frequency divider (18) can be arbitrarily changed and set using, for example, a programmable counter or the like. By doing so, the resolution of the detection accuracy and the response time of the detection operation can be changed and set according to the frequency of the crystal oscillator to be detected or selected.

Further, the specific configuration of each unit required for implementing the present invention can be variously changed.

In the claims, reference numerals are provided for convenience of comparison with the drawings, but the present invention is not limited to the structure shown in the attached drawings.

[Brief description of the drawings]

1 is a block diagram of a frequency range detection circuit, FIG. 2 is a block diagram of an overall configuration, FIG. 3 is an explanatory diagram of an intermediate frequency band, FIG. FIG. 4 is an explanatory diagram of an intermediate frequency band in another embodiment, and FIG. 5 is a circuit diagram showing a conventional configuration. (F _if ): Input signal frequency, (A ₁ ): Setting band,
(F ₁ ): Lower limit, (f ₂ ): Upper limit, (Cp): Gate pulse signal, (T ₁ ), (T ₂ ): Discrimination information, (100)
... gate pulse generation means, (101) ... counting means, (1
02) Storage means (15) Reference signal generation means (1
6), (18) ... frequency dividing means, (20), (21) ... discriminating means.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takashi Hirano 2-1 Nissincho, Neyagawa City, Osaka Prefecture Inside Onkyo Corporation (56) References JP-A-1-147378 (JP, A)

Claims (2)

(57) [Claims] 1. A counting means (101) for counting a frequency (f _if ) of an input signal, and a calculated value of the counting means (101) is set to a set band (A ₁ ) and a lower limit of the set band (A ₁ ). The band lower than the value (f ₁ ) and the upper limit (f ₂ ) of the set band (A ₁ )
Determining means for determining whether the one of the band of the upper band than (20), and (21), the determination means (20), (21) discrimination information (T _1), storing (T ₂₎ Storage means (102)
And a gate pulse generating means (100) for generating a gate pulse signal (Cp) for repeatedly initializing the counting means (101) at a set period, and the storage means (102) stores the gate pulse signal (Cp) A) a frequency range detecting device configured to repeatedly update the stored information in synchronization with the frequency information. 2. The frequency range detecting device according to claim 1, wherein said counting means (101) is configured to control the frequency (f) of the input signal.
_if ) is provided, and the gate pulse generating means (100) is provided with a reference signal generating means (15).
And a frequency dividing means (16) for dividing the reference frequency output from the reference signal generating means (15). Each of the frequency dividing means (16) and (18) has a frequency dividing ratio. Is a frequency range detection device configured to be able to change and set.