JP2621500B2 - CPU data communication processing method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication processing method of a CPU that performs predetermined processing and performs data communication with an external device.

2. Description of the Related Art It is common to perform data communication serially in order to reduce the number of CPU terminals when performing data communication with an external device. For example, when serially reading 1-byte data from an external device, eight serial transfer clocks are sent from the CPU to the external device, and the serial transfer is sequentially performed from the external device in response to the serial transfer clock. It is common practice to read bytes of data into a serial register in the CPU and read them in parallel in a batch.

In this case, the CPU is provided with a timer that counts the time required from the start of clock output to the end of reading one byte of data into the serial register. The CPU was in a standby state during the period required for the transfer. That is, considering the processing time of the CPU as a whole, this waiting period was useless because no other processing was performed.

An object of the present invention is to provide a data communication processing method of a CPU that can save such useless time.

SUMMARY OF THE INVENTION The present invention provides a serial communication interface which outputs a serial communication clock in response to a command from a main routine, and generates an interrupt request when the clock is output by the number required for serial communication. And an interrupt routine for stopping output of the clock in response to the interrupt request and performing interrupt processing for data communication.

The interrupt processing for data communication is performed after the clock output command of the main routine is output for one byte of clock. Until that time, the main routine performs predetermined processing.

Embodiment An embodiment in which the present invention is applied to a camera will be described below. FIG. 1 is a block diagram showing the overall configuration of the camera according to the present embodiment. In this embodiment, a focal plane shutter camera having an automatic focus adjustment (hereinafter, referred to as AF) function and an automatic film winding function and transferring data to a detachable interchangeable lens and a flash will be described as an example. . In the figure, a camera body mainly includes an AF circuit (2) in addition to a CPU (1) as a camera control unit.
Film sensitivity output section (3), exposure mode setting section (4),
It comprises a photometric circuit (5) and a display circuit (6). CPU
(1) is a one-chip microcomputer having a built-in RAM, which controls AF, photometry, calculation, display, exposure control (AE), film winding, and the like.

The AF circuit (2) uses a CC as a focus detection line sensor.
A D / CCD drive unit and A / D conversion unit are provided, and operations such as start and end of CCD charge accumulation (integration) and digitalization of CCD output (analog) are performed by control signals from the CPU (1). . The film sensitivity output unit (3) automatically reads the film sensitivity printed in the form of a DX code on the film container and outputs the film sensitivity to the CPU (1). Exposure mode setting section (4)
Outputs the shutter speed, aperture value, and exposure control mode (program, shutter priority, aperture priority, etc.) manually set by the operation member to the CPU (1). These circuits (2), (3) and (4) communicate data with the CPU (1) via dedicated data buses.

On the other hand, although details will be described later, the photometric circuit (5) and the display circuit (6) are connected to the CPU (1) via a common data bus together with the lens circuit (7) of the interchangeable lens and the flash circuit (8) of the flash device. Are configured to perform data communication sequentially.

Switch SW ₁ is ON at the initial stage of shutter button pressing operation
Signal for performing focus detection and photometric operation.
A photographing preparation switch which gives to the interrupt input terminal IP ₁ of CPU (1). Switch SW ₂ is a release switch which provides a signal for causing the shutter release operation and ON at the final stage of the pressing operation of the shutter button to the interrupt input terminal IP ₂ of CPU (1). Switch SW ₃ is an aperture encoder switch for generating a number of pulses corresponding to the narrowing of the open aperture. Switch SW ₄ is turned on when the main mirror is moved up, and turned off when the film winding operation is completed.
This is a winding state detection switch.

The power-on-clear circuit is composed of a series connection of a resistor and a capacitor, and the midpoint of the connection is connected to the reset terminal (RESET) of the CPU (1).

Magnet RMg is a release magnet for starting the shutter release in response camera to a control signal from the output terminal OP ₁ of CPU (1). Magnet FMg is an aperture magnet for stopping the narrowing operation of the diaphragm in response to a control signal from the output terminal OP ₂ of CPU (1). Magnet (1CM
g) and (2CMg) an output terminal of the _{CPU (1) (OP 3)} , (OP 4)
This is a shutter control magnet that starts traveling of the front curtain and rear curtain of the focal plane shutter in response to a control signal from the shutter.

The winding circuit output terminal of the _{CPU (1) (OP 6)} , drives the motor M ₁ for to film winding and shutter charging in response to a control signal (OP _7). Lens drive circuit is CPU
In response to the control signals of the output terminals (OP ₈ ) and (OP ₉ ) of (1)
Drives the AF motor M _2.

Next, a circuit configuration for data communication between the CPU (1) and the photometric circuit (5), the display circuit (6), the lens circuit (7), and the flash circuit (8) will be described. First, CP
U (1) includes the CPU (1) from these circuits (5) to (8).
Or a serial interface SCI including a serial register for temporarily storing data serially transferred from the CPU (1) to these circuits (5) to (8).
And a RAM in which data temporarily stored in the serial interface SCI is stored as software. still,
The detailed structure of the serial interface will be described later with reference to FIG. Output terminal OP ₁₁ ~OP ₁₄ of CPU (1) is provided for to specify a circuit to perform a serial transfer,
The circuit corresponding to the terminal that has output the "L" level signal is selected. Here, the output terminal OP ₁₁ is a lens circuit (7)
The output terminal OP ₁₂ is connected to the flash circuit (8) and the output terminal
OP ₁₃ in the display circuit (6), the output terminal OP ₁₄ are connected to the photometry circuit (5). Incidentally, a flash circuit (8) is turned perform so both data transmission and reception between the CPU (1), or be one of the transmit and receive in accordance with the output level of the output terminal PO ₁₀ is It is determined. Specifically from the flash circuit when the output terminal OP ₁₀ is "L" level (8) will receive data to CPU (1), "H" from the CPU (1) when the level to the flash circuit (8) Is received.

FIG. 2 is a circuit diagram showing a specific configuration of the serial interface. In the figure, the serial clock SCK ₁ a reference frequency by dividing the CPU (1) is used to synchronize the serial data transfer, this clock each as logical SCK ₂ the output terminal OP ₅ by the AND gate Circuits (5) to (8) are provided. That is, the output terminal OP ₅ is transmitted only from CPU (1) when the "H" level of the serial clock SCK ₂ is permitted. Also, the above serial clock
SCK ₁ is input to an octal counter in the serial interface, and the carry output of the counter is used as a serial interrupt signal described later. Incidentally, the serial interrupt signal is output when the serial interrupt is in the authorized state, as described later, the output of the serial clock SCK ₁ is software-configured to automatically stop.

These serial clock SCK ₁ , terminal OP ₅ , logical product SC
The relationship between K ₂ and the serial interrupt signal is shown in the timing chart of FIG. The operation of this embodiment will be described with reference to this timing chart and the flowcharts of FIGS.

FIG. 4 shows a flow of a battery mounting routine by an interrupt when the input level to the reset terminal RESET rises from "L" to "H" by a known power-on clear circuit when the battery is mounted.

When an interrupt is applied, the step (# 1) performs the clearing of PAM in CPU (1), the resets the metering flag (described later), the OP ₁₄ to "H" from the output terminal OP _10, the output terminal OP ₁
To make OP ₄ "L".

Next step (# 2) is prohibited once all interrupts, step permits activation interrupt by ON photographing preparation switch SW ₁ in (# 3), the CPU standby state.

Thereafter, when the photographing preparation switch (SW ₁ ) is turned on, the main routine shown in FIG. 5 is started. In this main routine, the AF control is executed with priority. In the main routine, first, the photometry flag is reset in step (# 10). The photometry flag changes from “0” to “1” when the serial transfer shown in Table 1 below is completed once.
The flag is switched to. Next, in step (# 11), 0 is substituted as a serial code. The main routine is AF
The serial code is used to specify the order of the processes when performing a plurality of types of control for the AE calculation and the like in the interrupt process. There are serial codes 0 to 4, each of which processes a routine as shown in Table 1.

In step (# 12), the CCD in the AF circuit (2) is initialized. In step (# 14), the serial start subroutine shown in FIG. 6 is executed. Hereinafter, the subroutine shown in FIG. 6 will be described.

Step a (# 100), the terminal OP ₁₁ to "L" choose lenses circuit (7) as a target of serial data communication with.
In step (# 11), the CPU (1) stores various 8-bit lens data (open aperture value, minimum aperture value, focal length, lens adjustment conversion coefficient for focusing, etc.) stored in the ROM in the lens. In the register IX, the storage start address to be taken into the RAM in the RAM is entered. In step (# 102), the number of lens data to be captured is entered in the register IY.

In step (# 103), to the terminal OP ₅ "H". As a result, the AND gate becomes active. At this time, the clock pulse SC for serial transfer is supplied to the lens circuit (7).
K ₁ is not supplied.

Next, a serial interrupt is permitted in step (# 104), and serial transfer is started in step (# 105). That is, the data of the external circuit is taken into the serial register in the serial interface SCI through the terminal SIN (however, OP ₅ = H), or the data in the serial register is sent to the external circuit through the terminal SOUT (however, OP ₅ =
H) or, alternatively, make latency AF operation priority action (except the OP ₅ = L) for starts outputting the clock pulse signal SCK _1. Then, the process returns in step (# 106) and returns to the flow in FIG.

Returning to FIG. 5, in step (# 15), integration of the CCD in the AF circuit (2) is started. Then, after waiting for the completion of the integration in step (# 106), the CP in step (# 17)
Import CCD data into U (1). In step (# 18), the amount of defocus (amount of defocus) and the direction are calculated based on the captured CCD data. In step (# 19), it is determined whether or not the defocus amount is within the allowable focusing range (that is, focusing).
In step 20), the subroutine of the relay permission determination shown in FIG. 7 is executed. If not in focus, the motor (M ₂ ) is driven toward the in-focus position based on the defocus amount and direction of the calculation result in step (# 21).

Hereinafter, the subroutine shown in FIG. 7 will be described.

In step (# 50), it is determined whether the photometry flag is 0 or 1 (all of the routines shown in Table 1 have been performed at least once). If it is 0, it means that all the routines in Table 1 are being processed, so that the routine returns and returns to the flow of FIG. On the other hand, if the photometric flag is 1 proceeds to step (# 51), to allow the release interruption by ON of the release switch (SW _2), the process returns. That is, unless each routine shown in Table 1 is performed at least once, the shutter is not released even if the release switch (SW ₂ ) is turned on.

Returning to FIG. 5, it determines whether it remains in the photographing preparation switch (SW ₁₎ is still ON at step (# 22). ON
If it remains, AF from step (# 15) to (# 21)
Repeat the operation. On the other hand, if it is OFF, the process proceeds to step (# 23), and if the AF motor (M ₂ ) is being driven, the motor drive is stopped. Thereafter, the step (# 1) shown in FIG.
Jump to CPU standby state.

The interrupt processing when a serial interrupt occurs during the operation of the flow shown in FIG. 5 will be described with reference to FIGS. 8 to 13 and 6.

When the serial interrupt occurs by serial black Tsu SCK ₁ in step # 105 is eight outputs, the flow shown in FIG. 8 is executed. First, in step (# 110), the serial interrupt is prohibited to prevent malfunction, and in step (# 11)
In step 1), the value of the serial code is determined, and a processing routine corresponding to the serial code shown in Table 1 is executed. Here, when the serial code is 0, the read lens process shown in FIG. 9 is executed.

In the lead lens processing shown in FIG.
0) in the terminal OP ₅ determines whether "L" or "H", the flow proceeds to step (# 121). If "H". Step back (# 121) in the terminal OP ₅ to "L", and jumps to step step FIG. 6 with (# 122) (104). As a result, the fifth
The processing time of the main routine shown in the figure is secured.

On the other hand, if the terminal OP ₅ is "L", the flow proceeds to step (# 123), is designated the lens data transferred to the serial register from the lens circuit (7) by the register IX
Transfer to RAM address. Next, in step (# 124), the next address is entered into the register IX (IX is incremented by 1), and in step (# 125), the number of data not yet transferred to the RAM is entered into the register IY (IY is decremented by 1) ).

In step (# 126), the number of data in the register IY is 0
It is determined whether or not all the lens data has been transferred to the RAM. If the number of data in the register IY is not 0, the process jumps to the step (# 103) in FIG. 6 to continue the transfer of the next lens data. Register IY
If it is 0, because the transfer of all the lens data has been completed, and the terminal OP ₁₁ to "H" at step (# 128),
Stop specifying the lens circuit (7), this time in the "L" terminal OP ₁₂ in step (# 129), selects a flash circuit (8).

In step (# 130), the flash data (guide number information, charging completion information, dimming confirmation information, etc.) stored in the flash circuit (8) is stored in the RM of the CPU (1).
Into the register IX. In step (# 131), the number of flash data is stored in the register IY. In step (# 132), the serial code
And jumps to the step (# 103) in FIG. 6 to start the serial transfer of flash data to the CPU (1).

When the serial code is 1, the read flash processing shown in FIG. 10 is executed. First, step (# 140) at the terminal OP ₅ determines whether "L" or "H", and jumps to step ninth diagram If "H"(# 121).

On the other hand, if the judgment in step (# 140) is "L",
RAM specified by register IX in step (# 142)
The flash data stored in the serial register is transferred to the address. Thereafter, the register IX is incremented in step (# 143), and the register IY is decremented in step (# 144).

Next, in step (# 145), the data of the register IY is set to 0.
It is determined whether or not it is not 0.
Jump to 103) to continue the transfer of the next flash data. If the determination in step (# 145) is 0, the transfer of all the flash data has been completed, so step (# 145)
148) Set the terminal OP ₁₂ to “H” to set the flash circuit (8)
Quit that you select, this time to select the metering circuit (5) in the "L" terminal OP ₁₄ in the step (# 147).

In step (# 149), the address for storing the photometric data in the RAM is entered in the register IX, and the step (# 150)
Use to enter the number of photometric data into register IY. Next, in step (# 151), 2 is entered into the serial code, and the process jumps to step (# 103) in FIG.
Start serial transfer to (1).

When the serial code is 2, the lead photometry process shown in FIG. 11 is executed. First, step (# 160) at the terminal OP ₅ determines whether "L" or "H", and jumps to step ninth diagram If "H"(# 121).

If the determination in step (# 160) is "L", in step (# 164), the data stored in the serial register is transferred to the address in the RAM specified by the register IX.
Then, the register IX is incremented in step (# 165), and the register IY is decremented in step (# 166). Next, in step (# 167), it is determined whether the data in the register IY is 0. If not, the process jumps to step (# 103) in FIG. 6 to continue the serial transfer of the next photometric data.

Step For the determination in (# 167) 0, stop selecting a photometric circuit (5) to the terminal OP ₁₄ to "H" at step (# 169).

In step (# 170), exposure calculation is performed based on the photometric data stored in the RAM and the information input from the terminals IPA and IPB, and the aperture value, shutter speed, and the like are determined. The calculation result is stored in the RAM.

Next, step (# 171) to select the flash circuit (8) to the terminal OP ₁₂ to "L", the step (# 172) in the flash circuit terminals OP ₁₀ from CPU (1) in the "L" ( 8) Transmission is selected.

In step (# 173), the address of the RAM storing the data to be transferred to the flash circuit (8) (for example, the aperture value and the focal length) is stored in the register IX. In step (# 174), the number of data to be transferred to the flash circuit (8) is entered in the register IY. Step (# 17
In 5), 3 is added to the serial code, and the process jumps to step (# 103) in FIG. 6 to start transferring flash data to the flash circuit (8).

When the serial code is 3, the write flash processing shown in FIG. 12 is executed. First, step (# 180) at the terminal OP ₅ determines whether "L" or "H", if the "H", the flow proceeds to step (# 181), if the "L" Step (# 1
Go to 85).

In step (# 181), the data at the address IX on the RAM is transferred to the serial register. Then, step (# 18
Step of incrementing register IX in 2) (# 18)
In 3), the terminal OP ₅ to "L", the steps of FIG. 6 (#
Jump to 104). On the other hand, if the judgment in step (# 180) is "L", in step (# 185) the register IY
Is decremented. In the step (# 186), it is determined whether or not the data of the register IY is 0.
The process jumps to the step (# 103) in the figure to continue the transfer of the next flash data.

Step For the determination in (# 186) 0, the terminal OP ₁₀ to "H" in so all the data to the flash circuit (8) transfer is completed step (# 188), the step (# 1
89) In the terminal OP ₁₂ to "H", the step (# 190), the terminal OP ₁₃ to "L". This completes the process of transferring data to the flash circuit (8), and selects the display circuit (6).

Next, in step (# 191), the RAMk address storing the display data to be transferred to the display circuit (6) is stored in the register IX.
Do you put in Then, in step (# 192), the number of data is entered into the register IY, and in step (# 193), 4 is entered in the serial code, and the process jumps to step (# 103) in FIG.

When the serial code is 4, the light display processing shown in FIG. 13 is executed. First Step pin (# 200) OP _5, it is determined whether "L" or "H", and jumps to step Figure 12, if "H"(# 181). When the judgment at step (# 200) is "L", the register I is set at step (# 202).
Decrement Y. Then, in step (# 203), it is determined whether or not the data in the register IY is 0. If not, the process jumps to step (# 103) in FIG. 6 in step (# 204) to transfer the next display data. continue.

On the other hand, the step when the judgment is 0 in (# 203), quit selecting a display circuit in the "H" terminal O ₁₃ in step (# 205), the 0 to the serial code in step (# 206) Put in. Then, at step (# 207), 1 is set to the photometry flag, and the routine jumps to step (# 100) in FIG.

 This concludes the description of the serial interrupt.

If the relay switch (SW ₂ ) is turned on while the release permission is issued in step (# 20) while the flow shown in FIG. 5 is being executed, a release interrupt occurs, and FIG. Is executed. First, in step (# 300), OP _{1 is set} to “H”, and the release magnet (RM
g) to start the mirror-up or aperture operation.

In step (# 306), the aperture encoder switch (S
The number of pulses by ON / OFF of W ₃ ) is counted, and it is waited that the counted value becomes a value corresponding to the aperture value calculated by the exposure calculation in step (# 170) in FIG.
At 7), the terminal OP _{2 is set} to “H”, and the aperture is fixed according to the calculation result by the aperture stop magnet (FMg). In step (# 308), the process waits for the time (ΔT ₂ ) until the raised mirror or the fixed aperture stabilizes.

In step (# 309), and the terminal OP ₃ to "H", is first run the shutter front curtain. And the step (#
After waiting for the shutter opening time corresponding to the shutter speed in 310), the terminal OP _{4 is set} to “H” in step (# 311).
And the exposure is completed by running the rear curtain of the shutter.

Then, after driving the motor (M _1), winding etc. is performed and shutter charge, step winding state detecting switch (# 323) (SW ₄₎ is waiting to OFF in step (# 322), in step (# 324) stops driving the motor (M _1).

In step (# 325), from the terminal OP ₁ terminal OP ₄ to "L", and jumps to step (# 10) of FIG. 5.

Effects As described above, according to the present invention, the serial interface is assigned the time from when the main routine instructs the start of transmission of the serial communication clock to when the clock for one byte is transmitted, and during this period, the main routine is executed. Since the predetermined processing is continued, the processing time of the entire CPU can be reduced, and a conventional timer for counting the standby time is not required, so that the utilization efficiency of the CPU can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall circuit configuration of an embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of a main part thereof, FIG. 3 is a time chart showing the operation of the configuration of FIG. FIGS. 4 to 14 are flowcharts showing the operation of the CPU of FIG. 1: CPU SCI: Serial interface # 10 to # 23: Main routine # 110 to # 111: Interrupt routine

Claims (1)

(57) [Claims] A CPU for performing predetermined processing and performing data communication with an external device operates in response to a command from a main routine to generate a serial communication clock for performing the data communication serially. A serial interface that includes a clock output unit to output and an interrupt generation unit that generates an interrupt request when the serial communication clocks are output by the number required for serial communication of data; An interrupt routine for stopping the output of the serial communication clock in response to the interrupt and performing an interrupt process for data communication, wherein the data communication is performed by the serial interface and the interrupt routine. Data communication method.