JP2617037B2 - Communication control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a communication control equipment in the case of transmitting and receiving data in time-division multiplex system in the communication control device.

[0002] With the recent increase in computer networks, high-speed and large-volume data transfer and high reliability of data transfer are required. For this reason, high-speed and large-volume data transfer must be realized by using ISDN (Integrated Digital Service Network), and communication controllers must be multiplexed to maintain high system reliability. In this case, a plurality of communication control units must handle the same data, and it is necessary to maintain consistency of data and communication control of this system.

[0003]

2. Description of the Related Art FIG. 5 is a diagram showing an example of a frame format by time slot multiplexing. In the figure, one frame is divided into a plurality of time slots TS1 to TSn, and each time slot serves data for one line. That is, in the example shown in the figure, a line having a multiplicity of n is configured. The line address of each frame is assigned, for example, such that TS1 is # 1 and TS2 is # 3 (the number of the time slot TS and the line address number do not always match. Sometimes addresses are assigned.)

As described above, on the transmitting side, data of n lines is divided and multiplexed and transmitted in one frame. On the receiving side, the multiplexed time slots are separated and stored for each line.
By repeating the transfer of one frame data a required number of times, all data can be transferred for each line. That is, all data for one line can be constructed from a set of data for each line separated on the receiving side.

FIG. 6 is a block diagram showing a configuration example of a conventional communication control device 10. As shown in FIG. In the figure, 1 is a channel for receiving data from a computer, 2 is a line controller for controlling the procedure of an ISDN line, and 3 is a time slot controller for associating a time slot with a line address. The line control unit 2 and the time slot control unit 3 have a duplex configuration of the 0 system and the 1 system.

Reference numeral 4 denotes a control unit for controlling the line control unit 2 and the time slot control unit 3, and reference numeral 5 denotes a transformer for interfacing a line network with a communication control unit. As the control unit 4, for example, a microprocessor is used. The operation of the device configured as described above will be described below.

[0007] The parallel data input from the computer enters the line control unit 2 via the channel 1. Line control unit 2
Converts the parallel data input under the control of the control unit 4 into serial data. The time slot control unit 3
The serial data provided from the line control unit 2 is time slot multiplexed for each line. The multiplexed frame format is as shown in FIG.

The time slot multiplexed data enters the transformer 5 from the time slot control unit 3 and is transmitted from the transformer 5 to the line network. Here, the series of operations described above are performed in the same manner by the line control unit 2 and the time slot control unit 3 of the 0 system and the 1 system, but the control unit 4 specifies the active system and the standby system. If it is assumed that the system 0 is specified, the multiplexed data is transmitted from the time slot control unit 3 of the system 0 to the line network.

[0009]

During the series of operations described above, both the 0-system and 1-system line control units 2 and the time slot control unit 3 hold the same data. Now, when the system 0 is operating in the active system, the time slot control unit 3
When a change occurs in one of the plurality of lines managed by the control unit 4, the control unit 4 must always reflect the change to the time slot control unit 3 of the first system.

When at least one of the plurality of lines managed by the time slot control unit 3 of the system 0 is abnormal, all the lines managed by the time slot control unit 3 and the line control unit 2 Line management 1 is the standby system
The system is switched to the line controller 2 and the time slot controller 3 of the system. During this switching timing, the operation of the normal line also stops.

Therefore, when a change occurs in the line managed by the time slot control unit 3 of the 0 system, the other system (1 system)
The time slot control unit 3 must always reflect the change, and the exchange of information between the time slot control unit 3 and the microprocessor 4 increases.
When an abnormality occurs in a line, all the lines on the time slot control unit 3 that manages the line must be switched to the time slot control unit 3 in the standby system, which affects the normal line. There was a problem that would.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has been made in consideration of the effects of a change in a line or a line failure. and its object is to provide a communication control equipment which can be achieved.

[0013]

FIG. 1 is a block diagram showing the principle of the present invention. The same components as those in FIG. 6 are denoted by the same reference numerals. In the figure, reference numeral 3 denotes a duplicated time slot control unit for associating a time slot with a line address, and reference numeral 2 denotes a duplicated line control unit for performing procedure control of an ISDN line. A control unit 4 controls the time slot control unit 3 and the line control unit 2.

Reference numeral 11 denotes a management table provided in the time slot control section 3 for associating a time slot number with a line address and adding a flag indicating the validity / invalidity of each time slot.

[0015]

When a fault occurs in the line address of the own system, when a line disconnection instruction is given from the control unit 4, or when a line invalidation instruction is given from another system, the management table 11 is referred to and a corresponding operation is performed. Time slot flag (E flag)
Configure to disable.

FIG. 2 is a diagram showing a configuration example of the management table 11. 20 is a time slot number, 21 is an E flag,
22 is a line address. This management table 11 is 0
It is provided in both the system and the time slot control unit 3 of the first system. The E flag 21 is set to “1” when the time slot is valid, and is set to “0” when the time slot is invalid.

The time slot control units 3 of the system 0 and the system 1
The validity / invalidity of time slots is managed for each time slot. Therefore, the time slots TSi of the system 0 and the system 1
Are not both "1" at the same time. If a failure occurs in the currently used time slot TSi, the time slot control unit 3 notifies the control unit 4 of the line address, and invalidates all time slots assigned to this line address. Therefore, only valid lines are transmitted from the time slot control unit 3.

In this way, the validity of the time slot
Since the invalidation is managed not for one time but for each time slot, the line in which an abnormality has occurred is disconnected, but the other normal lines are not affected.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 3 is a block diagram showing a main part of an embodiment of the present invention, showing an interconnection state of the time slot control unit 3. As shown in FIG. 1 are denoted by the same reference numerals. In the figure, 11 is the management table described above,
It is provided for each time slot, and comprises an E flag indicating whether this time slot is currently used and a corresponding line address when the time slot is used.

Reference numeral 12 denotes a line address table. When a line disconnection instruction, a hardware failure, or a line invalidation instruction from the control unit 4 is given from another time slot control unit 3, a flag of a corresponding line ( D flag). That is, "1" is set to the D flag corresponding to a line having a failure or the like. The line address table 12 is composed of a line address 12a and a D flag 12b as shown in the figure.

An OR gate 13 supplies a line address invalid signal to the line address table 12. The input of the OR gate 13 includes a hardware failure signal in the own system,
A line disconnect instruction signal from the control unit 4 and a line invalid signal from another system are included. Reference numeral 14 denotes a failure detecting unit that detects the occurrence of a hardware failure in the own system.

Reference numeral 15 denotes a line assignment circuit for associating a line address with a time slot number when a line connection request is received from the control unit 4. The line allocating circuit 15 is connected to the management table 11, and the line allocating circuits 15 notify each other of the time slot use status. Further, the line allocation circuit 15 receives a time slot sequence signal from the line network, and outputs a line invalidation instruction signal to notify the OR gate 13 of the other system.

Reference numeral 16 denotes a comparison circuit, and the management table 11
Line address currently used and line address table 1
2 is compared with the line address in which the D flag is set, and if the addresses are the same, the management table 11
The E flag of the corresponding time slot number is reset (set to "0"). At this time, if the same line address is assigned to a plurality of TSs, all the E flags are reset. The operation of the circuit configured as described above will be described below.

When a time slot sequence indicating which time slot is currently being executed is received from the line network, and a line connection request is issued from the control unit 4 to the time slot, the line allocation circuit 15 The control unit 3 confirms from the time slot use signal that no line is assigned to the same time slot number.

Thereafter, a line is allocated to the time slot. The line is allocated by assigning the line address 22 (see FIG. 2) to the time slot 20 in the management table 11.
And setting the E flag 21 (setting "1"). As a result, the time slot control unit 3 uses the assigned time slot to transfer the data of the corresponding line address. If the time slot has already been used, a line invalidation instruction is issued to the time slot control unit 3 using the time slot.

When a circuit disconnection request is detected from the control unit 4 while the circuit is operating, a line invalidation instruction is notified from the time slot control unit 3 of another system, or the internal failure detection unit 14 When a hardware failure is detected, the OR gate 13 notifies the line address table 12 of an abnormal signal. As a result, the corresponding D flag 12b of the line address table 12 is set to "1".

The state of the D flag is notified to the comparison circuit 16. If the line address in which the D flag is set is equal to the line address in the current management table 11 selected by the time slot sequence and the E flag is set, the comparison circuit 16
Reset the flag to “0”. Such abnormalities occur
The final state of the management table 11 in the case where
You. The state of the management table 11 in the final state is the line
Is normal, the system 0 differs from the system 1. In other words, the figure
2, line address # 1 is assigned to time slot TS
When assigned to 1 and operating, for example,
The E flag becomes “1” and the E flag of the 0 system becomes “0”.
If the line address # 3 is abnormal, the corresponding
The E flag becomes “0”.

As described above, according to the present invention, when a line connection request is issued for a time slot that has already been used, a line invalidation instruction is issued for that line. The current line is disconnected and the latest instruction is always valid. Further, when the line is not used due to a line invalid instruction, a line disconnection request, or a hardware error, the E flags of all time slots having the same line address are reset. Sex can be guaranteed.

Therefore, in the communication control device using the above-described method, it is not necessary to have exactly the same data in both the 0-system and the 1-system, and the load on the control unit 4 can be reduced. . Also, if an error occurs on the line
Is notified of an abnormal signal to the line address table 12,
The corresponding D flag is set to “1” and the management
The corresponding E flag in the cable 11 is reset,
The slot controller 3 passes the line address to the controller 4.
Know. Then, the control unit 4 starts the operation when the abnormality occurs in the line.
Issue an instruction to switch the current system to another system.
With reference to the management table 11, the
Data transfer .

In the above-described embodiment, the case where two time slot control units 3 exist is shown, but the present invention is not limited to this, and three or more time slot control units may exist. In this case, it is necessary to configure the management table 11 so that each time slot is at least duplicated. Further, in the above-described embodiment, the case where the line address number and the time slot number correspond one-to-one is shown, but as shown in FIG. 4, a plurality of time slots are assigned to one line address. It may be.

FIG. 4 shows an example in which two time slots, TS1 and TS2, are assigned to the same line address # 1. This is effective for increasing the number of data that can be transferred for each line.

[0033]

As described above in detail, according to the present invention, the validity / invalidity is controlled in units of a plurality of time slots constituting one frame in the time slot control section constituting the duplex system. A communication control device that can realize a multiplex system without affecting the effects of a line failure without affecting other normal lines.
It is possible to provide a location.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a management table.

FIG. 3 is a configuration block diagram showing a main part of one embodiment of the present invention.

FIG. 4 is a diagram illustrating another configuration example of the management table.

FIG. 5 is a diagram showing an example of a frame format by time slot multiplexing.

FIG. 6 is a block diagram illustrating a configuration example of a conventional device.

[Explanation of symbols]

 2 line control unit 3 time slot control unit 4 control unit 10 communication control device 11 management table

Claims (2)

(57) [Claims] 1. A duplex time slot control unit for allocating a line address to one or a plurality of time slots.
If a duplexed line control unit performs a procedure control times line, a communication controller with said time slot control unit and a control unit for controlling the line control unit, to the time slot control section, a time slot number and with associating the line address, the management table marked with a flag indicating the valid or invalid for each of the time slot
And Le, when the own system line disable instruction from or otherwise based, or the control unit by Ri line disconnection instruction failure is given to the line address is given, with reference to the management table, the line Means for invalidating a flag of a time slot to which a failed, disconnected, or invalidated line address is assigned.
Communication control equipment, characterized by comprising. Wherein said time slot control unit assigns a plurality of time slots in one line address, according to claim 1, characterized in that to perform the flag processing using the management table communication control equipment.