JP2617023B2 - Input buffer circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input buffer circuit.

[Conventional technology]

2. Description of the Related Art In recent years, the development of semiconductor integrated circuit devices has been remarkable, and the input buffer circuit of the integrated circuit is an important circuit part that receives an external input signal and determines the operation inside the circuit.

FIG. 2 (a) is a circuit diagram of a conventional input buffer circuit, and FIG. 2 (b) is a signal waveform diagram of the input buffer circuit of FIG. 2 (a).

2 (a) and 2 (b), Qp21 to Qp24 are P-channel MOS transistors, Qn21 to Qn24 are N-channel MOS transistors, A is an input signal, B is an output signal, and N21.
N23 is a node, VCC is a power supply voltage, VSS is a ground voltage, and ICC is a power supply current. This input buffer circuit is a circuit in which NOT circuits are connected in four stages.

The operation of the input buffer circuit will be described with reference to FIGS. 2 (a) and 2 (b).

First, when the input signal A is at the logic voltage “H” (high level), the P-channel MOS transistor Qp21 is off,
Since the N-channel MOS transistor Qn21 turns on,
The node N21 is at the logic voltage “L” (low level). Then, the P-channel type MOS transistor Qp22 is turned on,
Since the channel type MOS transistor Qn22 is turned off, the node N22 becomes the logic voltage “H”. Then, since the P-channel type MOS transistor Qp23 is turned off and the H-channel type MOS transistor Qn23 is turned on, the node N23 becomes the logic voltage "L". And the P-channel type MOS transistor Q
Since p24 turns on and the N-channel MOS transistor Qn24 turns off, the output signal B becomes the logic voltage "H". At this time, since no through current flows between the power supply voltage VCC and the ground voltage VSS, the power supply current ICC is very small.

Next, when the input signal A is at an intermediate level between the power supply voltage VCC and the ground voltage VSS, the P-channel type MOS transistor Q
Since both p21 and the N-channel MOS transistor Qn21 are turned on, the node N21 is at an intermediate level. And
P-channel type MOS transistor Qp22 and N-channel type M
The node N2 is turned on together with the OS transistor Qn22.
2 is also an intermediate level. Further, since both the P-channel MOS transistor Qp23 and the N-channel MOS transistor Qn23 are turned on, the node N23 is at the intermediate level. Then, a P-channel type MOS transistor Qp24 and N
Since both the channel type MOS transistor Qn24 is turned on, the output signal B has an intermediate level, and its output value is not determined. At this time, a through current flows between the power supply voltage VCC and the ground voltage VSS, and the power supply current ICC increases.

Next, when the input signal A is at the logic voltage "L", the P-channel MOS transistor Qp21 is turned on and the N-channel MOS transistor Qn21 is turned off, so that the node N21 is at the logic voltage "H". Then, the P-channel type MOS transistor Qp22 is turned off, and the N-channel type MOS transistor Qp22 is turned off.
Since n22 is turned on, the node N22 becomes the logic voltage “L”.
Then, the P-channel MOS transistor Qp23 is turned on and the N-channel MOS transistor Qn23 is turned off, so that the node N23 is at the logic voltage “H”. Then, the P-channel MOS transistor Qp24 is turned off and the N-channel MOS transistor Qn24 is turned on, so that the output signal B becomes the logic voltage "L". At this time, no through current flows between the power supply voltage VCC and the ground voltage VSS, and the power supply current ICC is extremely small.

[Problems to be solved by the invention]

In the above conventional input buffer circuit, when the voltage level of the input signal A is an intermediate level between the power supply voltage VCC and the ground voltage VSS, a through current flows between the power supply voltage VCC and the ground voltage VSS. There is a problem of increasing.

An object of the present invention is to provide an input buffer circuit capable of reducing a through current flowing from a power supply voltage to a ground voltage and reducing a power supply current even when a voltage level of an input signal is an intermediate level between the power supply voltage and the ground voltage. It is to be.

[Means for solving the problem]

The input buffer circuit according to claim 1, wherein an input buffer circuit body whose conduction state is controlled in accordance with a voltage level of a signal applied to an input terminal, and a signal applied to the input terminal are supplied with a power supply voltage and a ground voltage. And an input for detecting whether or not the voltage is an intermediate voltage, generating a first detection signal in response to detection of the intermediate voltage, and generating a second detection signal in response to detection of a voltage other than the intermediate voltage. A voltage level detection circuit, which is connected to an input terminal of the input buffer circuit and an output terminal of the input voltage level detection circuit, and when the second detection signal is input from the input voltage level detection circuit, outputs the output signal of the input buffer circuit main body to the second The first detection signal is input from the input voltage level detection circuit to the first voltage having the same logic or the second voltage having the same logic as the logic voltage of the signal applied to the input terminal when the detection signal is input. Sometimes Of the output signal of the force buffer circuit body of the first voltage and the second voltage and an output setting circuit to one of the voltage.

According to a second aspect of the present invention, in the input buffer circuit according to the first aspect, the input voltage level detecting circuit includes a P-channel MOS transistor, a resistor and an N-type transistor between a power supply voltage and a ground voltage. A channel-type MOS transistor is connected in series, the gates of the P-channel type MOS transistor and the N-channel type MOS transistor are connected in series to the input terminal of the input buffer circuit main body, and the voltage generated at both ends of the resistor respectively. When the logic voltages are different from each other, the first logic voltage is generated as a first detection signal, and when the voltages generated at both ends of the resistor are the same logic voltage, a logic opposite to the first logic voltage is generated. And a logic circuit for generating the second logic voltage as a second detection signal.

[Action]

According to the configuration of the present invention, the input voltage level detection circuit detects whether the signal applied to the input terminal is an intermediate voltage between the power supply voltage and the ground voltage, and responds to the detection of the intermediate voltage. 1 to generate a second detection signal in response to detection of a voltage other than the intermediate voltage. An output determination circuit is connected to an output terminal of the input voltage level detection circuit. When the second detection signal is input, the output signal of the input buffer circuit main body is changed to a first voltage having the same logic as the logic voltage of the signal applied to the input terminal at the time of input of the second detection signal, or a reverse logic. When the first detection signal is input from the input voltage level detection circuit, the output signal of the input buffer circuit main body is set to one of the first voltage and the second voltage. To ground from power supply voltage Is reduced through current flowing to the pressure, only a power supply current even less. Further, even in a transient state in which the logic voltage of the signal applied to the input terminal changes from one to the other, when it is in the intermediate voltage region,
The output signal can be reliably held at one of the logic voltages.

〔Example〕

One embodiment of the present invention will be described with reference to FIG.

FIG. 1 (a) is a circuit diagram of an input buffer circuit according to one embodiment of the present invention, and FIG. 1 (b) is a signal waveform diagram of the input buffer circuit of FIG. 1 (a).

1 (a) and 1 (b), 1 is an input buffer circuit main body, 2 is an input voltage level detection circuit, 3 is an output determination circuit, Qp11 to Qp16 are P-channel MOS transistors, Qn1
1 to Qn16 are N-channel MOS transistors, A is an input signal, B is an output signal, N11 to N17 are nodes, S is a control signal,
R is a resistor, VCC is a power supply voltage, VSS is a ground voltage, and ICC is a power supply current.

As shown in FIG. 1A, the input buffer circuit of this embodiment includes an input buffer circuit main body 1, an input voltage level detection circuit 2, and an output determination circuit 3.

In the input buffer circuit main body 1, a series connection is formed in which the drains of the MOS transistors Qp11, Qn11, the MOS transistors Qp12, Qn12, the MOS transistors Qp14, Qn14, and the MOS transistors Qp15, Qn15 are connected. Among these, MOS transistors Qp11, Qn11, MOS transistors Qp14, Qn14, and MOS transistors Qp15, Qn1
5 are connected in parallel between the power supply voltage VCC and the ground voltage VSS. The gates of the MOS transistors in each series connection are connected to each other, and connected to the drain of the preceding series connection. First stage MOS transistor Qp1
1, the input signal A is supplied to the gates of Qn11, and the last MO
An output signal B is generated from the drains of the S transistors Qp15 and Qn15. The input voltage level detection by the input voltage level detection circuit 2 is performed on the input to the gates of the MOS transistors Qp12 and Qn12, and the predetermined logic voltage at the intermediate voltage level by the output determination circuit 3 is determined by the MOS transistor Qp12. , Qn12 on the output generated at the drain. MOS transistors Qp11, Qn11, Qp14, Qn14 and
Each series connection composed of Qp15 and Qn15 acts to equalize the logic voltage levels of the input signal A and the output signal B.

The input voltage level detection circuit 2 includes a series connection including MOS transistors Qp16 and Qn16 provided between the power supply voltage VCC and the ground voltage VSS and a resistor R inserted between the drains thereof, and one end of the resistor R. A NOR gate circuit to which a signal generated at the other end is applied through an inverter and a signal generated at the other end are directly applied, and the output of the NOR gate circuit is branched, one of which directly obtains a predetermined delay time α. And a NAND gate circuit applied through an inverter. The gates of the MOS transistors Qp16 and Qn16 are connected to each other.
It is connected to the gates of p12 and Qn12. Here, the reason why one input signal (node 16) to the NAND gate circuit is delayed by the time α by the four-stage inverter for the other input signal (node 17) is that the transition of the signal applied to the input terminal This is to ensure the operation as the input buffer circuit by causing the output determination circuit 3 to perform the output determination operation with a predetermined time delay from the start.

The output determination circuit 3 includes MOS transistors Qp13 and Qn13, the gates of which are connected to the NA of the input voltage level detection circuit 2.
It is connected to the output terminal of the ND gate circuit. And MOS
The transistor Qp13 is connected to the power supply voltage VCC and the MOS transistor Qp1.
2, the MOS transistor Qn13 is inserted between the drain of Qn12 and the MOS transistor Qn13 of the input buffer circuit main body 1.
It is inserted and connected between n12 and the ground voltage VSS.

The input of the input voltage level detection circuit 2 is not the input signal A, but the node N11 which is the output of the NOT circuit composed of the MOS transistors Qp11 and Qn11 of the input buffer circuit main body 1. Is a substantial input signal, and the negation circuit constituted by the MOS transistors Qp11 and Qn11 is for setting a desired logic level, and is not necessary depending on the desired logic level. The input voltage level detection circuit 2 receives a node N11, which is a substantial input signal, and outputs a control signal S according to the voltage level. When the node N11 is at the logic voltage "H" or "L", the logic voltage "H" (second detection signal) is output as the control signal S, and the node N11 is at an intermediate voltage between the power supply voltage VCC and the ground voltage VSS. At some point, the logic voltage “L” (first
Is output as a control signal S. When the control signal S is at the logic voltage "L", that is, when the node 11 is at the intermediate voltage, the node N12 is fixed at the logic voltage "H". MOS transistors Qp14, Qn in input buffer circuit body 1
The two-stage NOT circuit composed of 14, Qp15 and Qn15 is connected to the node N1
2 is an input and an output signal B is output, which simply shapes the signal at the node N12.

The input buffer circuit of this embodiment is different from the node 12 whose output is determined by the output determination circuit 3 and the node 11 which is a substantial input signal, and does not fix the node 11 which is a substantial input signal. The node 11, which is a substantial input signal, is configured to receive the voltage level of the external input signal itself.

Hereinafter, the operation of the input buffer circuit will be described.

First, when the input signal A is at the logic voltage “H” (high level), the P-channel MOS transistor Qp11 is off,
Since the N-channel type MOS transistor Qn11 is turned on,
The node N11 becomes the logic voltage “L” (low level). At this time, the P-channel type MOS transistor Qp16 of the input voltage level detection circuit 2 is turned on and the N-channel type MOS transistor Qn16 is turned off, so that the nodes N14 and N15 have the logic voltage "H", and the nodes N16 and N17 have the logic voltage "H". Since the signal becomes “L”, the control signal S output from the input voltage level detection circuit 2 is a logic voltage “H”. Then, since the control signal S is the logic voltage “H”, the P-channel type MO of the output determination circuit 3
The S transistor Qp13 is off, and the N-channel MOS transistor Qn13 is on. Further, the P-channel type MOS transistor Qp12 is on, and the N-channel type MOS transistor Qn12
Is off, and the node N12 has the logic voltage “H”. Then, the P-channel type MOS transistor Qp14 is turned off,
Since the channel type MOS transistor Qn14 is turned on, the node N13 goes to the logic voltage “L”. Further, the P-channel type MOS transistor Qp15 is turned on and the N-channel type MOS transistor Qn15 is turned off, so that the output signal B of the input buffer circuit main body 1 becomes the logic voltage "H". At this time, since no through current flows between the power supply voltage VCC and the ground voltage VSS, the power supply current ICC is very small.

Next, when the input signal A is at an intermediate level between the power supply voltage VCC and the ground voltage VSS, the P-channel type MOS transistor Q
Since both p11 and the N-channel MOS transistor Qn11 are turned on, the node N11 is at an intermediate level. At this time, the P-channel type MOS transistor Qp16 and the N-channel type MOS transistor Qn16 of the input voltage level detection circuit 2 are both turned on.
N15 becomes the logic voltage “L”, and the node N16 becomes the logic voltage “H”. Then, since the node N17 becomes the logic voltage “H” after the delay time α generated by the four-stage inverter from the potential transition of the node N16, the control signal S output from the input voltage level detection circuit 2 is delayed from the potential transition of the node N16. After the time α, the logic voltage becomes “L”. Also, P-channel type MOS
Transistor Qp12 and N-channel MOS transistor Qn1
2 is ON, but the control signal S is at the logic voltage “L”.
Therefore, after a delay time α from the potential transition of the node N16, the P-channel type MOS transistor Qp13 of the output determination circuit 3
Turns on, and the N-channel MOS transistor Qn13 turns off. Therefore, after a delay time α from the potential transition of the node N16, the node N12 becomes the logic voltage “H”. Then, the P-channel type MOS transistor Qp14 is turned off and the N-channel type MOS transistor Qn14 is turned on, so that the node N13 becomes the logic voltage "L". Further, the P-channel type MOS transistor Qp15 is turned on, and the N-channel type MOS transistor Qp15 is turned on.
n15 turns off. That is, the output signal B is set to the logic voltage “H” after the delay time α from the potential transition of the node N16. At this time, the through current flows only between the potential transition of the node N16 and the potential transition of the node N17 between the power supply voltage VCC and the ground voltage VSS, and thereafter, the through current decreases and the power supply current IC
C also decreases. Here, the setting of the delay time α from the potential transition of the node N16 to the potential transition of the node N17 is set to, for example, about the transition time of the normal use of the input signal A or the node N11 which is a substantial input signal. As a result, when the input signal has a transition time longer than the normal use transition time, that is, when the time during which the input signal is at the intermediate voltage exceeds the delay time α, the output signal B is fixed. Conversely, when the time during which the input signal is at the intermediate voltage is less than the delay time α, the input signal is transmitted to the output signal B as it is via the buffer, and the output signal B is not fixed. Even if the delay time α is extremely short or nonexistent, it is possible to achieve a reduction in power consumption by fixing the internal signal when the input signal is at an intermediate voltage, but the output signal is temporarily fixed during the transition of the input signal. In some cases, a short pulse signal is generated in the output signal, causing noise in circuit operation. The circuit having the delay time α can eliminate such a cause of the noise.

Next, when the input signal A is at the logic voltage "L", the P-channel MOS transistor Qp11 is turned on and the N-channel MOS transistor Qn11 is turned off, so that the node N11 is at the logic voltage "H". At this time, the input voltage level detection circuit 2
P-channel type MOS transistor Qp16 is turned off and N-channel type MOS transistor Qn16 is turned on, so that nodes N14 and N15 become logic voltage "L", and nodes N16 and N17
Becomes the logic voltage “L”, so that the input voltage level detection circuit 2
Is a logic voltage "H". And
Since the control signal S has the logic voltage “H”, the output determination circuit 3
P-channel MOS transistor Qp13 is off, and N-channel MOS transistor Qn13 is on. The P-channel type MOS transistor Qp12 is off, and the N-channel type
The OS transistor Qn12 is on, and the node N12 goes to the logic voltage “L”. Then, the P-channel MOS transistor Qp14 turns on, and the N-channel MOS transistor Qn14
Is turned off, the node N13 goes to the logic voltage “H”. Further, the P-channel type MOS transistor Qp15 turns off,
Since the N-channel type MOS transistor Qn15 is turned on,
The output signal B becomes the logic voltage “L”. In this case, the power supply voltage
Since no shoot-through current flows between VCC and the ground voltage VSS, the power supply current ICC is very small.

As described above, according to this embodiment, even if the input signal A is at an intermediate level between the power supply voltage VCC and the ground voltage VSS, the output signal B of the input buffer circuit is fixed at the logic voltage “H”,
The through current between the power supply voltage VCC and the ground voltage VSS decreases, and the power supply current ICC also decreases.

〔The invention's effect〕

According to the input buffer circuit of the present invention, the input voltage level detection circuit detects whether the signal applied to the input terminal is an intermediate voltage between the power supply voltage and the ground voltage, and responds to the detection of the intermediate voltage. Generates a first detection signal, and generates a second detection signal in response to detection of a voltage other than the intermediate voltage. An output determination circuit is connected to an output terminal of the input voltage level detection circuit, and the input voltage level detection circuit When the second detection signal is input from the circuit, the output signal of the input buffer circuit main body is changed to a first voltage having the same logic as the logic voltage of the signal applied to the input terminal at the time of input of the second detection signal, or a reverse voltage. When the first detection signal is input from the input voltage level detection circuit, the output signal of the input buffer circuit main body is changed to one of the first voltage and the second voltage. Power by Is reduced through current flowing from pressure to the ground voltage, only a power supply current even less. Also, even in a transient state in which the logic voltage of the signal applied to the input terminal changes from one to the other, when it is in the intermediate voltage range, the output signal is reliably changed to one of the logic voltages. Can hold.

[Brief description of the drawings]

FIG. 1 (a) is a circuit diagram of an input buffer circuit according to an embodiment of the present invention, FIG. 1 (b) is a signal waveform diagram of the input buffer circuit of FIG. 1 (a), and FIG. FIG. 2 (b) is a circuit diagram of a conventional input buffer circuit, and FIG. 2 (b) is a signal waveform diagram of the input buffer circuit of FIG. 2 (a). 1 ... input buffer circuit main body, 2 ... input voltage level detection circuit, 3 ... output determination circuit, A ... output signal, B ...
Output signal, S: Control signal, Qn11 to Qn16: N-channel MOS transistor, Qp11 to Qp16: P-channel type M
OS transistor, VCC: Power supply voltage, VSS: Ground voltage

Claims (2)

(57) [Claims] An input buffer circuit whose conduction state is controlled in accordance with a voltage level of a signal applied to an input terminal; and a signal applied to the input terminal is an intermediate voltage between a power supply voltage and a ground voltage. An input voltage level detection circuit for detecting whether the intermediate voltage is detected, generating a first detection signal in response to detection of the intermediate voltage, and generating a second detection signal in response to detection of a voltage other than the intermediate voltage When the second detection signal is input from the input voltage level detection circuit, the output signal of the input buffer circuit main body is connected to the output terminal of the input buffer circuit main body and the output terminal of the input voltage level detection circuit. A first voltage having the same logic as the logic voltage of the signal applied to the input terminal when the second detection signal is input, or a second voltage having the opposite logic,
When the first detection signal is input from the input voltage level detection circuit, an output decision is made such that an output signal of the input buffer circuit main body is any one of the first voltage and the second voltage. And an input buffer circuit comprising the circuit. 2. An input voltage level detecting circuit, comprising: a P-channel MOS transistor, a resistor, and an N-channel MOS transistor connected in series between a power supply voltage and a ground voltage; When the voltages generated at both ends of the series-connected body in which the gate of the channel type MOS transistor is connected to the input terminal of the input buffer circuit main body and both ends of the resistor are different from each other, the first logic voltage is set to the first logic voltage. When the voltages generated at both ends of the resistor are the same logic voltage, a second logic voltage having a logic opposite to the first logic voltage is generated as a second detection signal. 2. The input buffer circuit according to claim 1, wherein said input buffer circuit comprises a logic circuit.