JP2616587B2 - Method for removing resin flash from semiconductor device - Google Patents

Method for removing resin flash from semiconductor device

Info

Publication number
JP2616587B2
JP2616587B2 JP3007368A JP736891A JP2616587B2 JP 2616587 B2 JP2616587 B2 JP 2616587B2 JP 3007368 A JP3007368 A JP 3007368A JP 736891 A JP736891 A JP 736891A JP 2616587 B2 JP2616587 B2 JP 2616587B2
Authority
JP
Japan
Prior art keywords
resin
heat sink
die pad
semiconductor device
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3007368A
Other languages
Japanese (ja)
Other versions
JPH04240755A (en
Inventor
隆 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3007368A priority Critical patent/JP2616587B2/en
Publication of JPH04240755A publication Critical patent/JPH04240755A/en
Application granted granted Critical
Publication of JP2616587B2 publication Critical patent/JP2616587B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/98Methods for disconnecting semiconductor or solid-state bodies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の樹脂ばり除
去方法に関し、特にヒートシンクをダイパッド裏面に取
付けた樹脂封止型半導体装置の樹脂ばりの除去方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for removing resin burrs from a semiconductor device, and more particularly to a method for removing resin burrs from a resin-encapsulated semiconductor device in which a heat sink is attached to the back surface of a die pad.

【0002】[0002]

【従来の技術】ここ数年来、IC、LSI等の半導体装
置は高速、高集積化が要求され、それに伴ない半導体装
置用パッケージは低熱抵抗、多ピン、小型化が求められ
る様になってきた。これまで、これらの要求に応えられ
るパッケージとして、セラミックPGAがこの分野をリ
ードしてきた。しかしながら、このセラミックPGAは
高価格という問題を抱えており、最近になり、セラミッ
クPGAの低熱抵抗および樹脂封止型パッケージの低価
格という両者の長所を合わせもつパッケージ、すなわち
ヒートシンクをダイパッド裏面に取付けた構造の樹脂封
止型半導体装置(以下、ヒートシンク付モールドICと
略す)が開発されてきた。
2. Description of the Related Art In recent years, semiconductor devices such as ICs and LSIs have been required to have high speed and high integration, and accordingly, packages for semiconductor devices have been required to have low heat resistance, high pin count and small size. . Heretofore, ceramic PGA has led the field as a package meeting these requirements. However, this ceramic PGA has a problem of high price, and recently, a package having both advantages of a low thermal resistance of ceramic PGA and a low price of a resin-sealed package, that is, a heat sink is mounted on the back surface of the die pad. 2. Description of the Related Art A resin-encapsulated semiconductor device having a structure (hereinafter, abbreviated as a molded IC with a heat sink) has been developed.

【0003】従来、このヒートシンク付モールドIC
は、図5に示す構造図の様に、ダイパッド1の表面2に
ダイボンディングされかつリードフレーム16にワイヤ
15で接続された半導体素子3を、トランスファー成形
法によりエポキシ樹脂4で樹脂封止したパッケージ5
に、ヒートシンク10をダイパッド裏面6にシリコン樹
脂11で接着した構造を有している。また、ヒートシン
ク付モールドIC13aの作動時に半導体素子3で発生
する熱は、主にダイパッド2を通りヒートシンク10に
伝導することで放熱されている。
Conventionally, this molded IC with a heat sink
As shown in the structural diagram of FIG. 5, a package in which a semiconductor element 3 die-bonded to the surface 2 of the die pad 1 and connected to the lead frame 16 by wires 15 is resin-encapsulated with an epoxy resin 4 by a transfer molding method. 5
The heat sink 10 has a structure in which a silicon resin 11 is bonded to the rear surface 6 of the die pad. Further, heat generated in the semiconductor element 3 when the molded IC 13 a with heat sink is operated is radiated mainly by conduction to the heat sink 10 through the die pad 2.

【0004】[0004]

【発明が解決しようとする課題】この従来のヒートシン
ク付モールドIC13aでは、ダイパッド裏面6にトラ
ンスファー成形法による樹脂封止工程において、通常、
最大厚さ部分で0.1〜0.3mm程度の樹脂ばり7が
凹面状に発生する。この樹脂ばり7上にヒートシンク1
0を接着した場合、ダイパッド裏面6とヒートシンク1
0との間隙は最低でも樹脂ばり7の厚さとなるが、熱抵
抗はこの厚さに比例して大きくなるので、熱伝導度の小
さいエポキシ樹脂(約16×10-4cal/cm・se
c・℃)とシリコン樹脂(約22×10-4cal/cm
・sec・℃)がダイパッド裏面6とヒートシンク10
との間に存在することは、ヒートシンク付モールドIC
13aの熱抵抗をかなり大きくすることになり、消費電
力の大きいICに対しては問題となっていた。
In the conventional mold IC 13a with a heat sink, in the resin sealing step by the transfer molding method on the die pad back surface 6, usually,
Resin burrs 7 having a maximum thickness of about 0.1 to 0.3 mm are formed in a concave shape. The heat sink 1 is placed on the resin beam 7.
0, the back surface 6 of the die pad and the heat sink 1
The gap with zero is at least the thickness of the resin burr 7, but since the thermal resistance increases in proportion to this thickness, the epoxy resin having a small thermal conductivity (about 16 × 10 −4 cal / cm · s
c · ° C.) and silicone resin (about 22 × 10 −4 cal / cm)
· Sec · ° C) is the die pad back surface 6 and the heat sink 10
Exists between the mold IC with the heat sink
The heat resistance of the IC 13a is considerably increased, which is a problem for an IC that consumes a large amount of power.

【0005】[0005]

【課題を解決するための手段】本発明のヒートシンク付
モールドICの樹脂ばり除去方法は、窪み部となってい
るダイパッド裏面6に樹脂封止工程で発生した樹脂ばり
7を、超高圧ウォータージェットによるウェットホーニ
ング法により除去する方法である。
According to the present invention, there is provided a method for removing resin burrs from a mold IC with a heat sink, comprising the steps of: applying a resin burr generated in a resin sealing step to a back surface of a die pad serving as a concave portion; This is a method of removing by a wet honing method.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0007】図1は本発明の実施例1のヒートシンク付
モールドICの樹脂ばり除去方法を示す構成図である。
本実施例は、ダイパッド1の表面2にダイボンディング
されかつリードフレーム16にワイヤ15で接続された
半導体素子3を、トランスファー成形法によりエポキシ
樹脂4で樹脂封止し、この樹脂封止したパッケージ5の
ダイパッド裏面6に発生したエポキシ樹脂による樹脂ば
り7へ、図示しない高圧ポンプにより圧力を高められた
超高圧水8(約700kg/cm2 )を高圧ノズル9か
ら噴出させて取除くものである。尚、高圧ノズル9は動
作範囲17内で移動させて樹脂ばり7部分のみ取除く。
FIG. 1 is a block diagram showing a method for removing resin burrs from a molded IC with a heat sink according to a first embodiment of the present invention.
In this embodiment, a semiconductor element 3 die-bonded to a surface 2 of a die pad 1 and connected to a lead frame 16 by a wire 15 is resin-encapsulated with an epoxy resin 4 by a transfer molding method. Ultra-high pressure water 8 (approximately 700 kg / cm 2 ) whose pressure has been increased by a high-pressure pump (not shown) is ejected from a high-pressure nozzle 9 to a resin burr 7 of epoxy resin generated on the back surface 6 of the die pad. The high-pressure nozzle 9 is moved within the operation range 17 to remove only the resin burr 7.

【0008】図2に本実施例により樹脂ばり7が取除か
れた直後のパッケージ5の構造図を示す。
FIG. 2 is a structural view of the package 5 immediately after the resin burr 7 is removed according to the present embodiment.

【0009】この様な超高圧ウォータージェットに代表
されるウェットホーニング法は、樹脂封止型半導体装置
の外部リード上に同じく樹脂封止工程において発生する
樹脂の薄ばりの除去にも使用されており、各種のパッケ
ージに対する汎用性および窪み部のばり除去性という点
で、機械的な除去方法に比べて優れている。また、ウェ
ットホーニングの前処理として、電解ばり取り(例えば
アルカリ電解処理)を行なえば、ウェットホーニングの
除去効率がさらに高まる。
The wet honing method typified by such an ultra-high pressure water jet is also used for removing resin thins generated in the resin sealing step on external leads of a resin-sealed semiconductor device. It is superior to the mechanical removal method in terms of versatility for various packages and burrs in the recess. Further, if electrolytic deburring (for example, alkaline electrolytic treatment) is performed as a pretreatment for wet honing, the removal efficiency of wet honing is further improved.

【0010】以上述べた様に、本実施例により、ダイパ
ッド裏面6に発生した樹脂ばり7を取除いた後、ヒート
シンク10をシリコン樹脂11で接着し、外部リード1
2の切断曲げを行い、完成したヒートシンク付モールド
IC13の構造図を図3に示す。この様にダイパッド裏
面6とヒートシンク10との間の熱抵抗が比較的高いエ
ポキシ樹脂が完全に取除かれ、薄いシリコン樹脂11
(厚さ約0.03mm)のみで、ダイパッド1とヒート
シンク10とを接着することになり、ダイパッド裏面6
とヒートシンク10との間の熱抵抗が大幅に低下し(熱
抵抗が従来の約3/10〜1/10になる)、半導体素
子3で発生する熱は熱伝導の主経路であるダイパッド1
からヒートシンク10に効率よく放散することになる。
As described above, according to the present embodiment, after removing the resin burrs 7 generated on the rear surface 6 of the die pad, the heat sink 10 is bonded with the silicon resin 11 to form the external leads 1.
FIG. 3 shows a structural view of the completed mold IC 13 with heat sink after performing the cutting and bending of FIG. In this manner, the epoxy resin having a relatively high thermal resistance between the die pad back surface 6 and the heat sink 10 is completely removed, and the thin silicon resin 11 is removed.
(With a thickness of about 0.03 mm), the die pad 1 and the heat sink 10 are bonded together, and the die pad back surface 6
The thermal resistance between the heat sink 10 and the heat sink 10 is greatly reduced (the thermal resistance becomes about 3/10 to 1/10 of the conventional one), and the heat generated in the semiconductor element 3 is transferred to the die pad 1 which is a main path of heat conduction.
From the heat sink 10 efficiently.

【0011】次に、図4に本発明の実施例2の構成図を
示す。実施例2では、エポキシ樹脂4の裏面14全体
に、超高圧水8を高圧ノズル9の移動(動作範囲17)
により噴出させる。この様に、ダイパッド裏面6のみな
らずエポキシ樹脂4の裏面14全体にも超高圧水8を当
てることにより、エポキシ樹脂表面上から樹脂封止工程
にて滲出してシリコン樹脂との接着力を弱める役割をも
つワックス等の離型剤が取除かれる為、ヒートシンク1
0とエポキシ樹脂4との接着強度が大幅に高まり、また
ヒートシンク10とエポキシ樹脂4間より浸入してくる
水分を抑止し、ヒートシンク付モールドICの信頼性が
さらに向上する。
Next, FIG. 4 shows a configuration diagram of a second embodiment of the present invention. In the second embodiment, the ultrahigh-pressure water 8 is moved by the high-pressure nozzle 9 over the entire back surface 14 of the epoxy resin 4 (operating range 17).
Squirt. In this manner, by applying the ultra-high pressure water 8 not only to the die pad back surface 6 but also to the entire back surface 14 of the epoxy resin 4, the resin oozes out of the epoxy resin surface in the resin sealing step to weaken the adhesive force with the silicon resin. Since the releasing agent such as wax having a role is removed, the heat sink 1
The adhesive strength between the heat sink 10 and the epoxy resin 4 is greatly increased, and water entering from between the heat sink 10 and the epoxy resin 4 is suppressed, so that the reliability of the molded IC with the heat sink is further improved.

【0012】[0012]

【発明の効果】以上説明したように本発明は、ヒートシ
ンク付モールドICのダイパッド裏面に樹脂封止工程で
発生した樹脂ばりを、ウェットホーニング法を適用する
ことにより除去できるので、ダイパッドとヒートシンク
間の熱抵抗が大幅に低下し、半導体素子で発生する熱は
熱伝導の主経路であるダイパッドからヒートシンクに効
率よく放散することになり、低価格で低熱抵抗である樹
脂封止型パッケージを実現できるという効果を有する。
As described above, according to the present invention, the resin burrs generated in the resin sealing step on the back surface of the die pad of the mold IC with the heat sink can be removed by applying the wet honing method. The thermal resistance is greatly reduced, and the heat generated by the semiconductor element is efficiently dissipated from the die pad, which is the main path of heat conduction, to the heat sink, which makes it possible to realize a low-cost, low-heat-resistance resin-sealed package. Has an effect.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例1のヒートシンク付モールドI
Cの樹脂ばり除去方法を示す構成図である。
FIG. 1 is a mold I with a heat sink according to a first embodiment of the present invention.
It is a block diagram which shows the resin burr removal method of C.

【図2】実施例1によるパッケージの構造図である。FIG. 2 is a structural diagram of a package according to a first embodiment.

【図3】実施例1により完成したヒートシンク付モール
ドICの構造図である。
FIG. 3 is a structural diagram of a molded IC with a heat sink completed according to the first embodiment.

【図4】本発明の実施例2のヒートシンク付モールドI
Cの樹脂ばり除去方法を示す構成図である。
FIG. 4 is a mold I with a heat sink according to a second embodiment of the present invention.
It is a block diagram which shows the resin burr removal method of C.

【図5】従来のヒートシンク付モールドICの構造図で
ある。
FIG. 5 is a structural diagram of a conventional molded IC with a heat sink.

【符号の説明】[Explanation of symbols]

1 ダイパッド 2 ダイパッドの表面 3 半導体素子 4 エポキシ樹脂 5 パッケージ 6 ダイパッド裏面 7 樹脂ばり 8 超高圧水 9 高圧ノズル 10 ヒートシンク 11 シリコン樹脂 12 外部リード 13,13a ヒートシンク付モールドIC 14 エポキシ樹脂の裏面 15 接続ワイヤ 16 リードフレーム 17,17a 高圧ノズルの動作範囲 DESCRIPTION OF SYMBOLS 1 Die pad 2 Die pad surface 3 Semiconductor element 4 Epoxy resin 5 Package 6 Die pad back surface 7 Resin burr 8 Ultra high pressure water 9 High pressure nozzle 10 Heat sink 11 Silicon resin 12 External lead 13, 13a Mold IC with heat sink 14 Epoxy resin back surface 15 Connection wire 16 Lead frame 17, 17a Operating range of high pressure nozzle

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 ヒートシンクを樹脂封止型半導体装置の
ダイパッド裏面に取付ける際の半導体装置の樹脂ばり除
去方法において、前記半導体装置のダイパッド裏面に樹
脂封止工程で発生した樹脂ばりを、超高圧ウォータージ
ェットによるウェットホーニング法により除去すること
を特徴とする半導体装置の樹脂ばり除去方法。
In a method of removing a resin flash from a semiconductor device when a heat sink is attached to a rear surface of a die pad of the resin-sealed semiconductor device, the resin flash generated in the resin sealing process on the rear surface of the die pad of the semiconductor device is removed by an ultra-high pressure water. A method for removing resin burrs from a semiconductor device, comprising removing the resin by a wet honing method using a jet.
JP3007368A 1991-01-25 1991-01-25 Method for removing resin flash from semiconductor device Expired - Lifetime JP2616587B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3007368A JP2616587B2 (en) 1991-01-25 1991-01-25 Method for removing resin flash from semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3007368A JP2616587B2 (en) 1991-01-25 1991-01-25 Method for removing resin flash from semiconductor device

Publications (2)

Publication Number Publication Date
JPH04240755A JPH04240755A (en) 1992-08-28
JP2616587B2 true JP2616587B2 (en) 1997-06-04

Family

ID=11664031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3007368A Expired - Lifetime JP2616587B2 (en) 1991-01-25 1991-01-25 Method for removing resin flash from semiconductor device

Country Status (1)

Country Link
JP (1) JP2616587B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009055717A1 (en) * 2009-11-26 2011-06-01 Continental Automotive Gmbh Sensor module and manufacturing method of a sensor module
WO2012137760A1 (en) 2011-04-04 2012-10-11 ローム株式会社 Semiconductor device and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JPH04240755A (en) 1992-08-28

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