JP2611745B2 - Method for manufacturing compound semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a compound semiconductor device, and more particularly to a method for manufacturing a high electron mobility transistor.

[0002]

2. Description of the Related Art A high electron mobility transistor, which is one type of MESFET, is often used as an amplifying device in microwave and millimeter wave bands. Such a high electron mobility transistor has a recess structure capable of realizing a high gate breakdown voltage in response to a demand for high output. The structure of the compound semiconductor substrate used in these high electron mobility transistors has a structure in which a plurality of group 3-5 compound semiconductor layers are stacked,
It looks like this:

When a semi-insulating GaAs substrate is used,
Non-doped GaAs is applied to the surface of the semi-insulating GaAs substrate.
A buffer layer composed of only an s layer or a buffer layer in which a non-doped InGaAs layer is laminated on a non-doped GaAs layer is provided, and an electron supply layer composed of an n-type AlGaAs layer is provided on the surface of the buffer layer. On the surface of the electron supply layer, a contact layer made of an n-type GaAs layer is provided.

When a semi-insulating InP substrate is used, the surface of the semi-insulating InP substrate has a non-doped InP substrate.
A buffer layer made of a GaAs layer is provided, an electron supply layer made of an n-type InAlAs layer is provided on the surface of the buffer layer, and InGaAs is provided on the surface of the electron supply layer.
A contact layer comprising a layer is provided.

In such a transistor, an opening having a recess structure is provided by etching a contact layer, and a gate electrode for Schottky junction is provided on the surface of the electron supply layer exposed by the opening. In the buffer layer near the hetero interface composed of the electron supply layer and the buffer layer, electrons and donor ions are spatially separated through this hetero junction interface, the electrons are two-dimensionally formed, and the region where donor ions do not exist is present. , The electron travels, thereby realizing high electron mobility.

Referring to FIG. 4, which is a schematic cross-sectional view of a manufacturing process of a compound semiconductor device, an example of a conventional high electron mobility transistor is formed as follows.

First, on a surface of a semi-insulating GaAs substrate 201, a non-doped GaAs layer 202 serving as a buffer layer is formed.
An n-type AlGaAs layer 203 serving as an electron supply layer and an n-type GaAs layer 204 serving as a contact layer are sequentially epitaxially grown. Next, a photoresist film 231 having an opening in a region where the recess is opened is formed of n-type GaAs.
It is provided on the surface of the layer 204. Subsequently, a mixed gas of a chloride gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine as a halogen element (e.g., an electron cyclotron resonance (ECR) etching apparatus or a reactive ion etching (RIE) apparatus). For example, SiCl ₄ + S
F ₆ , SiCl ₄ + NF ₃ or SiCl ₄ + SiF
₄ ) is introduced, and the photoresist film 231 is used as an etching mask to form the n.
The type GaAs layer 204 is selectively etched. By this selective etching, a recess 205 is formed in the n-type GaAs layer 204, and at the same time, an AlF ₃ film 206 covering the surface is formed on the surface of the n-type AlGaAs layer 203 exposed by the recess 205 [ FIG.
(A)]. Further, by such selective etching, the thickness of the n-type AlGaAs layer 203 remaining immediately below the recess 205 that determines the value of the threshold voltage (V _TH ) of the high electron mobility transistor is reduced by several angstroms.
Can be controlled with an accuracy of.

Here, for example, in etching using an etching gas composed of SiCl ₄ + SiF ₄ , n-type GaAs is used.
The reason that the etching rate of the s layer becomes 100 times or more the etching rate of the n-type AlGaAs layer, and this is because the n-type AlG
The surface of the aAs layer is covered with an AlF ₃ film and n-type AlGa
The fact that the etching rate of the As layer is sharply reduced is described in 1990, Journal of Vacuum-Science and Technology, Vol.
No. 6, pages 1956-1959 (Journal-
of-Vacuum-Science-and-Tec
hnology, Vol. B8, no. 6, pp. 19
56-1959, 1990). Also,
JP-A-3-175628 discloses that SiCl ₄ + NF
₃ was used (for the n-type AlGaAs layer) n-type GaA
A method for selective etching of the s layer is disclosed.

Next, O ₂ gas is introduced into a reaction vessel that generates a barrel type or parallel plate type plasma discharge, and the photoresist film 231 is stripped. At this time, Al
The F ₃ film 206 is also removed, and further, Al ₂ O ₃
A film 210 is formed (FIG. 4B). A method of removing a photoresist film with an organic solvent is also known. For example, after immersion in a mixed solution of dichlorobenzene phenol and alkylbenzene sulfonic acid at about 120 ° C., methyl ethyl ketone and There is also a method of sequentially immersing in alcohol (peeling method using a high-temperature organic solvent).

Subsequently, the photoresist film 231 is immersed in an aqueous HCl solution to remove the n-type AlGaAs layer 20 when the photoresist film 231 is peeled off.
The Al ₂ O ₃ film 210 formed on the three surfaces is removed, and at the same time, the exposed surface of the n-type AlGaAs layer 203 is cleaned. Next, a low-sensitivity lower-layer electron beam resist film 232 and a high-sensitivity upper-layer electron beam resist film 233 are sequentially applied and formed, and the upper-layer electron beam resist film 233 is aligned and exposed with an electron beam with a small irradiation amount. Further, the lower layer electron beam resist film 232 is aligned and exposed by an electron beam with a larger irradiation amount, and the upper layer electron beam resist film 233 and the lower layer electron beam resist film 232 are developed and patterned [FIG.
(C)].

Next, an aluminum film is formed on the entire surface,
The upper-layer electron beam resist film 233 and the lower-layer electron beam resist film 232 are removed by a lift-off method, and a T-shaped gate electrode 207 is formed. Next, a silicon oxide film 208 as a protective film is formed on the entire surface by a CVD method. Subsequently, the silicon oxide film 208 is etched by using a photoresist film (not shown) as a mask, and a source electrode 209a and a drain electrode 209b are formed at the portions [FIG. 4D].

In the case of a high electron mobility transistor using a semi-insulating InP substrate, an n-type InGaAs layer as a contact layer (for forming a recess structure) is selected (with respect to an n-type InAlAs layer as an electron supply layer). Applicable Physics-Letter, Vol. 62, No. 22, pages 2830-2832, 1993 (Applid-Physics-L)
etter, Vol. 62, No. 22, pp. 283
0-2832, 1993). Initially, in the selective etching by dry etching, CH ₄ + H ₂ was used as an etching gas. The mixed gas has a low selection ratio due to a defect such as a polymer is easily formed, CCl ₂
F ₂ , SiCl ₄ + SF ₆ , SiCl ₄ + SiF ₄ , C
An etching gas such as H ₃ Br or HBr has been adopted. CCl ₂ F ₂ , SiCl ₄ + SF ₆
Alternatively, when SiCl ₄ + SiF ₄ is used, a deposited film containing at least AlF ₃ is formed on the exposed surface of the n-type InAlAs layer, and when CH ₃ Br or HBr is used, the n-type InAlAs layer is exposed. A film made of InBr ₃ and Al ₂ O ₃ is formed on the surface. Except for this selective etching, it is formed by the same method as that of the high electron mobility transistor using the semi-insulating GaAs substrate. Even if a deposited film containing InBr ₃ is formed on the exposed surface of the n-type InAlAs layer by these selective etching, the O
_{2 At the time} of removing the photoresist film by plasma, at least InBr ₃ is removed, but n-type InAlAs
An Al ₂ O ₃ film is newly formed on the exposed surface of the layer.

[0013]

According to the above prior art, in the dry etching for forming the recess, the etching of the electron supply layer can be controlled with an accuracy of several angstroms. However, a problem arises when the photoresist film used for forming the recess is peeled off. For example, this is O ₂
When plasma is used, an Al ₂ O ₃ film having a thickness of about _{5 to 10} nm is newly formed on the surface of the electron supply layer exposed by the recess, and the decrease in the film thickness of the electron supply layer increases. The value of V _TH shifts to the positive side according to the target value, and the drain (source-to-source) current I _DS decreases accordingly.
Also, in the case of the above-described peeling method using a high temperature organic solvent,
An Al ₂ O ₃ film is newly formed on the surface of the electron supply layer, and this problem cannot be solved. As a method in which an Al ₂ O ₃ film is not formed on the surface of the electron supply layer, there is a method in which a photoresist film is peeled off using only a normal temperature organic solvent such as methyl, ethyl, and ketone. However, in this case, the cured product of the photoresist cannot be sufficiently removed, and a Schottky junction cannot be obtained between the gate electrode and the electron supply layer when the gate electrode is formed.

It is known that V _TH is proportional to the square of the thickness of the electron supply layer.

[0015]

## EQU1 ## Here, phi _B is the Schottky barrier potential of the gate electrode, q is a charge amount, epsilon is the dielectric constant of the electron supply layer, N _D is the donor concentration of the electron supply layer,
d is the thickness of the electron supply layer, and ΔE _C is the magnitude of the energy discontinuity in the conduction band of the hetero-matching. The inventor of the present invention has proposed that in a transistor provided on a semi-insulating GaAs substrate 201 according to the conventional technique, n-type AlGaAs doped with about 2 × 10 ¹⁸ cm ^{−3 of} Si and having a thickness d of about 40 nm.
It was measured between V _TH and this standard deviation [sigma] v _TH in the case of the layer 203. In the stripping method using O ₂ plasma, V _TH = −
0.64 V, σV _TH = 85 mV, and peeling method using a high-temperature organic solvent V _TH = −0.55 V, σV _TH = 124 mV
It became.

From these facts, the object of the present invention is to make σV
_TH is small, desired _VTH is easily obtained, and I
It is an object of the present invention to provide a method for manufacturing a compound semiconductor device in which a decrease in _DS can be easily suppressed.

[0018]

A method of manufacturing a compound semiconductor device according to the present invention is directed to a buffer comprising a non-doped group III-V compound semiconductor layer containing at least Ga and As on the surface of a semi-insulating group III-V compound substrate. A layer is formed, and at least Al and As are contained on the surface of the buffer layer.
Forming an electron supply layer composed of a type 3-5 group compound semiconductor layer, and forming a contact layer composed of an n-type group 3-5 group compound semiconductor layer containing at least Ga and As on the surface of the electron supply layer; And using the photoresist film as a mask, the contact layer is selectively etched by an etching gas composed of a chloride gas containing only chlorine as a halogen element and a first fluoride gas containing only fluorine as a halogen element. Forming a recess to leave a deposited film containing at least AlF ₃ on the surface of the electron supply layer; and supplying a second fluoride gas containing only fluorine as a halogen element to a reaction vessel for generating plasma discharge. Introducing and removing the photoresist film, and removing the deposited film and cleaning the surface of the electron supply layer with an aqueous solution of HCl. Having at least a that step.

Preferably, the semi-insulating group III-V compound substrate comprises a semi-insulating GaAs substrate, and the buffer layer comprises only a non-doped GaAs layer or a laminated film of a non-doped GaAs layer and a non-doped InGaAs layer. The electron supply layer is made of an n-type AlGaAs layer, and the contact layer is made of an n-type GaAs layer.
Alternatively, the semi-insulating group III-V compound substrate comprises a semi-insulating InP substrate, the buffer layer comprises a non-doped InGaAs layer, and the electron supply layer comprises an n-type InP substrate.
An AlAs layer, wherein the contact layer is n-type InG
It consists of an aAs layer.

More preferably, the second fluoride gas is NF ₃ gas or SF ₆ gas, and the etching for forming the recess is performed in the reaction vessel used for removing the photoresist film.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the embodiments of the present invention, the steps leading to the constitution of the present invention will be described first.

In a high electric mobility transistor, generally,
The electron supply layer contains Al, and the contact layer does not contain Al. First, consider selective etching for forming a recess. When the contact layer is etched to form the recess, a plurality of types of reaction products generated between the elements constituting the contact layer and the etching gas include a volatile reaction product and a nonvolatile reaction product. Here, if the surface deposition rate of the non-volatile reaction product is sufficiently low compared to the desorption rate of the non-volatile reaction product, the non-volatile reaction product will not stop the etching by covering the surface of the contact layer. On the other hand, when this etching reaches the electron supply layer, a non-volatile reaction product generated between the element constituting the electron supply layer and the etching gas includes:
If its surface deposition rate is not too low compared to its detachment rate, the surface of the electron supply layer will be covered by the coating of this non-volatile reaction product. Furthermore, if the thickness of this film does not change substantially with respect to the etching time, selectivity can be obtained in this etching. As such an etching gas, CCl ₂ F
₂ , SiCl ₄ + SF ₆ , SiCl ₄ + NF ₃ , SiC
l ₄ + SiF ₄ , CH ₃ Br or HBr are known.

A gas containing fluorine and chlorine (CCl ₂ F
₂ ) Or a mixed gas of a chloride gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine as a halogen element (SiCl ₄ + SF ₆ , SiCl ₄ +
If NF ₃ or SiCl ₄ + SiF ₄ ) is used, when etching reaches the electron supply layer, a deposited film containing at least AlF ₃ is formed on this surface, and the electron supply layer is protected from these etchings. You. Chloride and fluoride are formed as reaction products between the contact layer and these etching gases. Since the contact layer does not contain Al and coexists with chloride gas and fluoride gas, even if non-volatile reaction products are formed, their surface deposition rate is sufficiently lower than their desorption rate. Therefore, these chlorides and fluorides are unlikely to form a deposited film (coating). When CCl ₂ F ₂ is used, the ratio of chlorine to fluorine is fixed, and the etching of the photoresist film by this gas cannot be ignored, so that the reaction product between the photoresist film and this gas is deposited. There is a disadvantage of doing so. On the other hand, when using a mixed gas of a chloride gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine as a halogen element,
There are not many reaction products between the photoresist film and these gases, and by selecting the ratio of chloride gas to fluoride gas, the selective etching of the contact layer (relative to the photoresist film and the electron supply layer) is reduced. It will be easier.

Bromide gas (CH ₃ Br or HBr)
When is used, the deposited film (coating) covering the surface of the electron supply layer is mainly made of bromide. When the electron supply layer is composed of an n-type InAlAs layer, this gas causes InBr ₃
And a deposited film made of Al ₂ O ₃ are formed, and the selectivity of the etching of the contact layer can be secured. However, since the boiling point of AlBr ₃ is not so high, when the electron supply layer is formed of an n-type AlGaAs layer, selective etching using this gas cannot be expected.

Considering the peeling of the photoresist film used as an etching mask for forming the recess, the peeling (etching) rate of the photoresist film is considered to be at least higher than that of the AlF (which is a film on the surface of the electron supply layer).
Deposited film containing ₃ or InBr ₃ and Al ₂ O
It is necessary that the etching rate of the deposited film composed of ₃ and the contact layer is negligibly small. The restriction on the electron supply layer surface in this case is because it is necessary to protect the electron supply layer from reaction products of the photoresist film generated by the stripping reaction. Further, the restriction on the contact layer in this case is that the diameter of the opening of the recess is not greatly increased particularly in the peeling process.

In consideration of these conditions, when the film on the surface of the electron supply layer is formed of a deposited film containing at least AlF ₃ , plasma etching using a fluoride gas containing only fluorine as a halogen element is suitable. I understand.
In this case, the etching of the contact layer is very small,
This deposited film also functions as a protective film without being etched. The photoresist film is also etched by plasma etching using a gas containing chlorine, but the contact layer (and the deposited film containing AlF ₃ ) is also etched,
Improper. Also, plasma etching using a gas containing oxygen (instead of using O ₂ itself)
The contact layer (and the deposited film containing AlF ₃ ) is also etched with the removal of the photoresist film, and an Al 2 O 3 film is formed on the surface of the electron supply layer, which is not preferable.

On the other hand, the coating on the surface of the electron supply layer is made of InBr ₃
And optionally comprising a deposited film of Al ₂ O _3, for example, if performing plasma etching using only drank fluoride gas fluorine as a halogen element photoresist film constitutes but is peeled deposited film InBr ₃ Is also removed. At present, there is no suitable means for selectively removing the photoresist film without substantially etching the deposited film and the contact layer. Therefore, even when the electron supply layer is formed of an n-type InAlAs layer, the etching for forming the recess is performed by using a chloride gas containing only chlorine as a halogen element and a fluoride gas containing only fluorine as a halogen element. Dry etching using a mixed gas is preferable.

A method of removing a photoresist film by plasma etching using a fluoride gas containing only fluorine as a halogen element is disclosed in Japanese Patent Application Laid-Open No. Hei 1-200628.
No. 6,086,045. The above publication is used in the process of manufacturing a silicon semiconductor device, and the constituent materials other than the photoresist film are different from the constituent materials of the present invention, and there is no suggestion regarding the compound semiconductor device and further the AlF ₃ film.

Next, an embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1 which is a schematic cross-sectional view of a manufacturing process of a compound semiconductor device, and FIG. 2 which is a graph of an energy spectrum by X-ray photoelectron spectroscopy (XPS) in the manufacturing process, FIG. A high electron mobility transistor according to one embodiment is made as follows.

First, on a surface of a semi-insulating GaAs substrate 101, a non-doped GaAs layer 102 of a thickness of about 50 nm (a buffer layer) is doped with Si of 2 × 10 ¹⁸ cm ⁻³ to a thickness of about 40 nm (electrons). An n-type AlGaAs layer 103 (a supply layer) is sequentially epitaxially grown. In the XPS measurement immediately after the formation of the n-type AlGaAs layer 103, the peak of AlAs is mainly present (FIG. 2A).
Further, an n-type GaAs layer 104 (a contact layer) having a thickness of about 100 nm and doped with the same amount of Si as the n-type AlGaAs layer 103 is epitaxially grown. On such a compound semiconductor substrate, a photoresist film 131a for selective etching using a photolithography technique is formed. This photoresist film 131
a has an opening in a region where a recess is to be formed.

Next, a mixed gas (for example, BCl _{3) of} a chloride gas containing only chlorine as a halogen element and a first fluoride gas containing only fluorine as a halogen element is supplied to an ECR etching apparatus or an RIE apparatus. + SF ₆ , Cl ₂ + S
F ₆ , SiCl ₄ + SF ₆ , BCl ₃ + NF ₃ or SiCl ₄ + SiF ₄ ) is introduced into the n-type AlGaAs layer 103 by dry etching.
The As layer 104 is selectively etched. For example, B
A mixed gas composed of Cl ₃ + SF ₆ (BCl ₃ : SF ₆ ≒)
When 3: 1) is used, this etching is performed using n-type AlGa.
When reaching the As layer 103, a recess 105 is formed, and at most 1 n is formed on the exposed surface of the n-type AlGaAs layer 103.
An AlF ₃ film 106 having a thickness of about m is formed (FIG. 1A). Al is formed on the surface of the n-type AlGaAs layer 103.
The formation of the F ₃ film 106 is also evident from the XPS measurement immediately after the etching [FIG. 2B].
In the XPS measurement at this time, the n-type AlGaAs layer 103
On the surface, a small amount of S,
F (has a value different from the binding energy of Al-F)
And Cl are also observed. In this etching, the etching rate of the photoresist film 131a is
This is 1/100 of the etching rate of the n-type GaAs layer 104. Other Cl ₂ + SF ₆ , SiCl ₄ + SF ₆ ,
The same result can be obtained by etching using BCl ₃ + NF ₃ or SiCl ₄ + SiF ₄ .

Next, NF ₃ or SF is placed in a reaction vessel such as a barrel type or a parallel plate type which generates a plasma discharge.
_As a halogen element such as _6, only fluorine was contained (second
2) A fluoride gas is introduced to remove the photoresist film 131a. In this stripping step, the AlF ₃ film 106 is hardly etched, and there is no chlorine.
The aAs layer 104 is not etched too much. further,
Since the AlF ₃ film 106 functions as a protective film, there is no influence on the n-type AlGaAs film 103 by this stripping step. Note that there is no necessity to perform the etching for forming the recess 105 and this stripping step using different apparatuses. If this stripping step is performed continuously in the apparatus used for forming the recess 105, exposure to the atmosphere can be avoided. In this stripping step, the influence of the residual oxygen gas is suppressed, and the oxide on the surface of the recess 105 is formed. This is avoided.

As such a fluoride gas, other than the above, F ₂ , XeF ₂ or SiF ₄ is preferable. Note that a fluoride gas containing carbon such as CF ₄ , C ₂ F ₆ , and C ₃ F ₈ is not preferable because a reaction product with the photoresist film 131a is easily deposited.

Next, the compound semiconductor substrate is immersed in an aqueous HCl solution (HCl: H ₂ O ≒ 1: 1) at about 25 ° C. Thus, the AlF ₃ film 106 protecting the surface of the n-type AlGaAs film 103 is removed, and the surface of the n-type AlGaAs film 103 is cleaned. this is,
It is clear from the result of the XPS measurement [FIG. 2 (c)].

Subsequently, the low-sensitivity lower electron beam resist film 1
32a and a high-sensitivity upper electron beam resist film 133a are sequentially applied and formed. A region wider than the gate length is exposed with an electron beam with a small irradiation amount, and a region having the same width as the gate length (included in this exposure region) is exposed with a covering electron beam with the irradiation amount, and then developed. [Figure 1
(C)]. The photoresist film 131a is peeled off,
It is not preferable to remove the AlF ₃ film 106, deposit an insulating film over the entire surface, and form a contact hole having a desired cross-sectional shape in the insulating film. When such a manufacturing method is adopted, the n-type A is removed by an etching gas used for dry etching in forming the contact hole.
A new AlF ₃ film or A on the surface of the lGaAs film 103
The l ₂ O ₃ film is formed, and the thickness of the n-type AlGaAs film 103 at the portion where the gate electrode is formed is reduced.

Next, a metal film (for example, an aluminum film) capable of obtaining a Schottky junction with the n-type AlGaAs film 103
Is formed on the entire surface, the upper electron beam resist film 133a and the lower electron beam resist film 132a are removed by a lift-off method, and the gate electrode 107 having a T-shaped cross section is formed.
a is formed. Subsequently, a silicon oxide film 108a is deposited on the entire surface by, for example, a plasma CVD method.
A contact hole reaching the aAs layer 104 is formed in the silicon oxide film 108a, and a source electrode 109a connected to the n-type GaAs layer 104 through the contact hole.
a and the drain electrode 109ab are formed [FIG.
(D)].

In the first embodiment, the amount of decrease in the thickness of the electron supply layer (compared with the thickness at the time of film formation) at the portion where the gate electrode is formed is about 1 nm at most, so that σV _TH is small. , It is easy to obtain the desired V _TH and I _DS
Can be easily suppressed. According to this embodiment, V _TH =
−1.10 V, σV _TH = 43 mV, and the shift of the value of V _TH to the positive side and the variation of V _TH are caused by the conventional manufacturing method (for example, V _TH = −− in the separation method using O ₂ plasma).
0.64 V, σV _TH = 85 mV).
The reduction of I _DS is also easily suppressed.

In the first embodiment, the buffer layer is formed of only a non-doped GaAs layer.
This embodiment is also applicable to a case where the buffer layer is formed by stacking a non-doped InGaAs layer on a non-doped GaAs layer.

Referring to FIG. 3 which is a schematic cross-sectional view of the manufacturing process of the compound semiconductor device, the high electron mobility transistor according to the second embodiment of the present invention is a transistor formed on an InP substrate. It is formed as follows.

First, on the surface of the semi-insulating InP substrate 111,
Non-doped InGaAs layer 112 having a thickness of about 40 nm (which is a buffer layer), n-type InAlAs layer 113 having a thickness of about 25 nm (which is an electron supply layer) doped with 2 × 10 ¹⁸ cm ^-3 of Si, and n-type InAlAs. An n-type InGaAs layer 114 (which is a contact layer) having a thickness of about 10 nm and doped with the same amount of Si as the layer 113 is sequentially epitaxially grown. Next, the photoresist film 131b
Is formed. The photoresist film 131b has an opening in a region where a recess is to be formed.

Next, as in the first embodiment, the ECR
A gas mixture of, for example, Cl ₂ + SF ₆ (SF ₆ is several vol.%) Is introduced into an etching apparatus or an RIE apparatus,
The n-type InGaAs layer 114 is selectively etched with respect to the n-type InAlAs layer 113. When this etching reaches the n-type InAlAs layer 113, a recess 115 is formed, and a deposited film 116 having a thickness of about 1 nm is formed on the exposed surface of the n-type InAlAs layer 113 (FIG. 3A). The main component of this deposited film 116 is AlF
₃ , but this film also contains InF _{3 in a} very small amount. In this embodiment, similarly to the first embodiment, in addition to the mixed gas, SiCl ₄ + SF ₆ or SiC
l ₄ + SiF ₄ or the like can also be used.

Next, in the same manner as in the first embodiment, NF ₃ , SF ₆ , F ₂ , XeF ₂ or Si is placed in a reactor of a barrel type or a parallel plate type for generating a plasma discharge.
As a halogen element such as F ₄ , a (second) fluoride gas containing only fluorine is introduced, and the photoresist film 131 b
Is peeled off (FIG. 3B). In this stripping step, the deposited film 116 is hardly etched, and the n-type InGaAs layer 114 is hardly etched because chlorine is not present. Also, the presence of the deposited film 116 does not affect the n-type InAlAs film 113 by this stripping step.

Next, as in the first embodiment, at 25 ° C.
About 1: 1 HCl aqueous solution (HCl: H ₂ O ≒ 1: 1). Thus, the deposited film 116 that protected the surface of the n-type InAlAs film 113 is removed, and the surface of the n-type InAlAs film 113 is cleaned. continue,
A low-sensitivity lower electron beam resist film 132b and a high-sensitivity upper electron beam resist film 133b are sequentially applied and formed.
A region wider than the gate length is exposed with an electron beam with a small irradiation amount, and a region having the same width as the gate length (included in this exposure region) is exposed with a covering electron beam with the irradiation amount, and then developed. [FIG. 3 (c)].

Next, as in the first embodiment, for example, an aluminum film is formed on the entire surface, the upper electron beam resist film 133b and the lower electron beam resist film 132b are removed by a lift-off method, and the gate electrode 107b is removed. It is formed. Subsequently, a silicon oxide film 108b is deposited on the entire surface, contact holes reaching the n-type InGaAs layer 114 are formed in the silicon oxide film 108b, and a source electrode 109ba connected to the n-type InGaAs layer 114 through these contact holes. Then, a drain electrode 109bb is formed (FIG. 3D).

In the second embodiment, as in the first embodiment, the decrease in the thickness of the electron supply layer (compared to the time of film formation) at the portion where the gate electrode is formed is small. Has the same effect as the first embodiment.

[0047]

As described above, according to the method for manufacturing a compound semiconductor device of the present invention, the electron supply layer is made of an n-type group III-V compound semiconductor layer containing Al, and the contact layer contains Al. Dry etching for forming a recess is performed using a chloride gas containing only chlorine as a halogen element and a first fluoride gas containing only fluorine as a halogen element. If the photoresist film used for forming the recess is peeled off by plasma etching using a second fluoride gas containing only fluorine as a halogen element, a gate electrode is formed. The amount of decrease in the thickness of the electron supply layer (compared with the time of film formation) at the portion where the electron supply layer is formed can be suppressed to a minimum. As a result, the desired V _TH is easily obtained, the variation in the value of V _TH is reduced, and the decrease in I _DS can be easily suppressed.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating the effect of the first embodiment,
It is a graph of the energy spectrum by XPS measurement.

FIG. 3 is a schematic sectional view of a manufacturing process according to a second embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a manufacturing process of a conventional high electron mobility transistor.

[Explanation of symbols]

101, 201 semi-insulating GaAs substrate 102, 202 non-doped GaAs layer 103, 203 n-type AlGaAs layer 104, 204 n-type GaAs layer 105, 115, 205 recess 106 AlF ₃ film 107a, 107b, 207 gate electrode 108a, 108b, 208 Silicon oxide film 109aa, 109ba, 209a source electrode 109ba, 109bb, 209b drain electrode 111 semi-insulating InP substrate 112 non-doped InGaAs layer 113 n-type InAlAs layer 114 n-type InGaAs layer 116 deposited films 131a, 131b, 231 photoresist film 132a 132b, 232 Lower layer electron beam resist film 133a, 133b, 233 Upper layer electron beam resist film 210 Al ₂ O ₃ film

Claims (6)

(57) [Claims] A buffer layer comprising a non-doped group III-V compound semiconductor layer containing at least Ga and As is formed on the surface of a semi-insulating group III-V compound substrate, and at least Al and As are formed on the surface of the buffer layer. Forming an electron supply layer comprising an n-type group III-V compound semiconductor layer containing
Forming a contact layer comprising an n-type group III-V compound semiconductor layer containing at least Ga and As on the surface of the electron supply layer; and using a photoresist film as a mask, chloride containing only chlorine as a halogen element. And a first fluoride gas containing only fluorine as a halogen element, the contact layer is selectively etched to form a recess, and at least Al is formed on the surface of the electron supply layer.
Leaving a deposited film containing F ₃ , introducing a second fluoride gas containing only fluorine as a halogen element into a reaction vessel for generating plasma discharge, and stripping the photoresist film; Removing the deposited film and cleaning the surface of the electron supply layer with an aqueous solution of HCl. 2. The semi-insulating Group III-V compound substrate comprises a semi-insulating GaAs substrate, the buffer layer comprises a non-doped GaAs layer, and the electron supply layer comprises an n-type A
IGaAs layer, wherein the contact layer is an n-type Ga
2. The method for manufacturing a compound semiconductor device according to claim 1, comprising an As layer. 3. The semi-insulating Group III-V compound substrate comprises a semi-insulating GaAs substrate; the buffer layer comprises a laminated film of a non-doped GaAs layer and a non-doped InGaAs layer; 2. The method according to claim 1, wherein the contact layer comprises an n-type GaAs layer, and the contact layer comprises an n-type GaAs layer. 4. The semi-insulating group III-V compound substrate comprises a semi-insulating InP substrate; the buffer layer comprises a non-doped InGaAs layer; the electron supply layer comprises an n-type InAlAs layer; Layer of n-type I
2. The method for manufacturing a compound semiconductor device according to claim 1, comprising an nGaAs layer. 5. The method according to claim 1, wherein said second fluoride gas is NF ₃ gas or SF ₆ gas. . 6. The etching for forming the recess,
6. The method according to claim 5, wherein the method is performed in the reaction vessel used for removing the photoresist film.