JP2611230B2 - Digital VTR - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital VTR, and more particularly, to an error display for visually checking an error state generated during reproduction.

[Conventional technology]

In a digital VTR, a state of a code error (error) generated in a recording / reproducing process is known or monitored in association with a screen. Conventionally, the following two methods have been used to monitor an error state on a screen of an image monitor.

One method is to stop error correction and error correction of a reproduced image signal and display an image containing an error on an image monitor.

The second method is a method in which a reproduced digital image signal is cut off, and a signal in which data of an error pixel is turned white is supplied to an image monitor and displayed.

[Problems to be solved by the invention]

In the former method, image data with the wrong most significant bit is
As can be clearly seen on the display screen, there is a disadvantage that it becomes difficult to determine whether or not an error occurs as the least significant bit becomes an error. Further, when the number of errors is small, there is a problem that it is difficult to recognize the errors, and furthermore, the appearance of the error state tends to be different depending on the content of the image.

In the latter method, the reproduced digital image signal is once cut, the background is set to black, and the error is displayed as white, so that the disadvantage that the error is difficult to see is eliminated. However, there is a disadvantage that the reproduced image at the time when the error occurs cannot be monitored. Further, both methods have a drawback that an error cannot be displayed during normal operation of the device.

Therefore, an object of the present invention is to make it easy to see the error display,
Another object of the present invention is to provide a digital VTR that can simultaneously monitor an image being reproduced and that does not affect the original image even during operation.

[Means for solving the problem]

The present invention relates to a digital signal processing circuit which receives a reproduced image signal, detects an error in a pixel unit of the reproduced image signal, corrects the detected error, and corrects an uncorrectable error. A first output terminal from which an error-corrected and error-corrected image signal is output, and first level conversion means for converting information of an image in which an error has been detected by the digital signal processing circuit into a high-level signal; A second level conversion means for outputting a low-level signal obtained by attenuating the level of the image signal from the digital signal processing circuit; a second output terminal connected to the monitor; and error information from the digital signal processing circuit. A signal converted to a high level by the first level conversion means is output to a second output terminal as pixel information indicating an error. Means for outputting, to a second output terminal, a signal converted to a low level by the second level conversion means as pixel information indicating that error information from the digital signal processing circuit is not an error. Digital VTR.

[Action]

The reproduced image signal is not cut off,
Attenuated. In the attenuated image signal, only the information of the pixel in which the error is detected is converted to a high level. Thus, although the reproduced image is at a low level, it can be monitored with errors, and the errors can be seen clearly on the screen since they have been converted to a high level, eg, white. On the other hand, the reproduced image signal is taken out to another output terminal without being attenuated. Therefore, the reproduced image signal can be used for operation, and an error state can be displayed even during operation.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. The embodiment shown in FIG. 1 is an example in which a main image signal and an image signal for error display are extracted as analog outputs.

In FIG. 1, reference numeral 1 denotes a digital signal processing circuit. The digital signal processing circuit 1 includes, for example, a demodulation circuit that digitally demodulates a signal reproduced from a magnetic tape by a rotary head, an error correction circuit that performs error correction on a reproduced digital signal, and an error that cannot be corrected. An error correction circuit for interpolating with correct data is included.

An 8-bit parallel output signal from the digital signal processing circuit 1 is supplied to the D / A converter 2. In this example, 1
A pixel (sample data) corresponds to 8 bits. D /
An analog image signal from the A converter 2 is supplied to a video amplifier 4 via a low-pass filter 3. An analog image signal from the video amplifier 4 is taken out via an output buffer circuit 5 as a main analog output signal at an output terminal 6.

A resistor 7 and a resistor 8 are connected between the output side of the video amplifier 4 and the ground.
And a switch circuit 9 in series. The connection point between the resistors 7 and 8 is one input terminal a of the switch circuit 10.
Connected to. The other input terminal b of the switch circuit 10
Is the resistor 12 and the resistor inserted between the power terminal 11 and the ground.
Connected to 13 connection points. Output terminal c of switch circuit 10
Is output as an output terminal 15 via an output buffer circuit 14. This output terminal 15 is a secondary output signal for error display. An image monitor (not shown) is connected to the output terminal 15.

The switch circuit 9 is turned on by a control signal from the terminal 16.
/ OFF. This control signal is set to a high level when an error display is performed, and the switch circuit 9 is turned on at the high level. The switch circuit 10 is turned on / off by an output signal of the AND gate 17. When the output signal of the AND gate 17 is at a low level, the switch circuit 10 selects the input terminal a, and when the output signal of the AND gate 17 is at a high level,
The switch circuit 10 selects the input terminal b. AND gate 1
7 is supplied with a control signal from a terminal 16 and an error pulse from a terminal 18. The error pulse is a signal formed by the digital signal processing circuit 1 and goes high at the timing of a pixel detected as an error in the reproduced signal.

When an error is displayed, the control signal from the terminal 16 is set to a high level, and when the switch circuit 9 is turned on, an image signal divided by the resistors 7 and 8 is generated. The attenuated image signal is supplied to the input terminal a of the switch circuit 10.

The value of each of the resistors 12 and 13 and the DC voltage from the power supply terminal 11 are the connection point of the resistors 12 and 13, that is, the switch circuit.
The level supplied to the ten input terminals b is selected to be a white level. Therefore, during the error display operation, when the output signal of the AND gate 17 becomes high level corresponding to the error pixel, the switch circuit 10 selects the white level from the input terminal b. In a pixel having no error, since the switch circuit 10 selects the input terminal a, an image signal having an attenuated level is selected.

Therefore, in the error display state, the analog image signal taken out to the output terminal 15 is a signal in which a signal having a white level in a pixel having an error is superimposed on the reproduced image signal whose level has been attenuated. Since the image signal from the output terminal 15 is supplied to the image monitor, the display on the image monitor is obtained by superimposing a white dot error display on the low-level reproduced image.

FIG. 2 shows another embodiment of the present invention. In another embodiment, the image monitor has a D / A converter and the digital V
The present invention is applied when the interface between the TR and the image monitor is digital.

An error-corrected digital image signal from the digital signal processing circuit 1 similar to that of the above-described embodiment is taken out as a main digital output signal at an output terminal 22 via an output buffer circuit 21. At the same time, the digital image signal from the digital signal processing circuit is supplied to the input terminal a of the switch circuit 23 and the level compression circuit 24. The output signal of the level compression circuit 24 is input to the input terminal b of the switch circuit 23.
Supplied to The level compression circuit 24 compresses the level of the digital image signal, and is configured, for example, as a bit shift circuit.

The signal obtained from the output terminal c of the switch circuit 23 is supplied to the OR gate 25. The output signal of the OR gate 25 is output to an output terminal 26 as a secondary output signal for displaying an error. Although not shown, an image monitor having a built-in D / A converter is connected to the output terminal 26.

The switch circuit 23 is turned ON / O by a control signal from the terminal 27.
FF. This control signal becomes high level in the error display state, and becomes low level in other than the error display state. The switch circuit 23 selects the reproduced digital image signal supplied to the input terminal a when the control signal is at a low level,
When the control signal is at the high level, the output signal of the level compression circuit 24 supplied to the input terminal a is selected.

The control signal from the terminal 27 and the error pulse from the terminal 28 are supplied to the AND gate 29. The output signal of the AND gate 29 is supplied to the OR gate 25. The error pulse is a pulse that goes high at a timing synchronized with the error pixel, as in the above-described embodiment. The OR gate 25 converts all or some bits of the 8-bit parallel one-sample data output from the switch circuit 23 to a high level by the output of the AND gate 29.

For example, to convert all 8 bits to high level,
An OR gate 25 is constituted by eight OR gates, each bit of one sample of data is supplied to each OR gate, and eight OR gates are provided.
The output of the AND gate 29 is supplied commonly to the OR gate. In this case, only some upper bits including the most significant bit may be converted to a high level.

In the other embodiment of the present invention described above, in the error display state, a reproduced digital image signal is generated at the output terminal 22, and only the data of the erroneous pixel is set to high-level data at the output terminal 26. An output signal whose level has been converted to a lower level is obtained. Therefore, a display in which an error display of a high-brightness dot such as white is superimposed on a low-level reproduced image by the image monitor is obtained.

〔The invention's effect〕

According to the present invention, the error pixel (sample data) is forcibly converted into a high-brightness signal such as white by the error pulse, so that the error state can be easily seen on the display screen. Further, according to the present invention, since the error display is superimposed on the screen on which the image being reproduced whose luminance has been reduced is displayed, it is possible to know the content of the reproduced image at the same time as grasping the error state. Furthermore, according to the present invention, error correction or error correction is always in operation, and a high-quality reproduced signal without error is output as a main output signal. Therefore, the error is monitored even during operation of the device. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of another embodiment of the present invention. Explanation of main symbols in the drawings 1: digital signal processing circuit, 2: D / A converter, 6: output terminal of main analog reproduced image signal, 9, 10: switch circuit, 1
5: Output terminal for output signal for error display, 18: Terminal to which error pulse is input.

Claims (1)

(57) [Claims] A digital signal processing circuit for supplying a reproduced image signal, detecting an error in a pixel unit of the reproduced image signal, correcting the detected error, and correcting an error that cannot be corrected; A first output terminal from which an error-corrected and error-corrected image signal is output from the signal processing circuit, and a first level for converting information of an image in which an error has been detected by the digital signal processing circuit into a high-level signal Conversion means; second level conversion means for outputting a low-level signal obtained by attenuating the level of the image signal from the digital signal processing circuit; second output terminal to which a monitor is connected; A signal converted to a high level by the first level conversion means as pixel information indicating that the error information from the circuit is an error. A signal output to the second output terminal and converted to a low level by the second level conversion means as pixel information indicating that error information from the digital signal processing circuit is not an error is output to the second output terminal. And a means for outputting to a terminal.