JP2600256B2 - Memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device suitable for applying to image reduction.

[Summary of the Invention]

According to the present invention, in order to form a 1 / n reduced image, an arithmetic processing is performed for every n lines of an input video signal to obtain a line signal whose band is limited in the vertical direction (line direction). This is to reduce the aliasing distortion in the direction and obtain a good reduced image.

[Conventional technology]

Conventionally, in order to remove noise from a reproduced video signal from a video tape recorder, it is known to extract a noise component using, for example, frame correlation, multiply the noise component by a feedback constant K, and then subtract from the input video signal. Have been.
The reason for multiplying by the feedback constant K is to reduce the degree to which noise that is not originally noise when there is no frame correlation is subtracted as noise, thereby suppressing image quality deterioration.

FIG. 3 shows the configuration of a noise reducer utilizing, for example, frame correlation. In the figure, the input video signal S _IN supplied to the terminal (1), after being converted to digital signals by the A / D converter (2), a delay time of one frame via a subtractor (3) Is supplied to a frame memory (4) that constitutes a delay line. The input video signal S _IN supplied to the terminal (1) is subtracted by a subtracter (5).
To the subtracter (5), the input video signal S _IN 'one frame before is supplied from the frame memory (4), and the subtracter (5) outputs a signal having no frame correlation, that is, a signal having no frame correlation. The noise component S _N is obtained. The noise component S _N obtained from the subtracter (5) is supplied to a subtractor (3) after being multiplied by a feedback constant (coefficient) K in a coefficient unit (6), and is subtracted from the input video signal S _IN. You. The output signal of the frame memory (4) is supplied to a D / A converter (7).
In after being an analog signal, is supplied to the output terminal (8), this pin (8), the output video signal S _OUT, which is the removal of the noise is obtained.

Further, the input video signal S _IN supplied to the terminal (1) is supplied to a synchronization separation circuit (9), and the synchronization separation circuit (9)
The synchronization signal SYNC obtained is supplied to the address control circuit (10). Then, the write address and the read address of the frame memory (4) are controlled by the address control circuit (10), and the input video signal of one frame before is obtained from the frame memory (4) as described above. I have.

[Problems to be solved by the invention]

Incidentally, it has been proposed to form a reduced image by using a noise reducer circuit as shown in the example of FIG. In this case, the line of the input video signal S _IN feedback constant K in the state of 0 is decimated in accordance with the reduction ratio, reduced screen of the frame memory (4) under the control of the address control circuit (10) to (4B) By being sequentially written, reduction in the vertical direction (line direction) is performed. For example, when forming a 1/3 reduced image, as shown in FIG.
_(a) , l _{(a + 1)} , l _{(a + 2)} , ‥‥, line l _(a) , l _{(a + 3)} , l
_{(a + 6)} , written every three lines as indicated by ‥‥. Note that, in the horizontal direction as well, reduction is performed by thinning out in units of sampling information in accordance with the reduction ratio.

However, when a reduced image is formed in this way, the sampling frequency in each of the vertical and horizontal directions becomes lower as a result, so that aliasing distortion occurs in the vertical and horizontal directions, resulting in a reduced quality image having poor quality. there were.

Here, in the horizontal direction, since the frequency is high, A /
By inserting a low-pass filter before the D converter (2) to limit the band of the input video signal S _IN , it is possible to prevent aliasing from occurring.

The present invention has been made in view of the foregoing, and has as its object to reduce aliasing distortion in the vertical direction at the time of forming a reduced image to obtain a good reduced image.

[Means for solving the problem]

According to the present invention, the input video signal S _IN is supplied to the memory (4) via the first subtractor (3), and the output signal of the memory (4) is converted from the input video signal S _IN to the second subtractor (5). ), And the output signal of the second subtractor (5) is converted to a coefficient unit (6).
And is multiplied by a feedback constant K. This coefficient unit (6)
The output force signal is supplied to a first subtractor (3) and subtracted from the input video signal S _IN , and the output video signal S is output from the memory (4).
_A memory device from which _OUT can be obtained. When forming a 1 / n reduced image, a memory (4) is provided with an operation buffer unit (4A) and a reduced screen unit (4B), and each line of the input video signal S _IN In the first line, the feedback constant K of the coefficient unit (6) is set to 0, the output signal of the first subtractor (3) is written to the arithmetic buffer unit (4A) of the memory (4), and the second ~
In the (n-1) th line, data is read out from the operation buffer unit (4A) of the memory (4), the feedback constant K of the coefficient unit (6) is set to a predetermined value, and the output signal of the first subtractor (3) is set. Is written to the operation buffer unit (4A) of the memory (4), data is read out from the operation buffer unit (4A) of the memory (4) on the n-th line, and the coefficient unit (6)
Is set to a predetermined value, and the output signal of the first subtracter (3) is written to the reduced screen section (4B) of the memory (4).

[Action]

In the above-described configuration, the arithmetic processing is performed for every n lines of the input video signal _SIN , and a line signal whose band is limited in the vertical direction (line direction) is obtained, which is written to the reduced screen section (4B) of the memory (4). It is. That is, the first and second
An IIR filter (recursive filter) is formed by the subtracters (3) and (5), the memory (4), and the coefficient unit (6), and the band is limited in the vertical direction. Therefore, the folding distortion in the vertical direction is reduced.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In this example, a 1/3 reduced image is formed.

The circuit configuration of this example is the same as that of the example in FIG. 3, but when forming a reduced image, a frame buffer (4A) and a reduced screen unit (4B) are provided in the frame memory (4). As shown in FIG. 1, three lines of input video signal _{S IN (l (a) ~l} (a + 2), l (a + 3) ~l (a + 5), each ‥‥] The arithmetic processing is performed using the arithmetic buffer unit (4A), and the line signal whose band is limited in the vertical direction is written to the reduced screen unit (4B). The feedback constant K of the unit (6) is controlled as follows.

The three lines l _{(a) to} l _{(a + 2)} of the input video signal S _IN will be described. In the line l _(a) , as shown in FIG. 2A, the feedback constant K of the coefficient unit (6) is It is set to 0 and the arithmetic unit (3)
Is written into the calculation buffer section (4A) of the frame memory (4). In the l _{(a + 1)} line, the data written in the l _(a) line is read from the arithmetic buffer unit (4A) of the frame memory (4) as shown in FIG. The feedback constant K of 6) is halved, and the output signal of the subtracter (3) is written to the arithmetic buffer unit (4A) of the frame memory (4). And l _{(a + 2)}
In the line ₍₁₎ , the data written in the line l _{(a + 1)} is read from the arithmetic buffer unit (4A) of the frame memory (4) as shown in FIG.
Is reduced to 1/2, and the output signal of the subtracter (3) is written to the reduced screen section (4B) of the frame memory (4). The output signal 1 of the subtractor (3) written to the reduced screen portion (4B) of the frame memory (4) is represented by the following equation.

Hereinafter, the same processing as described above is performed for every three lines of the _SIN of the input video signal.

In the horizontal direction, the sampling information is thinned out to, for example, 1/3 and written to the reduced screen section (4B) of the frame memory (4).

As described above, in this example, the arithmetic processing is performed for every three lines of the input video signal _SIN , and as is apparent from the equation (1), a line signal whose band is limited in the vertical direction is obtained. It is written to the reduced screen section (4B). That is, for every three lines, a line signal band-limited by the IIR filter formed by the subtracters (3) and (5), the frame memory (4) and the coefficient unit (6) is obtained, and this is the memory (4) Is written to the reduced screen part (4B) of

As described above, according to the present embodiment, the arithmetic processing is performed for every three lines of the input video signal _SIN , and the line signal whose band is limited in the vertical direction is reduced to the reduced screen portion (4B) of the frame memory (4).
, And a reduced image is formed, so that it is possible to obtain a good 1/3 reduced image with reduced aliasing in the vertical direction.

In the above-described embodiment, the value of the feedback constant K of the coefficient unit (6) is set to 0 for the first line, 1/2 for the second line, and 1/2 for the third line. However, needless to say, the value of the feedback constant K is not limited to this. For example, 0 for the first line of three lines, and
It may be 1/4, and 3/4 on the third line. In this case, the output of the subtracter (3) written to the reduced screen part (4B) of the frame memory (4) corresponding to the three lines l _{(a) to} l _{(a + 2)} of the input video signal S _IN The signal 1 is represented by the following equation.

Further, in the above-described embodiment, an example in which a 1/3 reduced image is formed has been described. However, the present invention can be generally applied similarly to forming a 1 / n reduced image.

Further, in the above-described embodiment, the example in which the frame memory (4) is used as the memory has been described. However, the same configuration can be obtained by using the field memory.

〔The invention's effect〕

According to the present invention described above, in order to form a 1 / n reduced image, a line signal that is band-limited in the vertical direction (line direction) is obtained by performing arithmetic processing for every n lines of the input video signal. Therefore, it is possible to obtain a good reduced image with reduced aliasing distortion in the vertical direction.

[Brief description of the drawings]

1 and 2 are diagrams for explaining an embodiment of the present invention, FIG. 3 is a diagram showing an example of a noise reducer, and FIG. 4 is an explanatory diagram of a conventional example. (3) and (5) are subtractors, (4) is a frame memory, and (6) is a coefficient unit.

Claims (1)

(57) [Claims] An input video signal is supplied to a memory via a first subtractor, and an output signal of the memory is subtracted from the input video signal by a second subtractor, and an output of the second subtractor is output. A memory device in which a signal is supplied to a coefficient unit and multiplied by a feedback constant, and an output signal of the coefficient unit is supplied to the first subtractor and subtracted from the input video signal, and an output video signal is obtained from the memory In forming a 1 / n reduced image, the memory is provided with an operation buffer unit and a reduced screen unit, and the feedback constant of the coefficient unit is 0 in the first line for every n lines of the input video signal.
Then, the output signal of the first subtractor is written to the operation buffer unit of the memory, and data is read out from the operation buffer unit of the memory and the data of the coefficient unit is read out in the second to (n-1) th lines. The feedback constant is set to a predetermined value, the output signal of the first subtractor is written to the operation buffer of the memory, and the data is read out from the operation buffer of the memory on the n-th line. Wherein the feedback constant is set to a predetermined value and the output signal of the first subtractor is written to a reduced screen portion of the memory.