JP2595874B2 - Multi-chip module - Google Patents

Multi-chip module

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Publication number
JP2595874B2
JP2595874B2 JP5215617A JP21561793A JP2595874B2 JP 2595874 B2 JP2595874 B2 JP 2595874B2 JP 5215617 A JP5215617 A JP 5215617A JP 21561793 A JP21561793 A JP 21561793A JP 2595874 B2 JP2595874 B2 JP 2595874B2
Authority
JP
Japan
Prior art keywords
substrate
chip module
chip
circuit
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5215617A
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Japanese (ja)
Other versions
JPH0766359A (en
Inventor
武夫 吉川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
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Priority to JP5215617A priority Critical patent/JP2595874B2/en
Publication of JPH0766359A publication Critical patent/JPH0766359A/en
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Publication of JP2595874B2 publication Critical patent/JP2595874B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、マルチチップモジュー
ルに関し、特にシリコン基板に複数のＩＣチップが搭載
されるマルチチップモジュールに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module, and more particularly to a multi-chip module in which a plurality of IC chips are mounted on a silicon substrate.

【０００２】[0002]

【従来の技術】従来、この種のマルチチップモジュール
は、配線層を有する基板上に、トランジスタ、抵抗等の
能動、受動の単独または複数の素子が集積されてそれぞ
れ特定の回路機能を有する複数のＩＣチップを搭載し、
さらにＩＣチップと基板の配線層とを半田バンプあるい
はボンディングワイヤなどによって接続して構成されて
いた。2. Description of the Related Art Conventionally, a multi-chip module of this type has a plurality of active or passive elements such as transistors and resistors integrated on a substrate having a wiring layer and a plurality of elements each having a specific circuit function. Equipped with IC chip,
Further, the IC chip and the wiring layer of the substrate are connected by solder bumps or bonding wires.

【０００３】例えば、多数のチップを搭載し、多数の入
出力ピンを有し、冷却能力の高いマルチパッケージとし
て特開平１−３０８０５７号に開示されたマルチチップ
パッケージを図２に示す。このパッケージは、キャビテ
ィ構造の凹部が設けられたセラミック基板１１にチップ
１６が実装される。チップ１６は、ワイヤボンディング
１７によってボンディングパッドに接続し、ボンディン
グパッド１３はスルーホールなどの内部配線１４を通じ
て接続パッド１９と接続する。セラミック多層配線基板
１２の上面にも接続パッド２０が設けられ、半田バンプ
２１を介して接続パッド１９と機械的に圧着されて電気
的に接続する。接続パッド２０は内部配線を通じて、ろ
う付けによって接着されている入出力ピン１５に接続さ
れる。セラミック多層配線基板１２とセラミック基板１
１との接合部８は、半田により気密に封止される。[0003] For example, FIG. 2 shows a multi-chip package disclosed in Japanese Patent Application Laid-Open No. 1-308057 as a multi-package having a large number of chips, a large number of input / output pins, and a high cooling capability. In this package, a chip 16 is mounted on a ceramic substrate 11 provided with a concave portion having a cavity structure. The chip 16 is connected to bonding pads by wire bonding 17, and the bonding pads 13 are connected to connection pads 19 through internal wirings 14 such as through holes. A connection pad 20 is also provided on the upper surface of the ceramic multilayer wiring board 12, and is mechanically pressed and electrically connected to the connection pad 19 via a solder bump 21. The connection pad 20 is connected to the input / output pin 15 bonded by brazing through an internal wiring. Ceramic multilayer wiring substrate 12 and ceramic substrate 1
The joint portion 8 with 1 is hermetically sealed with solder.

【０００４】また、大型のシリコン基板上に絶縁層を介
して複数の金属配線層を形成し、基板の四辺に多数の信
号および電源接続用のパッドを形成し、複数の大規模集
積回路をその基板上に両表面が対峙するように半田ボー
ルで接続されたシステムＬＳＩが特開平２−２３２９５
９号に開示されている。Further, a plurality of metal wiring layers are formed on a large silicon substrate via an insulating layer, and a large number of pads for signal and power connection are formed on four sides of the substrate. Japanese Patent Application Laid-Open No. H2-223295 discloses a system LSI connected by solder balls so that both surfaces face each other on a substrate
No. 9.

【０００５】一般には、ＩＣチップ、シリコン基板、シ
リコン基板上の配線部はそれぞれ別々に製造され、その
後マルチチップモジュールとして組み立て、バンプまた
はボンディングワイヤで接続し、キャップ、エポキシ樹
脂による一括封止、またはチップ別の個別パッケージン
グ封止を経て製造される。In general, an IC chip, a silicon substrate, and a wiring portion on the silicon substrate are separately manufactured, then assembled as a multi-chip module, connected by bumps or bonding wires, and collectively sealed with a cap, epoxy resin, or It is manufactured through individual packaging sealing for each chip.

【０００６】ここで、誘電体分離（ｄｉｅｌｅｃｔｒｉ
ｃ ｉｓｏｌａｔｉｏｎ；以下ＤＩという）技術と呼ば
れる絶縁分離法について簡単に説明する。まず、例えば
ｎ型シリコンウエハの表面をＫＯＨなどにより異方性エ
ッチングを行い、所定の深さまでくさび状にエッチング
する。次に、このエッチング表面を酸化し、所定の厚さ
まで多結晶シリコンを堆積する。次に、ｎ型シリコンが
酸化膜で島状に分離されるまで研削、研磨を行なう。そ
して研削、研磨面を表面または上面として、形成された
ＤＩ分離島に拡散を行なう。Here, dielectric isolation (dielectric
A brief description will be given of an insulation separation method called a technique (hereinafter referred to as DI). First, for example, the surface of an n-type silicon wafer is anisotropically etched with KOH or the like, and is etched in a wedge shape to a predetermined depth. Next, the etched surface is oxidized to deposit polycrystalline silicon to a predetermined thickness. Next, grinding and polishing are performed until the n-type silicon is separated into islands by the oxide film. Then, diffusion is performed on the formed DI separation island with the grinding or polishing surface as the surface or upper surface.

【０００７】従来は、このようにして生成されたＤＩ分
離島を利用する場合は、分離島の上に単体の回路素子が
生成されていた。Conventionally, when utilizing the DI isolated islands generated in this way, a single circuit element has been generated on the isolated islands.

【０００８】[0008]

【発明が解決しようとする課題】上述のように従来のマ
ルチチップモジュールは、ＩＣチップと基板とが接近し
ているため、ＩＣチップから接続部を通りシリコン基板
にリーク電流が流れ、トランジスタのＩ−Ｖ特性が劣化
し、さらに、接続部とシリコン基板を通してチップ間に
流れるリーク電流のためチップ間の絶縁耐圧が劣化する
という欠点があった。As described above, in the conventional multi-chip module, since the IC chip and the substrate are close to each other, a leak current flows from the IC chip to the silicon substrate through the connection portion, and the I / O of the transistor is reduced. -V characteristics are deteriorated, and furthermore, there is a disadvantage that the dielectric strength between chips is deteriorated due to a leak current flowing between the chips through the connection portion and the silicon substrate.

【０００９】また、接続部が物理的に大きな占有空間を
有し、マルチチップモジュールの小型化が制限されると
いう欠点があり、さらに、製造工程が複雑でしかも長期
間に渡るため、製造コストが高くなるという欠点があっ
た。Further, there is a disadvantage that the connection portion has a physically large occupied space, and the miniaturization of the multi-chip module is limited. In addition, the manufacturing process is complicated and it takes a long time, so that the manufacturing cost is reduced. There was a drawback that it became high.

【００１０】本発明の目的は、上述の問題点を解消し、
マルチチップと共通基板の一体化による小型化と信頼性
向上、チップから共通基板に流れる基板正孔電流を減少
し、チップ間の絶縁破壊に対する強度を向上できるマル
チチップモジュールを提供することにある。An object of the present invention is to solve the above-mentioned problems,
It is an object of the present invention to provide a multi-chip module capable of miniaturizing and improving reliability by integrating a multi-chip and a common substrate, reducing a substrate hole current flowing from a chip to a common substrate, and improving strength against dielectric breakdown between chips.

【００１１】[0011]

【課題を解決するための手段】本発明のマルチチップモ
ジュールは、共通基板に形成される複数の分離島と、各
分離島にそれぞれ複数の能動素子と受動素子を集積して
形成される複数の回路部と、各回路部相互間を接続する
配線部とを有する。According to the present invention, there is provided a multi-chip module comprising: a plurality of isolated islands formed on a common substrate; and a plurality of integrated elements formed by integrating a plurality of active elements and passive elements on each isolated island. It has a circuit section and a wiring section for connecting the circuit sections to each other.

【００１２】また、共通基板に形成される複数の分離島
は、誘電体分離技術によって形成されるのが好ましい。Preferably, the plurality of isolation islands formed on the common substrate are formed by a dielectric isolation technique.

【００１３】[0013]

【作用】複数の回路素子が集積された複数の回路部が、
共通基板に形成された複数の分離島にそれぞれ形成さ
れ、かつ、それら相互間は配線部により接続される。し
たがって、回路部と共通基板の基部との間、および回路
部相互間が分離島によって隔てられる。A plurality of circuit parts in which a plurality of circuit elements are integrated are
The plurality of islands are formed on the common substrate, and are connected to each other by a wiring portion. Therefore, between the circuit portion and the base of the common substrate and between the circuit portions are separated by the separation island.

【００１４】[0014]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。Next, embodiments of the present invention will be described with reference to the drawings.

【００１５】図１は本発明のマルチチップモジュールの
一実施例の断面図である。FIG. 1 is a sectional view of one embodiment of the multichip module of the present invention.

【００１６】図１において、このマルチチップモジュー
ル９は、多結晶シリコンからなるシリコン基板１、ＤＩ
技術による分離用の酸化膜２、酸化膜２によって多結晶
シリコン基板１内部に分離形成されるＤＩ分離島３（図
には３個の断面を示す）、各ＤＩ分離島３に複数のトラ
ンジスタ、抵抗等を集積して生成された１チップ相当の
回路素子４、ＳｉＯ2 などの絶縁膜で形成されるパター
ン間の層間膜５、ＤＩ分離島間の回路を接続するＡｌ等
の金属配線６、外部接続用のパッド７、およびマルチチ
ップモジュール全体を被うカバー８からなる。In FIG. 1, a multi-chip module 9 includes a silicon substrate 1 made of polycrystalline silicon, a DI
An oxide film 2 for isolation by a technique, DI isolation islands 3 (three cross sections are shown in the figure) separated and formed inside the polycrystalline silicon substrate 1 by the oxide film 2, a plurality of transistors are provided in each DI isolation island 3, A circuit element 4 equivalent to one chip generated by integrating resistors and the like, an interlayer film 5 between patterns formed of an insulating film such as SiO2, a metal wiring 6 such as Al for connecting a circuit between DI isolation islands, and the outside It consists of connection pads 7 and a cover 8 covering the whole multi-chip module.

【００１７】多結晶シリコンからなるシリコン基板１
は、通常ｐ型シリコン（ｐ−ｓｕｂ）、ｎ型シリコン
（ｎ−ｓｕｂ）が用いられる。ＤＩ分離島３は、通常ｎ
−ｗｅｌｌまたはｐ−ｗｅｌｌと呼ばれるトランジスタ
素子などの拡散領域となる。Silicon substrate 1 made of polycrystalline silicon
Is usually made of p-type silicon (p-sub) and n-type silicon (n-sub). DI separation island 3 is usually n
It becomes a diffusion region such as a transistor element called -well or p-well.

【００１８】複数の回路素子４が集積された複数の回路
部は、共通基板１に形成された各分離島３の上にそれぞ
れ形成され、回路素子４相互間は金属配線６により接続
される。したがって、回路部４と共通基板１の基部との
間、および回路部相互間が分離島３と酸化膜２によって
隔てられるので、これらの間の絶縁耐圧が向上するとと
もに、シリコン基板に漏洩するリーク電流が減少し、回
路特性も向上する。A plurality of circuit sections on which a plurality of circuit elements 4 are integrated are formed on each of the isolated islands 3 formed on the common substrate 1, and the circuit elements 4 are connected to each other by metal wiring 6. Therefore, the circuit portion 4 and the base of the common substrate 1 and the circuit portion are separated from each other by the isolation island 3 and the oxide film 2, so that the withstand voltage between them is improved, and the leakage leakage to the silicon substrate is achieved. The current is reduced and the circuit characteristics are improved.

【００１９】[0019]

【発明の効果】上述のように本発明のマルチチップモジ
ュールは、共通基板に複数の分離島を誘電体分離技術な
どにより形成し、各分離島にそれぞれ複数の能動素子と
受動素子を集積して複数の回路部を形成し、各回路部相
互間を配線部により接続する構造とすることにより、マ
ルチチップモジュールの小型化の実現と、回路間接続配
線の信頼性向上と、誘電体分離技術を用いた分離島の酸
化膜による各分離島の回路間の絶縁耐圧の向上と、シリ
コン基板に流れるリーク電流減少による回路特性の向上
という効果がある。As described above, in the multichip module of the present invention, a plurality of isolation islands are formed on a common substrate by a dielectric isolation technique or the like, and a plurality of active elements and passive elements are integrated on each isolation island. By forming a plurality of circuit parts and connecting each circuit part with a wiring part, it is possible to realize the miniaturization of the multi-chip module, the improvement of the reliability of the wiring between the circuits, and the dielectric isolation technology. The oxide film of the used isolation islands has the effect of improving the dielectric strength between the circuits of each isolation island and improving the circuit characteristics by reducing the leak current flowing through the silicon substrate.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明のマルチチップモジュールの一実施例の
断面図である。FIG. 1 is a sectional view of one embodiment of a multichip module of the present invention.

【図２】従来のマルチチップモジュールの一実施例を示
す図である。 （Ａ）断面図 （Ｂ）半田バンプ部の部分拡大図FIG. 2 is a diagram showing one embodiment of a conventional multichip module. (A) Sectional view (B) Partial enlarged view of solder bump

【符号の説明】 １ シリコン基板 ２ ＤＩ分離用ＳｉＯ2 ３ ＤＩ分離島 ４ 回路素子 ５ 層間膜 ６ 金属配線 ７ パッド ８ カバー ９ マルチチップモジュール[Description of Signs] 1 silicon substrate 2 SiO 2 for DI separation 3 DI separation island 4 circuit element 5 interlayer film 6 metal wiring 7 pad 8 cover 9 multi-chip module

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 共通基板上に複数のＩＣチップが実装さ
れるマルチチップモジュールにおいて、 前記共通基板に形成される複数の分離島と、前記各分離
島にそれぞれ複数の能動素子と受動素子を集積して形成
される複数の回路部と、前記各回路部相互間を接続する
配線部とを有することを特徴とするマルチチップモジュ
ール。1. A multi-chip module in which a plurality of IC chips are mounted on a common substrate, wherein a plurality of separated islands formed on the common substrate, and a plurality of active elements and passive elements are integrated on each of the separated islands. A multi-chip module comprising: a plurality of circuit units formed as described above; and a wiring unit connecting the circuit units to each other.
JP5215617A 1993-08-31 1993-08-31 Multi-chip module Expired - Lifetime JP2595874B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5215617A JP2595874B2 (en) 1993-08-31 1993-08-31 Multi-chip module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5215617A JP2595874B2 (en) 1993-08-31 1993-08-31 Multi-chip module

Publications (2)

Publication Number Publication Date
JPH0766359A JPH0766359A (en) 1995-03-10
JP2595874B2 true JP2595874B2 (en) 1997-04-02

Family

ID=16675380

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5215617A Expired - Lifetime JP2595874B2 (en) 1993-08-31 1993-08-31 Multi-chip module

Country Status (1)

Country Link
JP (1) JP2595874B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6214751U (en) * 1985-07-10 1987-01-29
JPH0411751A (en) * 1990-04-28 1992-01-16 Nec Corp Dielectric material isolation type semiconductor device

Also Published As

Publication number Publication date
JPH0766359A (en) 1995-03-10

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