JP2595873B2 - Lead frame tip placement design method - Google Patents
Lead frame tip placement design methodInfo
- Publication number
- JP2595873B2 JP2595873B2 JP5193793A JP19379393A JP2595873B2 JP 2595873 B2 JP2595873 B2 JP 2595873B2 JP 5193793 A JP5193793 A JP 5193793A JP 19379393 A JP19379393 A JP 19379393A JP 2595873 B2 JP2595873 B2 JP 2595873B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- line
- circles
- circle
- common
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、リードフレーム先端配
置設計方法に関し、特にリードフレームの一定幅と一定
間隔とを制約するリードフレーム先端配置設計方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a lead frame tip arrangement, and more particularly to a lead frame tip placement design method for restricting a fixed width and a fixed interval of a lead frame.
【０００２】[0002]
【従来の技術】図３は従来のリードフレーム先端配置設
計方法を示すフローチャート、図４は、図３に示す方法
を用いて設計したリードフレームの先端配置図である。2. Description of the Related Art FIG. 3 is a flowchart showing a conventional lead frame tip arrangement designing method. FIG. 4 is a lead frame tip arrangement diagram designed using the method shown in FIG.
【０００３】図３に示すリードフレーム先端配置設計方
法は、次のような動作ステップで行われる。The lead frame tip arrangement design method shown in FIG. 3 is performed in the following operation steps.
【０００４】１）動作ステップＳ１１では、チップ外形
１とリードフレームのボンディングのためのオフセット
量を示すキャビティーライン２とを入力し、キャビティ
ーライン２と対向するチップ外形１の一辺に平行なオフ
セットライン５３とリードフレーム先端数ｎの設計条件
を入力する。1) In an operation step S11, a chip outline 1 and a cavity line 2 indicating an offset amount for bonding a lead frame are input, and an offset parallel to one side of the chip outline 1 facing the cavity line 2 is input. The design conditions for the line 53 and the number n of the lead frame tips are input.
【０００５】２）動作ステップＳ１２ではキャビティー
ライン５２とオフセットライン５３とをリードフレーム
先端数ｎに対して２ｎ−１個に分割し、キャビティーラ
イン５２，オフセットランイン５３上の対応する分割点
を結んだ直線５４〜５９を作成し、これら直線で区切ら
れる部分を交互にリードフレーム先端部６０〜６２及び
その間隙部６３，６４としリードフレーム先端部６０〜
６２を作成する。2) In operation S12, the cavity line 52 and the offset line 53 are divided into 2n-1 pieces with respect to the number n of lead frame tips, and the corresponding dividing points on the cavity line 52 and the offset run-in 53 are divided. Are formed, and the portions separated by these straight lines are alternately referred to as lead frame tips 60 to 62 and gaps 63 and 64 therebetween.
62 is created.
【０００６】３）動作ステップＳ１３では設計者がリー
ドフレーム先端部２３〜２５を一定幅、一定間隔に修正
する。3) In step S13, the designer corrects the lead frame tips 23 to 25 to have a constant width and a constant interval.
【０００７】４）動作ステップＳ１４では、リードフレ
ーム先端２３〜２５が設計条件に適当か評価する。適当
であれば動作ステップＳ１５に進み適当でなければ動作
ステップＳ１３に戻る。[0007] 4) In operation S14, it is evaluated whether the leading ends 23 to 25 of the lead frame are suitable for design conditions. If appropriate, the operation proceeds to operation step S15, and if not, the operation returns to operation step S13.
【０００８】５）動作ステップＳ１５では、作成された
リードフレームを表示する。このように、従来のリード
フレーム先端配置設計方法は試行錯誤的に作業が行われ
ていた。5) In operation S15, the created lead frame is displayed. As described above, the conventional lead frame tip arrangement design method has been performed by trial and error.
【０００９】[0009]
【発明が解決しようとする課題】しかしながら、このよ
うな上述した従来のリードフレーム先端配置設計方式
は、キャビティーラインに沿って測ったリードフレーム
先端部の長さ及びその間隙の長さを一定寸法とするた
め、リードフレーム先端部の幅とリードフレーム先端間
隔は一定ではなくなり、一般にリードフレーム先端部の
配列の両端部のものの幅が狭くなってしまうためチップ
とリードフレームとをワイヤーボンディングするときに
安定性がリードフレーム先端部の配列の両端に近いほど
悪くなるという欠点があった。However, in the above-described conventional lead frame tip arrangement design method, the length of the lead frame tip portion measured along the cavity line and the length of the gap therebetween are fixed. Therefore, the width of the lead frame tip and the lead frame tip interval are not constant, and generally the width of both ends of the arrangement of the lead frame tip becomes narrow. There is a disadvantage that the stability becomes worse as it approaches the both ends of the arrangement of the lead frame tip.
【００１０】[0010]
【課題を解決するための手段】本発明のリードフレーム
先端配置設計方法は、チップ外形とのリードフレームの
ボンディングのためのオフセット量を示すキャビティー
ラインを設定し、このキャビティーラインより前記チッ
プ外形からさらに離してオフセットラインを設定し、予
め定めた大きさの複数の第１の円の中心が前記キャビテ
ィーライン上に位置し、予め定めた大きさの前記第１の
円と同数の第２の円の中心が前記オフセットライン上に
位置し、隣り合う２個の前記第１の円及びこれら第１の
円に対応して隣り合う２個の前記第２の円が共通に接す
る中間共通接線を有するように前記複数の第１の円及び
前記複数の第２の円を配置し、前記中間共通接線または
両側部の前記第１の円及び前記第２の円に共通に接する
側面共通接線に挟まれた部分をリードフレーム先端部ま
たはリードフレーム先端部の間とすることを特徴とす
る。According to the lead frame tip arrangement design method of the present invention, a cavity line indicating an offset amount for bonding a lead frame to a chip outline is set, and the chip outline is determined from the cavity line. The offset lines are further set apart from each other, and the centers of a plurality of first circles having a predetermined size are located on the cavity line, and the same number of second circles as the first circles having a predetermined size are provided. Are located on the offset line, and two adjacent first circles and an intermediate common tangent where two adjacent second circles corresponding to the first circles are in common contact The plurality of first circles and the plurality of second circles are arranged so as to have an intermediate common tangent or a side common tangent common to both sides of the first circle and the second circle. Sandwich Characterized by the portion and between the lead frame tip or leadframe tip.
【００１１】本発明のリードフレーム先端配置設計方法
は、チップ外形とのリードフレームのボンディングのた
めのオフセット量を示すキャビティーラインを設定し、
このキャビティーラインより前記チップ外形からさらに
離してオフセットラインを設定し、リードフレーム先端
部の一側辺となる一の共通接線を設定し、中心が前記キ
ャビティーライン上にあり予め定めた大きさの第１の円
及び中心が前記オフセットライン上にあり予め定めた大
きさの第２の円が前記一の共通接線に共通に接するよう
に配置し、当該第１の円及び第２の円に共通に接する他
の共通接線に共通に接する他の第１の円及び第２の円を
配置し、さらに当該他の第１の円及び第２の円に共通に
接するさらに他の共通接線を求めるという操作を繰り返
し、この操作で求めた複数の共通接線で区切られた領域
を交互にリードフレーム先端部とし、予め定めた範囲内
に予め定めた数のリードフレーム先端部が配置されるよ
うに前記第１の円及び第２の円の大きさを修正していく
ことを特徴とする。According to the lead frame tip arrangement design method of the present invention, a cavity line indicating an offset amount for bonding a lead frame to a chip outer shape is set,
An offset line is set further away from the chip outer shape than the cavity line, a common tangent line that is one side of the lead frame tip is set, and the center is on the cavity line and a predetermined size is set. Are arranged so that the first circle and the center of the second circle are on the offset line and the second circle of a predetermined size is in common contact with the one common tangent line. Another first and second circles that are in common contact with another common tangent line that is in common contact are arranged, and further another common tangent line that is in common contact with the other first and second circles is determined. The above operation is repeated, and the area divided by a plurality of common tangent lines obtained by this operation is alternately used as a lead frame tip, and a predetermined number of lead frame tips are arranged within a predetermined range. First circle Characterized in that to continue to modify the beauty magnitude of the second circle.
【００１２】[0012]
【実施例】次に、本発明の実施例について図面を参照し
て詳細に説明する。Next, embodiments of the present invention will be described in detail with reference to the drawings.
【００１３】図１は、本発明の一実施例を示すフローチ
ャートである。図２は、図１に示す実施例で設計したリ
ードフレーム先端配置を示す図である。FIG. 1 is a flowchart showing an embodiment of the present invention. FIG. 2 is a diagram showing a lead frame tip arrangement designed in the embodiment shown in FIG.
【００１４】図１に従って本実施例を説明する。This embodiment will be described with reference to FIG.
【００１５】１）動作ステップＳ１では、チップ外形１
とリードフレームのボンディングのためのオフセット量
を示すキャビディーライン２と一方の側のリードフレー
ム先端側面ライン４を作成し、キャビティーラインに対
するオフセットライン３とリードフレーム先端数の設計
条件を入力する。1) In the operation step S1, the chip outer shape 1
A cavity line 2 indicating the offset amount for bonding the lead frame and a lead frame tip side surface line 4 on one side are created, and design conditions for the offset line 3 with respect to the cavity line and the number of lead frame tips are input.
【００１６】２）動作ステップＳ２では、リードフレー
ム先端幅、リードフレーム先端間隔を示す円１０〜１４
の直径とオフセットライン３の部分でのリードフレーム
幅、リードフレーム間隔を示す円１５〜１９の直径とし
て予め定めた値（例えば、ｒ＝５μｍ）を入力する。2) In the operation step S2, circles 10 to 14 indicating the leading end width of the lead frame and the leading end distance of the lead frame.
A value (for example, r = 5 μm) predetermined as the diameter of circles 15 to 19 indicating the lead frame width at the portion of the offset line 3 and the lead frame interval at the offset line 3 is input.
【００１７】３）動作ステップＳ３では、リードフレー
ム先端側面ライン４に接して、且つ、中心がキャビティ
ーライン２上になる円１０の中心座標を求め、同様に、
リードフレーム側面ライン４に接して、且つ、中心がオ
フセットライン３上になる円１５の中心座標を求める。3) In the operation step S3, the center coordinates of a circle 10 which is in contact with the lead frame tip side surface line 4 and whose center is on the cavity line 2 are obtained.
The center coordinates of a circle 15 which is in contact with the lead frame side surface line 4 and whose center is on the offset line 3 are obtained.
【００１８】４）動作ステップＳ４では、円１０，１５
が他方の側のリードフレーム先端側面ライン９の内側に
入っているかチェックし、入っていれば動作ステップＳ
５、いなければ動作ステップＳ６を行う。4) In operation step S4, circles 10, 15
Is inside the lead frame tip side line 9 on the other side, and if yes, operation step S
5. If not, the operation step S6 is performed.
【００１９】５）動作ステップＳ５では、円１０と円１
５の共通接線５を求める。次に再び動作ステップＳ３を
行い、円１１，１６の中心座標を求め、さらに動作ステ
ップＳ４，Ｓ５を行うというように動作ステップＳ３〜
Ｓ５を繰り返し、円１２、１３…、円１７、１８…、共
通接線６，７…を求めていく。5) In operation step S5, circle 10 and circle 1
5 is determined. Next, the operation step S3 is performed again, the center coordinates of the circles 11 and 16 are obtained, and the operation steps S4 to S5 are performed.
S5 is repeated, and circles 12, 13,..., Circles 17, 18,.
【００２０】６）動作ステップＳ６では、リードフレー
ム先端数が設定値と一致しているか否かをチェックし、
一致していれば動作ステップＳ７の処理を行うが、一致
していない場合には、動作ステップＳ２に戻って設定値
より大きいか否かのチェックを行い、大きい場合には円
１０〜１４、円１５〜１９の直径を大きく修正し、小さ
い場合には直径を小さく修正して再び動作ステップＳ３
の処理を行う。6) In operation S6, it is checked whether or not the number of leading ends of the lead frame matches the set value.
If they match, the process of operation step S7 is performed. If they do not match, the process returns to operation step S2 to check whether the value is larger than the set value. The diameter of 15 to 19 is corrected to be large, and if it is small, the diameter is corrected to be small, and the operation step S3 is performed again.
Is performed.
【００２１】７）動作ステップＳ７では、リードフレー
ム先端側面ライン４と接線５の間をリードフレーム先端
部２０とし、接線５と接線６の間をリードフレーム先端
間隙部２６として、リードフレーム先端配置する。同様
に接線６と接線７の間及び接線８と接線（リードフレー
ム先端側面ライン）９の間をリードフレーム先端部２
１，２２とし、接線７と接線８の間をリードフレーム先
端間隙部２７とする。7) In the operation step S7, the leading end of the lead frame is disposed with the lead frame leading end portion 20 between the lead frame leading end side line 4 and the tangent line 5 and the lead frame leading end gap portion 26 between the tangent line 5 and the tangent line 6. . Similarly, a portion between the tangent line 6 and the tangent line 7 and a portion between the tangent line 8 and the tangent line (lead frame tip side surface line) 9 are connected to the lead frame tip portion 2.
1 and 22, and the space between the tangents 7 and 8 is the lead frame tip gap 27.
【００２２】なお本実施例では初めにリードフレーム先
端側面ライン４を設定し、これから出発して共通接線５
〜９を順次に求めていったが、他の共通接線等から出発
するようにしてもよい。例えば初めに円１２、１７の位
置を定め共通接線６、７を求め、この後に共通接線４、
５、８、９を求めるようにしてもよい。In this embodiment, first, the lead frame tip side surface line 4 is set, and starting from this, the common tangent line 5
-9 are sequentially obtained, but it is also possible to start from another common tangent or the like. For example, first, the positions of the circles 12 and 17 are determined, and the common tangents 6 and 7 are obtained.
5, 8, and 9 may be obtained.
【００２３】[0023]
【発明の効果】本発明のリードフレーム先端配置設計方
法は、キャビティーラインとオフセットラインの上に中
心を有するそれぞれに同一半径の円を配置し、これらの
円の共通接線でリードフレーム先端部の配置を定めるこ
とにより、リードフレーム先端幅とリードフレーム先端
間隔とを一定にできるので、チップとリードフレームを
ワイヤーボンディングするときの安定性を確保できると
いう効果がある。According to the lead frame tip arrangement design method of the present invention, circles having the same radius are respectively arranged on the cavity line and the offset line, each having a center on the cavity line and the offset line. By determining the disposition, the leading end width of the lead frame and the lead frame leading end interval can be made constant, so that there is an effect that the stability at the time of wire bonding the chip and the lead frame can be secured.
【図１】本発明の一実施例を示すフローチャートであ
る。FIG. 1 is a flowchart showing one embodiment of the present invention.
【図２】図１に示す実施例を用いて作成したリードフレ
ームの先端配置を示す図である。FIG. 2 is a diagram showing a tip arrangement of a lead frame created using the embodiment shown in FIG. 1;
【図３】従来のリードフレーム先端配置設計方法を示す
フローチャートである。FIG. 3 is a flowchart showing a conventional lead frame tip arrangement design method.
【図４】図３に示す従来の方法を用いて作成したリード
フレームの先端配置を示す図である。FIG. 4 is a diagram showing a tip arrangement of a lead frame created by using the conventional method shown in FIG. 3;
１ チップ外形 ２ キャビティーライン ３ オフセットライン ４、９ 側面ライン ５〜８ 共通接線 １０〜１４ 円 １５〜１９ 円 ２０〜２２、６０〜６２ リードフレーム先端部 ２６、２７、６３、６４ リードフレーム間隙部 1 Chip outline 2 Cavity line 3 Offset line 4, 9 Side line 5-8 Common tangent 10-14 yen 15-19 yen 20-22, 60-62 Lead frame tip 26, 27, 63, 64 Lead frame gap
Claims (2)
ィングのためのオフセット量を示すキャビティーライン
を設定し、このキャビティーラインより前記チップ外形
からさらに離してオフセットラインを設定し、予め定め
た大きさの複数の第１の円の中心が前記キャビティーラ
イン上に位置し、予め定めた大きさの前記第１の円と同
数の第２の円の中心が前記オフセットライン上に位置
し、隣り合う２個の前記第１の円及びこれら第１の円に
対応して隣り合う２個の前記第２の円が共通に接する中
間共通接線を有するように前記複数の第１の円及び前記
複数の第２の円を配置し、前記中間共通接線または両側
部の前記第１の円及び前記第２の円に共通に接する側面
共通接線に挟まれた部分をリードフレーム先端部または
リードフレーム先端部の間とすることを特徴とするリー
ドフレーム先端配置設計方法。1. A cavity line indicating an offset amount for bonding a lead frame to a chip outline is set, and an offset line is set further away from the chip outline from the cavity line to a predetermined size. Of the plurality of first circles are located on the cavity line, and the centers of the same number of second circles as the first circle having a predetermined size are located on the offset line and are adjacent to each other. The plurality of first circles and the plurality of the plurality of first circles and an intermediate common tangent line where two adjacent second circles corresponding to the first circles have a common tangent line in common. A second circle is arranged, and a portion sandwiched between the intermediate common tangent or a side common tangent tangent to the first circle and the second circle on both sides is defined as a lead frame tip or a lead frame tip. A lead frame tip arrangement design method, wherein
ィングのためのオフセット量を示すキャビティーライン
を設定し、このキャビティーラインより前記チップ外形
からさらに離してオフセットラインを設定し、リードフ
レーム先端部の一側辺となる一の共通接線を設定し、中
心が前記キャビティーライン上にあり予め定めた大きさ
の第１の円及び中心が前記オフセットライン上にあり予
め定めた大きさの第２の円が前記一の共通接線に共通に
接するように配置し、当該第１の円及び第２の円に共通
に接する他の共通接線に共通に接する他の第１の円及び
第２の円を配置し、さらに当該他の第１の円及び第２の
円に共通に接するさらに他の共通接線を求めるという操
作を繰り返し、この操作で求めた複数の共通接線で区切
られた領域を交互にリードフレーム先端部とし、予め定
めた範囲内に予め定めた数のリードフレーム先端部が配
置されるように前記第１の円及び第２の円の大きさを修
正していくことを特徴とするリードフレーム先端配置設
計方法。2. A cavity line indicating an offset amount for bonding a lead frame to a chip outline is set, and an offset line is set further away from the chip outline from the cavity line, and a lead line tip end portion is set. One common tangent which is one side is set, a first circle having a center on the cavity line and a predetermined size, and a second circle having a center on the offset line and a predetermined size. The circles are arranged so as to be in common contact with the one common tangent line, and the other first and second circles that are in common contact with other common tangent lines that are in common contact with the first and second circles are The operation of arranging and further obtaining another common tangent line that is in common contact with the other first and second circles is repeated, and the areas divided by the plurality of common tangent lines obtained by this operation are alternately formed. The size of the first circle and the second circle is modified such that a predetermined number of lead frame distal ends are disposed within a predetermined range as a lead frame distal end. Lead frame tip placement design method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5193793A JP2595873B2 (en) | 1993-08-05 | 1993-08-05 | Lead frame tip placement design method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5193793A JP2595873B2 (en) | 1993-08-05 | 1993-08-05 | Lead frame tip placement design method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0749894A JPH0749894A (en) | 1995-02-21 |
| JP2595873B2 true JP2595873B2 (en) | 1997-04-02 |
Family
ID=16313880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5193793A Expired - Fee Related JP2595873B2 (en) | 1993-08-05 | 1993-08-05 | Lead frame tip placement design method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2595873B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2967752B2 (en) * | 1997-03-12 | 1999-10-25 | 三菱電機株式会社 | Lead frame tip placement design method |
| JPH1166126A (en) * | 1997-08-20 | 1999-03-09 | Mitsubishi Electric Corp | Lead frame tip arrangement designing method |
-
1993
- 1993-08-05 JP JP5193793A patent/JP2595873B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0749894A (en) | 1995-02-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4785673A (en) | Strain-gauge sensor for measuring forces | |
| JPH09320936A (en) | Method for arrangement of alignment mark | |
| JP2595873B2 (en) | Lead frame tip placement design method | |
| US6005294A (en) | Method of arranging alignment marks | |
| JPS6328523A (en) | Manufacture of honeycomb die | |
| JP3182079B2 (en) | Wiring structure of capacitive element of semiconductor device | |
| JP2765476B2 (en) | Lead frame design method | |
| JP2967752B2 (en) | Lead frame tip placement design method | |
| JP2000124376A (en) | Manufacture of lead frame | |
| US11097373B2 (en) | Spring package for a vibration welding device and respective vibration welding device | |
| JP2005150456A (en) | Semiconductor device and its manufacturing method | |
| JPH01231411A (en) | Manufacture of surface acoustic wave resonance filter | |
| JP3150020B2 (en) | Semiconductor integrated circuit | |
| JP3570858B2 (en) | Lead frame tip placement design method | |
| JPH0320930B2 (en) | ||
| JPS6154270B2 (en) | ||
| JPS58107618A (en) | Chip condenser | |
| JPH04180668A (en) | Lead frame for semiconductor device | |
| JPH0219921Y2 (en) | ||
| JPH01251601A (en) | Thin-film resistance element | |
| JPH05109957A (en) | Manufacture of resin-sealed-type semiconductor device and lead frame | |
| JPH0221126B2 (en) | ||
| JPH02140934A (en) | Semiconductor device | |
| JP2000018334A (en) | Joining structure of belt | |
| JPH0911221A (en) | Ceramic substrate fitted with break grooves |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19961105 |
|
| LAPS | Cancellation because of no payment of annual fees |