JP2591427B2 - Magnetic disk drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic disk drive, and more particularly to a magnetic disk drive suitable for inspecting a defect position on a storage medium surface.

[0002]

2. Description of the Related Art Conventionally, in a magnetic disk drive, when inspecting a defect position on a surface of a storage medium, all defect positions and the length of the defect for each track are detected and recorded in a memory.

That is, as shown in FIG. 3 as an example, on a certain track, a first defect A between j1 and j2 from a reference position, a second defect B, j5 and j6 between j3 and j4. Between the third defect C, j7 and j8, the fourth defect D, j9
If a fifth defect E is intermittently present between and j10, the memory stores j1, j2, j as shown in FIG.
Data of 3, j4, j5, j6, j7, j8, j9, and j10 are recorded.

[0004] When the inspection is completed, the upper circuit reads the contents of the memory, and treats those having a similar defect position as the same defect to obtain final defect position information (defect map) on the storage medium surface.

[0005]

However, in the above-mentioned conventional example, a large-capacity memory is required because positional information on all defects is recorded as shown in FIG. However, there is an inconvenience that the load on the high-order circuit is large because the general defect position information creation processing is performed by the high-order circuit.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the disadvantages of the prior art, and in particular, to reduce the memory capacity required for storing defect position information on the surface of a storage medium and to reduce the load on a host circuit. An object of the present invention is to provide a magnetic disk drive.

[0007]

Therefore, according to the present invention, there is provided a counter which counts up in synchronization with a reference clock signal and outputs a position data signal from a reference position of a storage medium, and checks the presence or absence of a defect in the storage medium. A comparison circuit, a memory for storing output values of a counter at a first position and a last position of a defect detected by the comparison circuit, and an address generator for outputting an address signal for storing defect position information in the memory to the memory Means for controlling the address generating means based on the defect information from the comparison circuit, and when the interval between the defects is shorter than a preset value, the control means regards the address as one continuous defect. It has a configuration. This aims to achieve the above-mentioned object.

[0008]

The counter counts up the count value in synchronization with the reference clock signal, and outputs the count value to the memory.

[0009] The control means is provided for every one rotation of the storage medium.
Upon receiving the index signal output twice, the count value of the counter is reset.

When the comparison circuit detects a defect, it turns on a defect detection signal to the control means.

The control means outputs a write signal to the memory when the defect detection signal from the comparison circuit is turned on, and stores the count value of the counter at that time at an address position designated by the address signal from the address generation means. Let it.

The control means outputs a write signal to the memory when the defect detection signal from the comparison circuit is turned off, and stores the count value of the counter at that time in an address position designated by the address signal from the address generation means. And a reset signal is output to the address generation means.

The address generating means starts counting up the count value in synchronization with the reference clock signal upon receiving the reset signal, and when the count value reaches a preset value, increments the address signal to the memory. .

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

In the embodiment shown in FIG. 1, the first counter 7 counts up in synchronization with a reference clock signal a and outputs a position data signal j from a reference position of a storage medium.
A first comparing circuit 5 for checking the presence or absence of a defect in a storage medium, a memory 8 for storing defect position information, and an address generating means 1 for outputting an address signal s for storing defect position information to the memory 8; When the position data signal j from the first counter 7 reaches a preset value, a start signal generating means 3 for outputting a defect inspection start signal and the position data signal j from the first counter 7 are set in advance. The first comparison circuit 5 is controlled by a stop signal generation unit 4 that outputs a defect inspection stop signal when the value becomes a predetermined value, and a defect inspection start signal from the start signal generation unit 3 and a defect inspection stop signal from the stop signal generation unit 4. Address generating means 1 based on the defect information from the first comparing circuit 5.
Control means 2 which determines that the distance between defects is shorter than a preset value, and regards the control means 2 as one continuous defect, and enables the control means 2 to be activated by a start signal b from a higher-level circuit (not shown). And a signal generation circuit 6.

Here, the address generation means 1 starts counting up in synchronization with the reference clock signal a in accordance with an instruction from the control means 2 and outputs a count end signal u to the control means 2 when the count value reaches a preset value. A second counter 1a, and an address generation circuit 1b for incrementing an address in the memory 8 for storing defect position information according to an instruction from the control means 2.

The start signal generating means 3 includes a first register 3a for outputting a data signal x indicating a preset defect inspection start position, a data signal j from the first counter 7 and a first register 3a. And a second comparison circuit 3b that outputs a coincidence signal v to the control means 2 when the data signal x from the first comparator 3 matches.

The stop signal generating means 4 includes a second register 4a for outputting a data signal y indicating a preset defect inspection end position, a data signal j from the first counter 7 and a second register 4a. And a third comparison circuit 4b that outputs a coincidence signal w to the control means 2 when the data signal y from the second comparator 4 matches.

The first counter 7 indicates that the storage medium is 1
It has a sufficient storage capacity (number of bits) for counting the number of reference clocks during rotation, and outputs the count value as a data signal j in byte units.

The memory 8 includes, as shown in FIG.
One set of an address for storing position data when a defect is detected (defect start position storage address) and an address for storing the last position data of a continuous defect after the defect is detected (defect end position storage address) Is set to 1 address, and [M] from address 0 to address M
+1] data capacity.

The control means 2 can be easily realized by using a sequencer.

Next, the operation of this embodiment will be described.
Here, as shown in FIG. 3 as an example, the value of the data signal j is between the first defect A and the first defect A, j3 to j4 between j1 and j2.
A second defect B during j, a third defect C between j5 and j6,
It is assumed that a fourth defect D exists between j7 and j8, and a fifth defect E exists between j9 and j10. However, the distance between the second defect B and the third defect C, and the distance between the fourth defect D and the fifth defect D
The distance from the defect E is set to a value (N
Byte).

(1). The enable signal generation circuit 6 activates the enable signal e to the control means 2 when the start signal b from the upper circuit becomes active.

(2). When the enable signal e from the enable signal generation circuit 6 becomes active, the control means 2 outputs an index signal d which is output once every rotation of the storage medium as a reference signal for positioning the storage medium.
Of the address generation circuit 1b
The reset signal q to the inactive state.

(3). When the reset signal q from the control means 2 becomes inactive, the address generation circuit 1b
The value of the memory address is reset to 0 and output to the memory 8 as an address signal s. Further, the value of the memory address is incremented based on the increment signal p from the control means 2 and output to the memory 8 as the address signal s.

(4). On the other hand, when detecting the index signal d, the control means 2 makes the preload signal h to the first counter 7 inactive.

(5). The first counter 7 includes the control unit 2
When the preload signal h from the CPU becomes inactive, the counting of the reference clock signal a is started. Then, the count value is output to the memory 8, the second comparison circuit 3b, and the third comparison circuit 4b as the data signal j.

(6). The second comparison circuit 3b compares the value of the data signal x from the first register 3a with the value of the data signal j from the first counter 7 in synchronization with the reference clock signal a. Activate the match signal v.

(7). The control means 2 includes a second comparison circuit 3
When the coincidence signal v from b becomes active, the compare enable signal g to the first comparison circuit 5 is activated.

(8). The first comparison circuit 5 includes a control unit 2
While the compare enable signal g is active, the read data signal c from an external circuit (not shown) is compared, and when a mismatch (first defect A) is detected, the compare error signal f to the control means 2 is activated. To

(9). The control means 2 includes a first comparison circuit 5
When the compare error signal f changes from inactive to active, a write signal k is output to the memory 8.

Then, the preload signal t to the second counter 1a is activated to reset the second counter 1a.

(10). When receiving the write signal k from the control means 2, the memory 8 stores the value of the data signal j in the defect start position storage address of the address [m '] indicated by the address signal s from the address generation circuit 1b as shown in FIG. Write j1.

(11). When the compare error signal f from the first comparison circuit 5 changes from active to inactive, the control means 2 outputs a write signal 1 to the memory 8.

At the same time, the control means 2 controls the second counter 1a
The preload signal t is deactivated, and the second counter 1a starts counting.

(12). When the memory 8 receives the write signal 1 from the control means 2, the memory 8 stores the value of the data signal j in the defect end position storage address of the address [m '] indicated by the address signal s from the address generation circuit 1b as shown in FIG. Write j2.

(13). Next, the first comparison circuit 5
When the defect B is detected, the compare error signal f to the control means 2 is activated during that time.

(14). The control means 2 does not receive the count end signal u from the second counter 1a even if the compare error signal f from the first comparison circuit 5 changes from active to inactive.
, The preload signal t to the second counter 1a is activated to reset the second counter 1a.

(15). When the compare error signal f from the first comparison circuit 5 changes from active to inactive, the control means 2 outputs a write signal 1 to the memory 8.

At the same time, the control means 2 controls the second counter 1a
The preload signal t is deactivated, and the second counter 1a starts counting.

(16). When the memory 8 receives the write signal 1 from the control means 2, the memory 8 stores the value of the data signal j in the defect end position storage address of the address [m '] indicated by the address signal s from the address generation circuit 1b as shown in FIG. Overwrite j4.

(17). When the count value reaches a preset value (a value corresponding to a data length of N bytes), the second counter 1a outputs a count end signal u to the control means 2.

(18). When receiving the count end signal u from the second counter 1a, the control means 2 outputs an increment signal p to the address generation circuit 1b.

(19). When receiving the increment signal p from the control means 2, the address generation circuit 1b increments the value of the address signal s.

Here, if the address signal s exceeds the maximum address value in the memory 8, ie, M, an overflow signal r is output to the control means 2.

(20). Next, the first comparison circuit 5
When the defect C is detected, the compare error signal f to the control means 2 is activated.

(21). When the compare error signal f from the first comparison circuit 5 changes from active to inactive, the control means 2 receives the count end signal u from the second counter 1a. And the preload signal t to the second counter 1a is activated to activate the second counter 1a.
Reset a.

(22). When the memory 8 receives the write signal k from the control unit 2, as shown in FIG. 5, the memory 8 stores the data signal j at the defect start position storage address of the address [m '+ 1] indicated by the address signal s from the address generation circuit 1b. Write the value j5.

(23). When the compare error signal f from the first comparison circuit 5 changes from active to inactive, the control means 2 outputs a write signal 1 to the memory 8.

At the same time, the control means 2 controls the second counter 1a
The preload signal t is deactivated, and the second counter 1a starts counting.

(24). When the memory 8 receives the write signal 1 from the control means 2, as shown in FIG. 5, the memory 8 stores the data signal j at the defect end position storage address of the address [m '+ 1] indicated by the address signal s from the address generation circuit 1b. Write the value j6.

Thereafter, the same processing is performed, and the third defect C and the fourth defect D are regarded as one defect as shown in FIG.

As described above, by considering a plurality of defects intermittently within N bytes as one continuous defect, in the present invention, the memory capacity for storing defect position information can be reduced as compared with the prior art. Can be.

Conventionally, the work of creating the final defect position information is performed by reading data from the memory every time the higher-level circuit detects a compare error signal. Therefore, the load on the host circuit can be greatly reduced.

(25). The third comparison circuit 4b always compares the value of the data signal y from the second register 4a with the value of the data signal j from the first counter 7, and outputs a match signal w to the control means 2 when they match.

The control means 2 controls the third comparison circuit 4
When the match signal w is received from b, the compare enable signal g to the first comparison circuit 5 is made inactive, and the comparison operation in the first comparison circuit 5 is stopped.

That is, by controlling the second comparison circuit 3b, a defect inspection can be started at an arbitrary position from the index signal d. By controlling the third comparison circuit 4b, the comparison can be performed at an arbitrary position. Can be stopped.

(26). Further, when receiving the overflow signal r from the address generation circuit 1b, the control means 2 outputs an overflow signal z.

(26). Further, when receiving the coincidence signal w from the third comparison circuit 4b, detecting the next index signal d, and outputting the overflow signal z, the control means 2 sends the signal to the enable signal generation circuit 6. Is activated.

When the reset signal i from the control means 2 becomes active, the enable signal generation circuit 6
The enable signal e to the control means 2 is made inactive to stop the operation.

Here, the upper circuit obtains defect position information from the memory 8 after confirming that the enable signal e from the enable signal generation circuit 6 becomes inactive.

[0062]

Since the present invention is constructed and functions as described above, according to this, a plurality of defects intermittently existing at short distances on the surface of a storage medium can be treated as one defect at the time of defect inspection. Therefore, it is possible to provide an unprecedented excellent magnetic disk device in which the memory capacity required for storing defect position information can be reduced, and the load on the upper circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a memory map of a memory in the embodiment of FIG. 1;

FIG. 3 is an explanatory diagram illustrating an example of a defect that has occurred in one track of a storage medium.

FIG. 4 is an explanatory diagram showing defect positions when the storage medium of FIG. 3 is inspected in the embodiment of FIG. 1;

FIG. 5 is an explanatory diagram showing a storage state of defect position information in a memory when the storage medium of FIG. 3 is inspected in the embodiment of FIG. 1;

FIG. 6 is an explanatory diagram showing a storage state of defect position information in a memory when the storage medium of FIG. 3 is inspected in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Address generation means 1a 2nd counter 1b Address generation circuit 2 Control means (sequencer) 3 Start signal generation means 3a 1st register 3b 2nd comparison circuit 4 Stop signal generation means 4a 2nd register 4b 3rd comparison Circuit 5 First comparison circuit 6 Enable signal generation circuit 7 First counter 8 Memory

Claims (4)

(57) [Claims] 1. A counter for counting up in synchronization with a clock signal and outputting a position data signal from a reference position of a storage medium, a comparison circuit for checking the presence or absence of a defect in the storage medium, and a detection circuit for detecting the defect. A memory for storing an output value of the counter at a first position and a last position of a defect; address generation means for outputting an address signal for storing defect position information to the memory to the memory; A magnetic disk provided with control means for controlling the address generating means based on the defect information and, when the interval between the defects is shorter than a preset value, assuming that the defect is one continuous defect; apparatus. 2. The counter according to claim 1, wherein the address generation unit starts counting up according to an instruction from the control unit, and outputs a count end signal to the control unit when the count value reaches a preset value. 2. The magnetic disk drive according to claim 1, further comprising: an address generation circuit for updating an address signal output to said memory in accordance with the instruction. 3. A counter that counts up in synchronization with a clock signal and outputs a position data signal from a reference position of a storage medium, a comparison circuit that checks for the presence or absence of a defect in the storage medium, and the comparison circuit detects A memory for storing output values of the counter at a first position and a last position of a defect, address generation means for outputting an address signal for storing defect position information in the memory to the memory, and a position from the counter Start signal generating means for outputting a defect inspection start signal when the data signal has a preset value; and starting the comparison circuit by a defect inspection start signal from the start signal generation means, and outputting defect information from the comparison circuit. Controlling the address generation means on the basis of the distance between the defects to be smaller than a preset value. A magnetic disk drive provided with a control unit that regards the defect as one continuous defect when the defect is short. 4. A counter that counts up in synchronization with a clock signal and outputs a position data signal from a reference position of a storage medium, a comparison circuit that checks for the presence or absence of a defect in the storage medium, and the comparison circuit detects A memory for storing output values of the counter at a first position and a last position of a defect, address generation means for outputting an address signal for storing defect position information in the memory to the memory, and a position from the counter A stop signal generating unit that outputs a defect inspection stop signal when the data signal reaches a preset value, and the address generating unit is controlled based on the defect information from the comparison circuit, and an interval between the defects is set in advance. If the value is shorter than the current value, it is regarded as one continuous defect, and the defect detection from the stop signal generating means is performed. Control means for stopping the comparison circuit in response to an inspection stop signal.