JP2590918B2 - Manufacturing method of amorphous semiconductor device - Google Patents

Manufacturing method of amorphous semiconductor device

Info

Publication number
JP2590918B2
JP2590918B2 JP62208433A JP20843387A JP2590918B2 JP 2590918 B2 JP2590918 B2 JP 2590918B2 JP 62208433 A JP62208433 A JP 62208433A JP 20843387 A JP20843387 A JP 20843387A JP 2590918 B2 JP2590918 B2 JP 2590918B2
Authority
JP
Japan
Prior art keywords
electrode
metal layer
amorphous semiconductor
processing
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62208433A
Other languages
Japanese (ja)
Other versions
JPS6451670A (en
Inventor
吉田  隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP62208433A priority Critical patent/JP2590918B2/en
Publication of JPS6451670A publication Critical patent/JPS6451670A/en
Application granted granted Critical
Publication of JP2590918B2 publication Critical patent/JP2590918B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

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  • Weting (AREA)
  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、絶縁基板上に第一電極を介して形成された
非晶質半導体層の上に金属層を被着し、その金属層を分
割して第二電極を形成する非晶質半導体装置の製造方法
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to depositing a metal layer on an amorphous semiconductor layer formed on an insulating substrate via a first electrode, and forming the metal layer on the amorphous semiconductor layer. The present invention relates to a method for manufacturing an amorphous semiconductor device in which a second electrode is divided and formed.

〔従来の技術〕[Conventional technology]

例えば、非晶質半導体を用いた太陽電池において、高
い出力電圧を得るためには、基板上に複数個の太陽電池
素子を作成し、それらを直列接続する。そのためには、
絶縁基板上に非晶質半導体層をはさんで積層される第一
電極層,第二電極層を分割する工程が必要となる。また
非晶質半導体層も分割されることがある。
For example, in a solar cell using an amorphous semiconductor, in order to obtain a high output voltage, a plurality of solar cell elements are formed on a substrate and connected in series. for that purpose,
A step of dividing the first electrode layer and the second electrode layer that are stacked on the insulating substrate with the amorphous semiconductor layer interposed therebetween is required. Further, the amorphous semiconductor layer may be divided.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

基板上に被着される第一電極層およびその上の非晶質
半導体層の分割には最近レーザスクライビング法が用い
られるようになったが、その上に通常金属によって形成
する第二電極層の分割は、既に積層された下の層への影
響を及ぼさないようにレーザ光出力を調整することが難
しいので、レーザスクライビング法は適用されない。そ
こで従来のフォトリソグラフィ技術を用いる。すなわ
ち、金属層上にレジストを塗布し、これを露光し、現像
し、エッチングしたのちレジスト膜を剥離する工程を経
て分割する。しかしこの方法は五つの工程を経るため、
工数が多く製造コストが高くつくという欠点があった。
Recently, a laser scribing method has been used to divide the first electrode layer deposited on the substrate and the amorphous semiconductor layer thereon, but a second electrode layer usually formed of a metal thereon has been used. The laser scribing method is not applied to the division because it is difficult to adjust the laser light output so as not to affect the lower layer already laminated. Therefore, a conventional photolithography technique is used. That is, a resist is applied on the metal layer, the resist is exposed, developed, etched, and then divided through a step of removing the resist film. However, this method goes through five steps,
There is a disadvantage that the number of steps is large and the production cost is high.

本発明の目的は、上述の欠点を除いて、金属層を分割
して第二電極にする際の工程数をへらして、製造コスト
を低くした非晶質半導体装置の製造方法に関する。
An object of the present invention is to provide a method for manufacturing an amorphous semiconductor device in which the manufacturing cost is reduced by reducing the number of steps for dividing a metal layer into a second electrode, excluding the above-mentioned disadvantages.

〔問題点を解決するための手段〕[Means for solving the problem]

上記の目的を達成するために、本発明によれば、絶縁
基板上に第一電極を介して形成された非晶質半導体層の
上に金属層を被着し、該金属層を電界加工法により分割
して第二電極を形成する非晶質半導体装置の製造方法に
おいて、金属層を分割する加工電極を、加工電極用基板
上に、加工対象である金属層の所望分割形状と同一形状
に形成し、この加工電極を金属層と対向させて、加工電
極の形状にしたがって金属層を分割して第二電極を形成
することとする。
To achieve the above object, according to the present invention, a metal layer is deposited on an amorphous semiconductor layer formed on an insulating substrate via a first electrode, and the metal layer is formed by an electric field processing method. In the method for manufacturing an amorphous semiconductor device in which the second electrode is formed by dividing the processed electrode, the processed electrode for dividing the metal layer is formed on the processed electrode substrate in the same shape as the desired divided shape of the metal layer to be processed. Then, the processed electrode is made to face the metal layer, and the metal layer is divided according to the shape of the processed electrode to form the second electrode.

〔作用〕[Action]

電界加工法を用いることにより、フォトリソグラフィ
法によるような多くの工程を必要とせず、コストダウン
が可能になる。
The use of the electric field processing method does not require many steps as in the case of the photolithography method, so that the cost can be reduced.

さらに、加工電極は加工対象である金属層の分割形状
と一致した形状を有しているので、金属層の一括加工が
可能となる。
Further, since the processed electrode has a shape corresponding to the divisional shape of the metal layer to be processed, the metal layer can be collectively processed.

〔実施例〕〔Example〕

第1図は、本発明の参考例を示す断面図で、ガラス基
板1上に、透明で導電性を持つ第一電極2を形成し、そ
の上部にp−i−n接合を持つ非晶質半導体層3を設
け、その上部に蒸着またはスパッタリングで厚さ1μm
に形成した半導体素子の金属電極層を分割するために、
分割部と対向する位置に絶縁物6で囲まれた加工電極5
を設ける。加工電極5と金属層4との間隔は0.05〜1.0m
m、望ましくは0.1〜0.8mm、最も望ましくは0.2〜0.6mm
にすることが好ましい。この加工電極5と金属層4の間
には、ノズル7より電解液8が供給される。電解液の種
類は金属電極を形成する金属の種類により異なるが、た
とえばAlの場合にはNaOH,NaCl,酢酸の水溶液などが好ま
しい。金属層4と加工電極5の間に金属層を正とする電
圧が印加することにより、金属電極は電流量に比例した
速度で溶解反応を起こす。金属層4の厚さが1μm程度
と薄いため、分割部の金属層はきわめて簡単に除去され
る。また、分割部の間隔が50μm以上あれば、加工電極
5の形状をその間隔を制御することにより、金属層4の
除去幅を自由に選ぶことが出来る。絶縁物6は、反応対
象部分以外は電流が流れることを防止して必要な溶解反
応の起こるのを阻止するのに役立つ。
FIG. 1 is a cross-sectional view showing a reference example of the present invention, in which a transparent and conductive first electrode 2 is formed on a glass substrate 1 and an amorphous material having a pin junction is formed thereon. A semiconductor layer 3 is provided and a thickness of 1 μm is formed on the semiconductor layer 3 by vapor deposition or sputtering.
In order to divide the metal electrode layer of the semiconductor element formed in
A processing electrode 5 surrounded by an insulator 6 at a position facing the division portion
Is provided. The distance between the processing electrode 5 and the metal layer 4 is 0.05 to 1.0 m
m, preferably 0.1-0.8mm, most preferably 0.2-0.6mm
Is preferable. An electrolytic solution 8 is supplied between the processing electrode 5 and the metal layer 4 from a nozzle 7. The type of electrolyte varies depending on the type of metal forming the metal electrode. For example, in the case of Al, an aqueous solution of NaOH, NaCl, acetic acid or the like is preferable. When a positive voltage is applied between the metal layer 4 and the processing electrode 5, the metal electrode causes a dissolution reaction at a rate proportional to the amount of current. Since the thickness of the metal layer 4 is as thin as about 1 μm, the metal layer in the divided portion is very easily removed. If the interval between the divided portions is 50 μm or more, the removal width of the metal layer 4 can be freely selected by controlling the interval of the shape of the processing electrode 5. The insulator 6 serves to prevent a current from flowing except for a reaction target portion and to prevent a necessary dissolution reaction from occurring.

第2図は本発明の別の参考例を示すもので、第1図と
共通の部分には同一の符号が付され、第1図の実施例と
異なる点は、加工電極5が複数個存在することにより加
工能率を上げることが可能となる点である。
FIG. 2 shows another embodiment of the present invention. The same reference numerals are given to the same parts as in FIG. 1, and the difference from the embodiment of FIG. This makes it possible to increase the processing efficiency.

第3図は本発明の実施例であり金属層を短冊状に分割
するのに用いる加工電極の一例を示すもので、(a)は
平面図,(b)はその断面図,(c)は(b)のA部拡
大図である。加工電極用基板である絶縁基板11上にフォ
トエッチングにより形成された金属製の加工電極5が、
加工対象に求められる形状を持っており、図示しない端
子により電圧印加可能である。この加工電極基板11を第
4図に示す電解加工装置内に組み込む。すなわち、加工
台12上に、非晶質半導体素子の基板1を支持し、その金
属電極層4に加工電極基板11を加工電極5を下に向けて
対向させる。基板11には電解液の供給口13が形成され、
その上部に電解液8をためる液だめ14が設けられてい
る。電解液8を供給口13を通って加工面に供給し、電源
9によって加工電極5には負電圧、金属層4には正電圧
を印加することにより、加工電極のパターンにしたがっ
て、金属層が溶解し分割される。電解液8は、ポンプ16
により槽15から液溜め14に供給され、液受け17を経て槽
15に戻される。
FIG. 3 shows an embodiment of the present invention and shows an example of a processing electrode used to divide a metal layer into strips. FIG. 3 (a) is a plan view, FIG. 3 (b) is a cross-sectional view thereof, and FIG. It is the A section enlarged view of (b). A metal processing electrode 5 formed by photo-etching on an insulating substrate 11, which is a processing electrode substrate,
It has a shape required for a processing object, and a voltage can be applied by a terminal (not shown). This processed electrode substrate 11 is incorporated in the electrolytic processing apparatus shown in FIG. That is, the substrate 1 of the amorphous semiconductor element is supported on the processing table 12, and the processing electrode substrate 11 is opposed to the metal electrode layer 4 with the processing electrode 5 facing downward. An electrolyte supply port 13 is formed in the substrate 11,
A liquid reservoir 14 for accumulating the electrolytic solution 8 is provided on the upper part thereof. The electrolytic solution 8 is supplied to the processing surface through the supply port 13, and a negative voltage is applied to the processing electrode 5 and a positive voltage is applied to the metal layer 4 by the power supply 9, whereby the metal layer is formed according to the pattern of the processing electrode. Dissolve and split. Electrolyte 8 is pump 16
Is supplied from the tank 15 to the liquid reservoir 14,
Returned to 15.

第5図(a),(b)は、加工電極基板11の別の例を
示すもので、第5図の例と異なる点は、加工電極5と金
属槽4との間隔を保つためのストッパ18が基板11に装着
されている点である。
FIGS. 5 (a) and 5 (b) show another example of the processing electrode substrate 11, which is different from the example of FIG. 5 in that a stopper for keeping an interval between the processing electrode 5 and the metal bath 4 is provided. Reference numeral 18 is a point attached to the substrate 11.

第6図は本発明の異なる実施例を示し、加工電極5を
用いて溶解分離する前に、金属電極層4の一部を針19に
より加工して除去する。
FIG. 6 shows another embodiment of the present invention, in which a part of the metal electrode layer 4 is removed by processing with a needle 19 before dissolving and separating using the processing electrode 5.

〔発明の効果〕〔The invention's effect〕

本発明によれば、上記の方法を採用した結果、金属層
を所望の分割形状に一括して加工でき、また、フォトリ
ソグラフィ技術を用いる場合のように多くの工程を必要
とせず、レーザスクライビング法によるように非晶質半
導体層などの下層への影響もなく、高額の設備も必要と
しないので、非晶質半導体装置のコストダウンに極めて
有効である。
According to the present invention, as a result of adopting the above method, the metal layer can be processed into a desired divided shape at a time, and the laser scribing method does not require many steps as in the case of using the photolithography technique. As described above, there is no influence on lower layers such as an amorphous semiconductor layer, and no expensive equipment is required, which is extremely effective in reducing the cost of an amorphous semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の参考例を示す断面図、第2図は別の参
考例を示す断面図、第3図(a),(b),(c)は本
発明の実施例に用いる加工電極基板の一例で(a)が平
面図,(b)が断面図,(c)は(b)のA部拡大図、
第4図は第3図の加工電極基板を用いた実施例のための
電解加工装置の断面図、第5図(a),(b)は加工電
極の基板の別の例を示し、(a)が平面図,(b)が断
面図、第6図は本発明のさらに別の実施例を示す断面図
である。 1:ガラス基板、2:第一電極、3:非晶質半導体層、4:金属
電極層、5:加工電極、8:電解液。
FIG. 1 is a cross-sectional view showing a reference example of the present invention, FIG. 2 is a cross-sectional view showing another reference example, and FIGS. 3 (a), (b) and (c) are processes used in the embodiment of the present invention. (A) is a plan view, (b) is a cross-sectional view, (c) is an enlarged view of a portion A of (b),
FIG. 4 is a sectional view of an electrolytic processing apparatus for an embodiment using the processing electrode substrate of FIG. 3, and FIGS. 5 (a) and 5 (b) show another example of a substrate of the processing electrode. ) Is a plan view, (b) is a sectional view, and FIG. 6 is a sectional view showing still another embodiment of the present invention. 1: glass substrate, 2: first electrode, 3: amorphous semiconductor layer, 4: metal electrode layer, 5: processed electrode, 8: electrolytic solution.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】絶縁基板上に第一電極を介して形成された
非晶質半導体層の上に金属層を被着し、該金属層を電界
加工法により分割して第二電極を形成する非晶質半導体
装置の製造方法において、 金属層を分割する加工電極を、加工電極用基板上に、加
工対象である金属層の所望分割形状と同一形状に形成
し、この加工電極を金属層と対向させて、加工電極の形
状にしたがって金属層を分割して第二電極を形成するこ
とを特徴とする非晶質半導体装置の製造方法。
1. A metal layer is deposited on an amorphous semiconductor layer formed on an insulating substrate via a first electrode, and the metal layer is divided by an electric field processing method to form a second electrode. In the method for manufacturing an amorphous semiconductor device, a processing electrode for dividing a metal layer is formed on a processing electrode substrate in the same shape as a desired division shape of a metal layer to be processed. A method for manufacturing an amorphous semiconductor device, wherein a second electrode is formed by dividing a metal layer in accordance with the shape of a processing electrode.
JP62208433A 1987-08-22 1987-08-22 Manufacturing method of amorphous semiconductor device Expired - Fee Related JP2590918B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62208433A JP2590918B2 (en) 1987-08-22 1987-08-22 Manufacturing method of amorphous semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62208433A JP2590918B2 (en) 1987-08-22 1987-08-22 Manufacturing method of amorphous semiconductor device

Publications (2)

Publication Number Publication Date
JPS6451670A JPS6451670A (en) 1989-02-27
JP2590918B2 true JP2590918B2 (en) 1997-03-19

Family

ID=16556130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62208433A Expired - Fee Related JP2590918B2 (en) 1987-08-22 1987-08-22 Manufacturing method of amorphous semiconductor device

Country Status (1)

Country Link
JP (1) JP2590918B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5098850A (en) * 1989-06-16 1992-03-24 Canon Kabushiki Kaisha Process for producing substrate for selective crystal growth, selective crystal growth process and process for producing solar battery by use of them
JP4660354B2 (en) * 2005-01-18 2011-03-30 新光電気工業株式会社 Method and apparatus for processing conductive thin film

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4599154A (en) * 1985-03-15 1986-07-08 Atlantic Richfield Company Electrically enhanced liquid jet processing

Also Published As

Publication number Publication date
JPS6451670A (en) 1989-02-27

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