JP2587537B2 - Delay circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a delay circuit suitable for being applied to a video tape recorder (hereinafter referred to as VTR) for recording and reproducing television signals and the like.

<Summary of the Invention> The present invention is provided with a delay time adjusting means, a storage means, a counting means, a comparing means, and a controlling means, and is designated by an external input even beyond the delay time adjusting range. The purpose is to realize time.

<Prior Art> A conventional technique will be described based on a delay circuit described in JP-A-1-179263.

 FIG. 4 shows the configuration of the prior art.

In FIG. 1, reference numeral 1 denotes a delay circuit. The delay circuit 1 includes a reference time delay circuit 2, a delay time adjustment circuit 3, a register 4 serving as storage means, a counter circuit 5, a comparison circuit 6, and a system control circuit 7. I have.

The reference time delay circuit 2 includes a discharge circuit 11, a charge recognition circuit 12,
It consists of a variable resistor R0 and a capacitor C0.

The delay time adjustment circuit 3 includes an AND gate 31, a count register 32, an addition register 33, and an adder.

The counter circuit 5 includes an AND gate 51 and a count register.
52.

The case where the tracking adjustment of the VTR is performed using the delay circuit 1 having such a configuration will be described in detail below with reference to the timing chart of FIG.

Before the start signal a shown in FIG. 5A is input to the system control circuit 7 (when in the low state), the reference time delay circuit 2
In, a preset delay time t1 (hereinafter referred to as a reference time) is measured.

In the discharge circuit 11, the mono-multi-reset signal m shown in FIG. 5B supplied from the system control circuit 7 is normally in the ON state (low level), and the transistor Tr1 operates. There is no state.

When measuring the reference time, first, the system control circuit 7 turns off the mono-multi reset signal, and controls the transistor Tr1 of the discharge circuit 11 to the cutoff state.

As a result, charges are stored in the capacitor C0 as shown in FIG. 5C.

At this time, a charge completion signal e (high-level signal) as shown in FIG. 5D is supplied to the AND gate 31 from the collector side of the transistor Tr2 provided in the charge recognition circuit 12.

A high-level signal is supplied to the AND gate 31 until the transistor Tr2 in the charge recognition circuit 12 is turned on (until charging is completed).

When the charging is completed, a low state signal e is supplied to the system control circuit 7 and the AND gate 31.

In this way, only after the transistor Tr1 is turned on and discharged, only until the charging of the capacitor C0 is completed,
And gate 31 is opened.

On the other hand, the AND gate 31 has a counter clock terminal K.
Supplies a clock signal k (shown in FIG. 5E) having a constant period.

The system control circuit 7 sets the register clear signal r (shown in FIG. 5F) to a low state simultaneously with the start of charging of the capacitor C0 (when the mono-multi reset signal m becomes a low state) to activate the count register 32. State.

As a result, in the count register 32, while the capacitor C0 is being charged, the clock signal k output from the AND gate 31 is output.
Count. Therefore, as shown in FIG. 5G, the reference time t1 corresponding to the count value T1 can be measured from the count value T1 of the register 32.

Next, data T2 to be adjusted based on the reference time t1 from the external input terminal 8, for example, the switches 8A and 8B (shown in FIG. 5H)
Is supplied to the system circuit 7.

This data T2 can be remotely controlled by a remote controller or the like, and acts as auxiliary data for tracking adjustment. The external data T2 is supplied to the addition register 33 as data corresponding to the adjustment time t2.

Next, the measured value T1 stored in the count register 32
And the data T2 of the addition register 33 are added by the adder 34, and the added data T0 (shown in FIG. 5I) is stored in the register 4 as storage means.

Thereafter, when the start signal a (high signal) is input to the system control circuit 7, the system control circuit 7 sends the register clear signal p as shown in FIG.
Is supplied.

As a result, the count register 52 outputs the clock signal k (fifth
E) and a count permission signal s (shown in FIG. 5J) supplied from the system control circuit 7 are supplied to an AND gate 51, and a clock signal k as an output signal thereof is counted by a count register 52. .

The count value of the count register 52 is supplied to the comparison circuit 6 and compared with the data T0 stored in the register 4.

As a result, when the data values match, the comparison circuit 6 supplies a data match signal d as shown in FIG.

When the data match signal d is supplied, the system control circuit 7 outputs a control signal c as shown in FIG. 5L.

That is, since the delay time is counted using the same counter clock k, the fact that the count value T0 stored in the register 4 matches the count value of the count register 52 means that the count values match. Therefore, the output of the control signal c is delayed from the input of the start signal a by the time t0 corresponding to the data T0 stored in the register 4.

Therefore, the control signal c is output after being delayed by the delay time adjusted by the external input after the start signal a is input.

Note that any external data for tracking adjustment T2 can also be obtained by manually operating the external switches 8A and 8B.

Of course, the external input circuit 8 can be remotely operated to input the adjustment data T2 to the addition register 33.

<Problem to be Solved by the Invention> In the configuration described above, the time by the reference time delay circuit and the time by the delay time adjustment circuit exist as independent times. Therefore, even if the time of the delay time adjusting circuit is shortened so as to extend only the adjustment range of the delay time while keeping the above two total times, the target time cannot be made shorter than the time by the reference time delay circuit. . In other words, since the minimum time is determined by the reference time, the adjustment range is shifted from the initial value of the time by the delay time adjustment circuit.

<Means for Solving the Problems> In order to solve the above problems, in the present invention,
Delay time adjusting means for changing the delay time by adding / subtracting external data T2 'corresponding to the adjustment time t2 to / from the data T1 corresponding to a predetermined delay time t1 set in advance; and the delay time adjusting means Storage means for storing data T0 corresponding to the delay time t0 'adjusted in the above, counting means for starting counting by input of a start signal, and comparing the stored data T0 of the storage means with the output data of the counting means. A comparison circuit for outputting a data coincidence signal when coincidence occurs, and outputting a control signal with a delay from the start signal by a delay time t0 ′ adjusted by the external data T2 ′. Is compared with the external data T2 '. When the value of the external data T2' is negative, the external data T2 'remains unchanged if T1≥ | T2' | T2 '= - it is made by providing a control means for controlling so as to the value of T1.

<Operation> In this configuration, when the delay time is changed, external data T2 is output by the delay time adjustment circuit 3 based on the time t1 preset in the reference time delay circuit 2 before the start signal a is input. 'Varies the delay time. This external data T2 'is data for tracking adjustment set by being controlled remotely by a remote controller or the like. The data T0 'taking into account the external data T2' is stored in the storage means 4. The external data T2 'can be set to a negative time so that the external data T2' can be shorter than the time t1 set by the reference time delay circuit 2, and the arithmetic circuit 34 '
Thus, time data T0 'obtained by adding and subtracting T1 and T2' is obtained.

Next, when the activation signal a is input, the count circuit 5 starts counting. The comparison circuit 6 compares the data T0 'of the storage means 4 with the output data of the count circuit 5.

When the two data contents match in the comparison circuit 6, a data match signal d is output. The control signal c is output based on the data match signal d. As a result, the control signal c is output after being delayed by the time t0 'corresponding to the data T0' changed by the external input after the start signal a is input.

Therefore, the delay time for tracking adjustment can be easily changed by remote control.

Embodiment Next, a case where an example of a delay circuit according to the present invention is applied to a tracking adjustment circuit of a VTR will be described in detail with reference to FIGS. Note that the same reference numerals are given to the same parts as those in the related art.

FIG. 1 is a diagram showing a specific configuration of a delay circuit according to the present invention. The circuit in FIG. 1 is a delay circuit 1 and includes a reference time delay circuit 2, a delay time adjustment circuit 3, a register 4 serving as a storage unit, a counter circuit 5, a comparison circuit 6, and a system control circuit 7.

The case where the VTR tracking adjustment is performed using the delay circuit having such a configuration will be described below with reference to the timing chart of FIG.

Before the activation signal a is input to the system control circuit 7,
The delay time t1 preset in the reference time delay circuit 2 is measured.

In the discharging circuit 11, the mono-multi-reset signal m shown in FIG. 2B supplied from the system control circuit 7 is normally in the ON state (low level), and the transistor Tr1 operates. There is no state.

When measuring the reference time, first, the system control circuit 7 turns off the mono-multi reset signal, and controls the transistor Tr1 of the discharge circuit 11 to the cutoff state.

As a result, electric charges are stored in the capacitor C0 as shown in FIG. 2C.

At this time, a charge completion signal e (high-level signal) as shown in FIG. 2D is supplied to the AND gate 31 from the collector side of the transistor Tr2 provided in the charge recognition circuit 12.

A high-level signal is supplied to the AND gate 31 until the transistor Tr2 in the charge recognition circuit 12 is turned on (until charging is completed).

When the charging is completed, a low state signal e is supplied to the system control circuit 7 and the AND gate 31.

In this way, only after the transistor Tr1 is turned on and discharged, only until the charging of the capacitor C0 is completed,
And gate 31 is opened.

On the other hand, the AND gate 31 has a counter clock terminal K.
Supplies a clock signal k (shown in FIG. 2E) having a constant period.

The system control circuit 7 sets the register clear signal r (shown in FIG. 2F) to a low state simultaneously with the start of charging of the capacitor C0 (when the mono-multi reset signal m is changed to a low state), and activates the count register 32. State.

As a result, in the count register 32, while the capacitor C0 is being charged, the clock signal k output from the AND gate 31 is output.
Count. Accordingly, as shown in FIG. 2G, the reference time t1 corresponding to the count value T1 can be measured from the count value T1 of the register 32.

Next, data T2 '(shown in FIG. 2H) to be adjusted based on the reference time t1 is supplied to the system circuit 7 from the external input terminal 8, for example, the switches 8A and 8B.

This data T2 'can be remotely controlled by a remote controller or the like, and acts as auxiliary data for tracking adjustment. The external data T2 'is added to the addition register 33'.
Is supplied as data corresponding to the adjustment time t2 '. As shown in FIG. 3, the addition register 33 'is provided with a bit 33a' for indicating whether data is positive or negative. Therefore, T2 'can be externally adjusted to a negative value. Before supplying T2 'to the addition register 33', the count register 32 supplies the data of T1 to the system control circuit 7, and compares the data of T1 and T2 '.

That is, when the value of T2 'is negative, if T1 ≧ | T2' |
If T1 <| T2 '| is unchanged, the system control circuit 7 calculates so that T2' =-T1 if T1 <| T2 '|. Its calculated
T2 'is supplied to the addition register 33'.

Next, the measured value T1 stored in the count register 32 and the data T2 'of the addition register 33' are added / subtracted by the arithmetic unit 34 ', and the data T0' is stored in the register 4 as storage means. That is, the data T0 ′ is
It can be shorter than T1.

Thereafter, when the activation signal a (high signal) is input to the system control circuit 7, the system control circuit 7 sends the register clear signal p as shown in FIG.
Is supplied.

As a result, the count register 52 outputs the clock signal k (second
E and a count permission signal s (shown in FIG. 2J) supplied from the system control circuit 7 are supplied to an AND gate 51, and a clock signal k as an output signal thereof is counted by a count register 52. .

The count value of the count register 52 is supplied to the comparison circuit 6 and compared with the data T0 'stored in the register 4.

As a result, when the data values match, the comparison circuit 6 supplies a data match signal d as shown in FIG. 2K to the system circuit 7 '.

When the data match signal d is supplied, the system control circuit 7 outputs a control signal c as shown in FIG. 2L.

That is, since the delay time is counted using the same counter clock k, the fact that the count value T0 'stored in the register 4 matches the count value of the count register 52 means that the count values match. Therefore, the output of the control signal c is delayed from the input of the start signal a by the time t0 'corresponding to the data T0' stored in the register 4.

Therefore, the control signal c is output after being delayed by the delay time adjusted by the external input after the start signal a is input.

Note that, by manually operating the external switches 8A and 8B, any external data T2 'for tracking adjustment can be obtained.

Of course, it is also possible to remotely control the external input circuit 8 to input the adjustment data T2 'to the addition register 33'.

In this embodiment, the delay circuit according to the present invention is used for tracking adjustment. However, the present invention is not limited to this, and the delay circuit can be used for another purpose of remotely adjusting a delay time.

Although the timing of the data T2 'shown in FIG. 2H is supplied to the addition register 33' at the same time as the data T1 in this embodiment, the timing is not limited to this and may be any time until the activation signal a becomes high.

In this embodiment, the count permission signal s is in the high state when the activation signal a is in the high state (second embodiment).
The count permission signal s only needs to be high before the activation signal a becomes high, and the timing is not limited to this.

Furthermore, in the above-described embodiment, the operation of the VTR and the adjustment of the tracking are not limited to the time by the delay time adjustment circuit, which is the range of the adjustment time, and the time by the reference time delay circuit adjusted at the time of production can also be adjusted. By becoming
The deviation of tracking adjustment can be resolved. Therefore,
The delay circuit according to the present invention is extremely suitable for application to a VTR as described above.

<Effects of the Invention> As described above, since the delay time can be changed by the external input circuit capable of digital processing, the delay time can be easily adjusted even by a remote operation such as a remote control.

Since the external data T2 'can be set to a negative time, a delay time t0' shorter than a predetermined delay time t1 is obtained by adding and subtracting the data T1 and the external data T2 '. It is possible to variably adjust to an optimum value in all adjustment directions.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an example of a delay circuit according to the present invention, FIG. 2 is a timing chart of the delay circuit according to the present invention, FIG. 3 is a diagram showing an addition register, and FIG. FIG. 5 is a system diagram showing an example of a conventional delay circuit. FIG. 5 is a timing chart of the conventional delay circuit. DESCRIPTION OF SYMBOLS 1 ... Delay circuit 2 ... Reference time delay circuit 3 ... Delay time adjustment circuit 4 ... Storage means 5 ... Counter circuit 6 ... Comparison circuit 7 ... System control circuit

Claims (1)

(57) [Claims] 1. An external data corresponding to an adjustment time t2 for data T1 corresponding to a predetermined delay time t1 set in advance.
Delay time adjusting means for varying the delay time by adding or subtracting T2 '; delay time t0' adjusted by the delay time adjusting means
Storage means for storing data T0 corresponding to the following; count means for starting counting by input of a start signal; storage data T0 of the storage means and output data of the count means are compared; A delay circuit that outputs a control signal with a delay from the start signal by a delay time t0 ′ adjusted by the external data T2 ′, wherein the control circuit outputs the data T1 and the external data T2 ′. When the value of the external data T2 'is negative, the external data T2' remains unchanged if T1≥ | T2 '|, and the external data T2' =-T1 if T1 <| T2 '| Control means for controlling the delay circuit.